JPS5948898A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to semiconductor memory and sound devices.

Dynamic type MO8 (kin 11 Zetsumatsu Mono half σ body) RAM
In semiconductor storage devices such as random access memory (Random Access Memory), the first step in improving the quality of the product or box is
I'm thinking of using the fire rescue method.

In order to use the defective bit relief scheme, the device must be able to store the defective address in its memory array.1. An address conveyor consisting of suitable notation t1 means for θ and address ratio soft circuits and additional circuits such as redundant circuits (spare memory arrays) are provided. Ko16 specialist N
When an address signal is inputted to the C memory device rather than the defective pin point cell of that VJ capital, it is detected by the address ratio recovery circuit such as j'1', i in address No. 11 of 7. . Traditionally, a redundant memory cell or defective bit is selected depending on the output of a circuit such as an address ratio soft circuit.

N address conveyors are provided in each of the Y-system and Y-system redundant memory arrays. The address conveyor uses a MOSFET (insulated gate field effect transistor) with a high WlL ratio to flow a relatively large current r to cause the fuse to blow out in order to address the defective address. Since it includes an address defood function, it occupies a large area, and as the number of redundant memory arrays increases, the chip size of semiconductor memory circuits increases significantly. I'll make it bigger.

The inventor of the present application focused on the fact that in a dynamic RAM, most defective bits actually occur in either the X (word) system or the Y (data) thread, and developed the above-mentioned address conveyor. I thought about using my car a lot.

It is an object of the present invention to provide a semiconductor memory device with necessary defective bit relief without increasing the overall chimp size.

Other objects of the invention a1 will become clear from the following description and drawings.

Is this invention below? ■rδ((Explained in 1) along with the implementation sequence.

FIG. 1 shows a block diagram of .mu., one of the features of the present invention.

In the same figure, each circuit block surrounded by dots is formed on a single semiconductor substrate such as silicon by known semiconductor integrated circuit fabrication technology, and has a terminal I10.
,XAO~XAm,YAO~YAn,WE,08
Power is supplied to the BB terminal and the V.a''ss from an appropriate external power supply device (not shown).

In the memory array shown by the circuit symbol M-ARY, known IMO8 memory cells are arranged in a matrix. In this implementation example U, the upper memory cells are arranged in parallel in a pair, and the data nodes D are connected to the input/output nodes.
t, the distribution ICf falls with the two-point method. Then, the memory array M-ARYt, I, the circuit B self-sign XR-ARY,
YR-ARY is used to create redundant memory arrays for X and Y threads.

The circuit symbol Pot is a data line precharge circuit, and the precharge circuit φa. Receive W top, short-circuit complementary data line and D, vo□/2 V
It is constructed by MO8FETlfc which precharges C.

The circuit symbol SA indicates a sense amplifier, and although there are no particular restrictions, the voltage is %i. . and circuit ground potential vS8, respectively]: War switch 11O5FE
It is composed of an 0MO8 (phase j type 40S) launch circuit provided with a T, and its pair of input/output notes are coupled to the complementary data line D.

Timing pulse φ, a1. φpa+ &φ, a2°φ2 are for controlling the upper power switch MO8FKT. Nokwer switch MOEIN
ET is turned off just before precharging, and the complementary data line is set to V with D floating. 0・V level rl
Hold A. Then, by turning on the precharge S MOS FBtiT, the complementary data line is activated.

D or seven V each. Precharged to o/2.

What is indicated by the circuit symbol 0-BW at 7' is the LY RAM switch, which switches the selected complementary data lines to both 1JYJ, 41 . 'f sleeve data iC
Combine with d &.

The circuit B pin number X-ADB indicates the row address buffer and the outer F:i! 1 child X A, 0~X
In response to external address signal r from Am, internal complementary address signal a (J, aQzam, am\C) it hj
,do.

What is indicated by the circuit symbol Y-A D, B is the column address buffer, and the outer Iri group M children YAU~Y
After receiving the external address code from An, I'll send the first one.
l #lil address signal a U l a O~a,
n, a n 7. (form hyasuru〇circuit symbol R-D
(Denoted by 3R is the row address decoder, and internal complementary address information aO+ aO~am,
B mi, (receives and selects word #Ji1 of memory array M-ARY a number rJ [5 1-. is transmitted to memory array M-ARY.
Ru.

Circuit symbol 0-D (The 75 mark in 3R is the column address decoder, internal complementary address signals aO, a
O++an, 'an2, memory array M-AR
Select the Y data line. This (7J7'-ta 6bJ!1 selection signal is the data line escape timing signal φy
The same JLII t is transmitted to the column switch C-5W.

The circuit symbol PO2 is a co-tracing phase, 7Ili
The data line precharge circuit is not particularly limited, but it is constructed with a MOSFET similar to Dobe, which receives the precharge pulse φI) c d and shorts the common complementary data line.

Although it is indicated by the circuit symbol MA, it is a main amplifier and has a circuit configuration similar to that of the sense amplifier SA described above. Timing pulses φ, φ and! 11al
mal and φma21φma2 are the power switch MO8F
ETr? 1IIJ.

Time 'RJr; Shown by self-sign DOB (α, data output buffer is not available, read timing pulse φrw
Then, read data from the MA is sent to the external terminal I10. Incidentally, during convolution, this data output buffer DOB is made inactive (output high impedance) by the start timing pulse φrW.

The diagram shown in the circuit symbol is the data input buffer input, write timing pulse φrW input, external input,
Write data from 71Aj child engineer 10? Tell the common phase data gland. Note that when nlI'l is extended, this data input buffer D is made inactive by the cutting timing pulse φrw.

Each of the above timing blocks is formed by the following circuit blocks.

The circuit symbol TG is the timing circuit of the first year. Although not particularly limited, address 1d a O-
a m r a O ~ an ”f, from the edge detection pulse VC which is the same 1υ [at the change timing of address No. 46 a Qzam and aOzan of b, upper nC
The main timing shown as a representative is the 1st generation. This timing occurs 1]ll! 3T(lJ,, upper +ilr) In response to the write enable signal WE from the IL outer 9 terminal of the detection pulse, chip selection i+-Yumishi]r, the above series of timing pulses are generated in the form JJy, -r.

The circuit symbol AC indicates the address conveyor that must be used for defective addresses 1. The memory circuit includes a memory circuit that stores the memory address, and an address comparison circuit that detects whether a defective address has been specified in the memory.Terminals P1 to P4 are used to store the defective address. .

The circuit symbol As indicates an address selector, which receives address signals aO-am, a, 0-an from address buffers X-ADB and Y-ADE, and selects one of the address signals aO. ~am+aO~ankfl selectively conveys the address conveyor ACE.

What is shown in the circuit symbol OS is an output selector, which sends the selection signal t to the redundant memory array corresponding to the address of the upper address defective address for the entire output of the address conveyor AC.
- Tell.

In the circuit symbol SC, the address selector As (address signal a O~am'l) is +AF, SF! ,
0 \-a nnoshi)zu I'Lk address conveyor AC
At the same time, it is determined whether the output selector 017 transmits the address to the 7L redundant memory array of the address conveyor AC. . From 15 to P8, an entry is made to determine the state of the selector control rj, k, c, h1.

In addition, in this implementation, one address conveyor AO can be selectively assigned X thread or t=t Y system defective addresses.1. (5-year-old, this is '2J Lc, I cut to the redundant memory array:) I did my best 1j7
;:,) L and Gadeki 2).

In Figure 1 and 2, there is a circuit diagram of a concrete example of the main turning point i for the first blunt j'+''.
z). In the following explanation, an n-channel MOS is added to the stand, f, and 40eFJi:T, which are not explained in tf.
FJiiT de Rir. Mutual drawings! il'M,
′? j” <To do M O8F E T times-6^1
'' are shown in lowercase letters.

The memory array M-A R-1 is represented by ~x1, and the phantom half-I jl-arrangement.
lt '2S phase I + 7 data green, 1], switch MO8J1'mTQ, 15 to Ql9 and MOEI
The input/output nodes of the multiple memory cells arranged in a 4I4 configuration are distributed and coupled with a predetermined regularity as shown in the figure.

As shown in 1.4, the precharge circuit PO1,f is connected to the switch MO8F, which is provided between the complementary data lines DD.
Composed by NTQ.

For the sense amplifier SA, the representative pf Jannel MO8FETQ7. Q9 and Ω channel MO8F[T
0MO8 (Saisen type MOS) consisting of Q, 6, and Q8
) It consists of a launch circuit, and seven pairs of input/output nodes are connected to the upper data line D. Further, the launch circuit VC is not limited to nine circuits, but the launch circuit VC is in a parallel form.
Channel MO8FgTQ, 12. Q, 13'li = Heavy drowsiness pressure Vaa is provided with 1 kata, parallel form n-chan colliding MO8FJ! : TQ, 10°Q, 1lk- The ground voltage of the circuit V8° is supplied through δ.

These power switches MO8FffTQlO, Qll
and MO8'FETQ12. Ql, 3μ, is used in common for sense amplifiers OA installed in similar rows.

”6αM OFat F T Q, 10, Q,
The gate of 12 has a sense amplifier SA, ? C activation awn phasing/f ming pulse φ 1. φpal is applied i
l, M OS F E Ta ]11. Q, 13 Kate I/r, Ke, -F', 1f
L-', timing pulse φ, a1, φpa1 and timing pulse φ2. φpa
2 is applied. This 1.1! Reason υ, a t or small tI seeps from the memory cell L IT pressure removes the sense an 7'f'lA, +# When the production is complete, the level of data is converted to the level of the metal IL mysterious small゛Conductance M O8F' J! : TQ, 10, Q]
This is to prevent 2vCyo p'rli NagareyamaQ 1jjtj fIJ Ukononivc, L:p. And upper B [
JC at 2SA (after increasing the bar light by about 41 v + il data IL by l corner operation, the ratio f7 & above 4υSit' k5TQ11.fQ
Turn on 13+L- and get 3"+': 'ILA!
IIυf1−ke speed up. Divided into two stages like this1,
By performing the 1+:q-width operation and cutting of the 1+:q width of the 77-8A, the high level 141j of the A11 Tsukudata Mori is stopped, and the 10 U decoder is read quickly. R-DORtlm, one circuit (
14 words) is shown as a representative,
For example, an n-channel MO8FI that receives address signals IL2 to a6! ! TQ32-Q36 and p-channel MO
Composed of EllF'B3TQ37~Q41 fl, flO
The four word selection signals mentioned above are formed by the NAND circuit using the MoB circuit.

The output of this NAND circuit is CMOB inno (-tae v
The n1 power is inverted at 1 and transmitted to the gates of MO8FE'I'Q24-Q, 27 through the MO8FKTQ28-Q, 31 meetings.

In addition, a 4 signal is generated by a combination of a decode signal formed by address signals aO to a1 and a timing pulse φX.
word line selection timing signal φx00 to φx
ll is applied to the MO8FETs Q24 to Q27 and transmitted to each word line.

Also, between each word line and the ground potential [fi, MO8FE
TQ20 to Q23 are provided, and the above NAN is connected to their gates.
The output of the D circuit is set to be equal to the voltage applied. By doing this, the word line at the time of non-inclusion? It can be fixed to ground potential to prevent a desired word line from being selected.

The above word line is provided with MO8FETQO to Q5 for reset.Reset pulse φpwk
In response, these MO8FKTQ, 41 to Q5 are turned on, thereby resetting the selected word line to the ground level.

Column swing °a-swrs, shown as representative 21
MO8PI is here! 1TQ42. As shown in Q43, the complementary data signal D and the common complementary data lines CD and CD are selectively VC coupled.

Cn et al. (7) The gates of MO8FfflTQ, 42, and Q43 are connected to
<I-Q is supplied. 10 self i+1+, a-oke data 13) 1. The VC between CD and UD is also used for the same precharge times 1FISP02 as above. +TQ, 44 are provided.

These complementary data %dOD, 0DIL are connected to a pair of input/output nodes of the main amplifier MA, which has the same circuit structure as the above 6C sense amplifier SA.

In this embodiment, as a redundant memory play, two word lines are provided for the Y system, and a pair of data lines are provided for the Y system, although this is not limited to one. M.O.
In I3FETQ47 to Q50, the above two words @ are for selecting all, MOBFETQ45
, Q46 is for selecting the above pair of data &. Kokura's MO8FETQ45 to Q48 are
The selection signal from the first node O8 enables selection.

In addition, in this embodiment VC, the address conveyor ACFez 241. (A
O1, Ac2) Prepared.

FIG. 3 shows an actual circuit diagram of the address conveyor.

II): Address QQ on address conveyor 11
It is constructed by a defective address distribution circuit and an address format circuit according to No. 19, and one enable circuit.

In the same figure, VC, t, representatively, one defective 7-address recording circuit, address ratio f-n circuit, and one enable circuit are connected to each other.

Terminals P1 to P4 are also pressure supply terminals for the program to handle defective addresses.
When the terminal P1. P3 has a voltage of y%t ”oa
is given, and the ground potential is maintained at the terminals P 2 and p 4 for 1 time.

In the above enable circuit, the next σ is applied to each circuit.

Load MO8FET Q47 and Tiansan M OS Ju E
TQ.

48 designates the inverter, and the load M OB F Jn
The drain and gate of TQ and 47 are connected to terminal P3. The output of this inverter is connected to the gate of the driver 1!1/1M08FETQ49 which causes the fuse F12 to blow. The drain of this MO8FETQ49)'+1i
A fuse F1 is provided between the i-J-P 1 and the seventh fuse P 2 ic Jm. Also, the gate of the MUSFFjTQ48 is connected to the terminal P4! L. , the above terminal P4 and the turtle voltage V. Between 0 and 0, V is a resistor (2 is provided. Upper iα fuse i!' 1 is not limited to Q protection, but is 4 degrees apart from polysilicon. Predetermined defective address 14) When the terminal P1. Power supply voltage V to P3K. 0 is applied, terminal P2. Since the ground potential of the circuit is applied to P4, the drive MO that blows out the fuse F1
S II' l T Q, 49 turns on and automatically connects fuse F1 to +! l'r! let

In order to determine whether or not this fuse F1 is blown, the following CMOS inverter and latch circuit are provided.
Tebru.

p channel MO8FF! TGL53, Q54 and n
Channel MO8FKTQ55, Q56 is CMOS
Ti't 184 the Nant gate circuit. The p-channel MO8FJIiTQ57, Q58 and the n-channel MO8FgTQ, 59, Q60 are composed of CMOBMOS inverters. A launch circuit is completed by crossing the outputs of these two NAND circuits and one input with each other #f3#-an.

At the drain output of the above M0slPffTQ49, O8FF between the p channel MO8FKTQ51 and the n channel;
M08FETQ5:(.

Q, lie down at the gate of 55, and top M+20
The output of the MOS inverter is V, which is the input of the other Nant gate 111L, which is formed around the latch.
The gates of iO8F'ETQ, 5B, Q, 60 and the same drive MO8FBTQ, 49 are in parallel configuration).
S F is sent to the gate of TQ50. Also,
Although there is no limit to the current temperature, when the fuse F1 is removed from the bath, in order to prevent the drain of the MO8F JB T
OIEFJljTQL, 1 is provided. However, at this time, MO8F'[TQ, LL causes MOS
F'le 1°Q, 50 drain)'1lii and the circuit's dependent point I4L point 1f4J V
It is designed to

And, the output of the Nantes gate of the upper i curved sword is p channel 7 channel m08fJIiTQ61 and n channel, le MUSFJ
7j OM OS inverter 't 1ljl is outputted to enable No. 18 φ.

471 circuits are formed by each of the following circuit elements in one circuit and nine circuits with an address ratio of 11 and a defective address.

Defective address rhyme W circuit 11, MO8FETQ63 L/'LQ65 which is the same as the above f enable circuit, fuse F2, and the frame f' transmitted through the address selector Asx are the father of the address signal a07 and the above drive. M.O.
MO8FETQ, 6 in parallel configuration with 8FETQ64
6 and structure JJy, Sanru.

7 [When entering a certain bad address r, the same as above, 1.
Where is the terminal Pl, P:l? U, pressure voltage 0 is applied to n1 terminal P2. P4VC is given the ground potential of the circuit.

Then, MO8FETQ receives the defective address signal aO
66 is provided, 11, l? υ, if the defective address signal aO to be connected is high level, M OS F Fj,,T
Since Q66 is turned on, the above drive MO8FKTQ, 6
5 is turned off to prevent fuse F2' from melting.If it is low level, MO8FETQ6 (i is turned off, so turn on the above drive! iI/IMO8FETQ, 65xon and set fuse F2' to melt V5[8.

Then, check whether this fuse F2 is #broken or not.4'
Separately from J1 and d), a 5J 0M0FI inverter and a latch 1cil h'i5 are provided. TQ68. to p-channel MO8F. n-channel MOD FET Q, [i9 is CMOS inverter k47j), , M0sFKTc
4L2 constitutes a 70-ding I) force-plane transistor and p-channel 140 S F g T Q 7 (
1.

71 and Q74. Q, 75 and n channel Mui O8F
ET Q. 72. Q73'J and C1,76,Q77
is the CMOS latch circuit digit hZ.

Lido 1/S ratio IIV times 11'i't, direct Taly type j11
1 and Chil also p channel MOS 11' ffi
T Q, 723, Q, 79 and T1 channel, Le M OHF E T Q 80, Q81 and p channel MO8FETQ82, Q83 and n channel M
0rJII'BiTQ84, Q85 and CMOS
By Impatae v2 (6J ruminations are possible).

Satsumi M OS F ff T Q 79, Q 8
The above addressing +9aO is applied to the gate of 0,
The MO8FET Q83 and Q84 gate VCits connected to this and the address signal aO of the inverter J:
v 2 p (applied in reverse order, CM
Of3 latch I! , tl path, the defective address signals aO, aO are sent to the MOS F I! : TQ
78, Q 85 and Q, 81. Like Q82,
p-channel MoGFE3T and n-channel MO8FI
It is applied directly to ICT.

Now, as a bad address, the address is Fi@a O'
If a high level (?ANri 1) r memory δ is set, fuse 1! ``2 is not fused, so the outputs of the O'MO8 launch circuit are aOH high 1/bell and aOU low level. Therefore, n channel Ii40 S F E
TQ, 85 and p channel MOS FET Q
82 is turned on.

And memory access V, input 6, L7? If near address signal aO is low level, p channel MO8F
ETQ, 79 is turned on, and n1 inverter 2 is inverted due to the high level of f1.7℃aO.
08FETQ84 is turned on.

In this way, when both addresses (signals do not match), the n-channel MOEIJ!'ETQ, which is turned on at the top 6 times,
84. Q85 determines whether the output acO is low level (simple 0
)K.

On the other hand, if the 7L7j address signal s, 0 input by memory access is high level, the O8B between n channels
' E T Q, 80 is turned on tl,, inno (-tae v2 inverted aO's a1 novel to p
Channel MO8FKTQ, 83 is turned on.

In this way, when both addresses are in the first place, Kini t:r,, p Chango, Le MOBF, who is on the upper d pion.
ETQ82. Q83 sets the output acO to the low level (logic 1).

For all bits of the address signal, the coincidence output acO to acm (X thread) of the above No. 1 I Novel (iAil [11)]
Also, when 1qa c O ~ a c n ('Y system) and the logic l of enable 1 and No. 1 φ are ↓I et al. 1 again, f
Illff buried circuit (figure bosses) output crab NL, 1N
2, a signal is formed to switch to the redundant memory array.
to at.

It should be noted that the enable signal φ is disabled at the timing 1d φX and φy in order to prohibit the selection of a defective memory array. ′! F, t, enable A signal φ,
The 0 output of the sieve inhibits the switching signal to the upper memory array. In this case, even when there is no defective memory array, acO~a Q 171 (X series) or Ha
c O to a c n (Y system) This is the 7''th point where switching to the redundant memory array stops in kW for address designation in which all logic 1 is set.

In this implementation pHvc, two sets of address selectors AS1. AS2 and two sets of output Sλ selectors O8, , O are provided.

FIG. 4vc shows a circuit diagram of one implementation of one set of address selectors AS1 among the two address selectors.

One set of address selectors [is a unit address selector consisting of two 3-state output circuits and one inverter as described below, the number of which is the same as the number of address ratio 9 circuits in the address conveyor of one set of 'Ic' described above. It is provided.

In this center 1i1MV', there is no limit to δ, but the above unit address selector is 0M08 circuit with relatives δn and 2.
One 3-state output circuit and one 0M0S inverter v3
It is composed of n. One 3-state 11 output circuit is connected in series;
ETQ, 86. Q, 87 and n chaff 4kk408FET
Q88, Q89 and 'T, :I:"t Ijy, Sat
'L le. Upper E MO8FETQ, 86 and Q, 89 gates (-[manual terminals, upper ICMO'5FETQ8
7 and Q88 gate rtc is 101 si inverter iV
Also, complementary control signal CI +01
The application type is rough.

The 3-state output circuit for the song is also the same MODOFETQ as above.
, 90 LQ, 93 invites, a n, le,, soshi, upper i own MO8F ET [9tJ toQ, 93 (1
) Human power yM + is applied to the gate, and the above M O8F Ii
i T C+, 91, Q, 92 gates [Tttll l'l 1A C and cl are applied, which are the opposite complements of the above case.

Now, the upper 11th system + 1jt14th Q is at a high level Q
, but Louleherna et al., MO8F [TQ87 , Q,88
is turned on and the signals from the input terminals 47 and the like are transmitted to the output terminal OUT.

In addition, when the open side 1 times CI is set to a high level, MQSFFtTQ91, Q, and 92 are turned on, and the input terminal ay is output from the input terminal ay to the output terminal OUT.
I will tell you.

Although sometimes there are no restrictions, in this implementation sequence, the address selector AStU, the address conveyor AC3 mentioned above,
It corresponds to

Above input terminal aX [H, address buffer X -ADB
An address signal from ill is applied to input terminal a7[[
, so that the address signal from the address buffer Y-ADB is applied. The above output store child out
The output signal from the above-mentioned f'C address conveyor AC
, to the address ratio collection circuit shown in FIG. 3. FIG. 5A shows a circuit diagram of an embodiment of a set of output selectors O8a.

4M with this output selector OB, f-4, CM OS circuit
Two 3-state output circuits with b5C and two CMOS
It consists of an inverter and a bootstrap circuit.

This 3-state output circuit is constructed by combining the 3-state output circuit shown in FIG.
Enter. That is, one of the three-state output times 8trz,,P
Channel MO8II'ETQ94, Q96 and N
Channel M OEI F ) U T Q9 @ + Q
et 1 IC-C Tsumenari-yiL, 3 on the lag side
Status output circuit fIX P, MO8FET Q
981 Qes and (1 channel MO8FgTQ,
I.O.Q.

It is composed of Q, to+, and C.

Output selector O8 of the implementation column of C, &p,'+
When the ft1l extension+j<g number CI is low level and the output signal NK from the address conveyor AC is high level, the high level output signal YO is supplied to the redundant memory play of the Y thread. This 1j, MO8F'ET (J
, 4s+Q4g are turned on, and the redundant memory 1/i of the Y thread is replaced by 1. With this IC Karushi,
i1+1'', number 0, is at a high level, and the address conveyor AC is at a high level.

(D IJj force (fl No. IN) is at a high level, and the output signal at a high level is supplied to the bootstrap rough depression.

This bootstrap circuit receives a high-level signal r, and forms an output signal XO,'i of In,QX high-1 voltage (v (voltage higher than -LL of JO)) to provide redundancy for the X system. Output to the memory array.This output No. 1B XO.

fl, MO8FJI! The word fiIVc of the redundant memory array of the X system is transmitted through the 1TQ4sk valve. At this time, an X-based redundant memory array will be used. By providing the bootstrap circuit in this manner, the gate of the switch MO8FET of the memory cell is provided with a voltage of 111. Pressure can be applied.

Therefore, the data on the data object is transferred to the switch MO8FET.
memory sensitivity without level loss due to threshold voltage (MO8
I can tell you the answer and capacity. In addition, MO8FETQ4
11, when the output 1d OX1 becomes high level due to the capacitance between the gate electrode and the channel, @, MO
8Fij TQ48 gate voltage increases. Therefore, the level t of the output key signal XO can be transmitted to the 11th word line.

There are two sets of selector control circuits (So, 2) in this embodiment, although there are no particular restrictions on the number of selector control circuits SC.

sc,) is provided.

and "(Figure 6 shows the selector control times de ii S
cl t/,,r - A circuit diagram with six columns is shown.

Right here, N channel MC18FBiTQtoz or Q'ttg, P channel M OFJ P' H
T Qtis 4 I LQ g + 7 Youth 1? '3
．． The selector control circuit SCI is connected to the resistor R4 or It@K, j't. This selector control circuit has +hl, and! Since 1' and r are the same as the enable circuit in FIG. 3, the description will be omitted.

This fruit is Lore IIVc, terminal P6r high level.

Terminal Ps? When the fuse F3 reaches the low level, fuse F3 is halved.
reached the Yuhai level. Therefore, the γ dress selector A
S, r! , Address No. 18 ax (aQ ~ am)'
Inform f-1 tress conveyor AC+. If each address ax at this time matches the invalid address, the address conveyor AC is a high level output IFj.
N+2 output selector 08IK output. Deba selector O8, upper control cape signal 0. In response to the high level of the signal XO and the high level of the output input signal IN, the high level signal XO is fully output. As a result, the X-system defective bits can be switched to the X-system redundant memory array.

For example, if terminals P5 and P are all at low level TTL, then (F3 will not be blown out. Therefore, the control signal Oi
becomes low level, and conversely to the case described above, defective bits of the Y system are switched to the redundant memory array of the Y system.

In this implementation 1+1J, one address conveyor is used by switching to the Xi redundant memory array or the Y-series redundant memory array as needed. It can also be used for memory arrays. Once upon a time, Tokuchi Kimitsu 7/i! i
Just by using a 2m address conveyor for two sets of f:n redundant memory arrays,
Set address conveyor tray x thread Y thread one piece at a time, or
It can be used for two types: system or Y system. Half-length diary 1
Since many defective memory arrays that actually occur in ,0 devices tend to be biased toward x, Both systems, Y, (j) [It is also possible to repair defective memory arrays that occur.

Therefore, by using fewer address conveyors, it is possible to effectively repair defective memory arrays and to reduce the chip size.

Note that since the area occupied by the selector relative to the address conveyor is small, an effect of zero improvement in yield can be expected.

Furthermore, when the selector is not operated, it is desirable to set the state of the defective 11111K selector, which is gradually changed depending on the configuration of the memory in section 7. The data line is made of aluminum, and the defective thread on the data line side is word line 11! It's more expensive than 'I's defective book, so
If you can't move the selector, press #! Set it on the side. When the sister fuse F3 of the selector controller A of the selector controller A is not melted, the selectors AS and O8 are set to select the redundant memory array of the Y thread. In this way, only a small number of fuses can be used when switching to a redundant memory array.

In addition, by connecting a pair of complementary theme lines and a co-curricular data line R to the precharge operation of the memory array, approximately V can be obtained. , /2, so like conventional dynamic RAM, the voltage ranges from U volt to V. . Precharge MO8FE has a smaller level change compared to the one that charges up at level 1.
Gate of T [υ1 pressure 〒normal logic level (Voo)k
Since it can be turned on in a sufficiently unsaturated state even when used, the precharge operation is very fast, and low consumption can be achieved with low power consumption.

Then, like the above 6, set the precharge level to about V.

Since it is necessary to set the intermediate level of 0/2, even if the memory cell's switch M is
Even if the built-in logic level (voo) k is used with the gate voltage (word line selection voltage) of the O8FET, it can be turned on in a sufficiently non-t; In this way, the information arrangement and the entire reading of the 6 capacitors can be stopped without using the bootstrap voltage tray.

1'fCz BfG reference voltage tar, memory cell is H selection 11. Since the charge level of one of the data glands is not used, there is no need for a dummy cell for forming a read reference voltage as in a conventional dynamic RAM.

This invention does not have the aforementioned embodiment l+1IVc limitation awn t1-.

Alternatively, the output selector may be constructed as shown in FIG. 5B.

Deba selector F of this implementation row (X P channel Mo
5it'g'rQ,,, I Q+*o −
Qtg't, Qtts t N-channel MOS PET Qtts, Q124 + Qi
zs +QI211.0M0S It I'V
6, IV7, IVs and a bootstrap circuit.

The appearance of this output selector #lf@ is the same as the output selector shown in the itJ1 younger brother 5A diagram, but when the memory array is not used redundantly, the redundant memory array will definitely not be selected. Control an by j) using the enable signal φk as follows.
MO8FETQ+*s and Qrstr are newly provided.

Also, in the first column of the front array, the address selector AS
One selector control circuit SO+tl'' was provided for the set consisting of 1 and output selector O8, and another selector control circuit sa,'2 was provided for other similar groups. However, the arrangement may be such that a selector control circuit is provided for each selector.

The number of address conveyors is n'f provided for X thread and Y thread.
It is sufficient that the number of memory arrays is less than the total number of ft memory arrays. An address selector and an output selector are provided corresponding to the address conveyor.

'E7csThe present invention can be widely used in the RAMP-configured cow's body t-inertia device, regardless of its specific circuit structure.

[Brief explanation of drawings]

Figure 151 is a block 11 of a practical example of this invention. Figure 2 is a circuit diagram showing its concrete implementation.
Figure 3 shows the address conveyor's -'A%+V'
J? The circuit diagram shown in FIG.
8"J k is the circuit diagram shown in FIG. 5A, and FIG. 5B is the circuit diagram showing the implementation of the output selector 111. The figure is a circuit diagram of one implementation of the selector control circuit. ~
ADB...Row address buffer, a-svt...
Cassim switch, 0- A I'1 B... Column address buffer, R-, r) OR... Row address buffer, C-, I) (! 1t... Force, address decoder, PO2...・Precharge circuit, MA...
・Main amplifier, TG...timing generation circuit, DO
B...Data output buffer, D, TB...Data output buffer, AC...Address conveyor, AS...
Address selector, O8... Output selector, SC...
・Selector control circuit. Figure 3-617- Figure 5A

Claims (1)

[Claims] 1. An address selector that receives an X or Y address signal r and selectively outputs it, and this address selector ? Il
- an address recording means for recording the passed defective address signal, and an address ratio soft circuit for comparing this defective address signal with each memory operation address and detecting whether a defective address has been selected. An address conveyor, an output tray holder of the address conveyor, a redundant memory array corresponding to the defective address, and a selector for selecting the redundant memory array corresponding to the defective address. 2. The above-mentioned defective address (No. 74) shall be used to write and record the defective address signal depending on whether or not the fuse means melts or not. 'f: f time and time m 16? and Y yarn, respectively.
Cow conductor record 11 device α with beat description.