JPS5947262B2 - Phase difference measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for measuring a phase difference (time difference) between a reference signal prepared in advance and a signal to be measured coming from the outside, such as a verbal run signal.

When measuring the above-mentioned phase difference, conventionally, as shown in FIG. up to α
It is designed to measure the temple area.

However, since the signal under test a is generally a signal arriving from the outside, its amplitude value is often not constant and varies. Therefore, when the amplitude value of the signal under test a increases as shown by the dotted line, its shaped wave becomes as shown in Figure 1c, and the rising or falling portion of the shaped wave b changes over time △ and △. change only by '. Therefore, when measuring the time to the rising edge (falling edge) of a shaped wave as with conventional devices, it is difficult to accurately measure the phase difference because the measured value changes according to the amplitude change of the signal under test. I can't do that. The present invention provides an apparatus that always performs accurate phase difference measurement regardless of amplitude changes of the signal under test by measuring the time until the amplitude maximum value (minimum value) of the signal under test.

First, to explain the principle, when a clock pulse is passed for the duration TH of the shaped wave b as shown in Figure 1 d, and the number of clock pulses d is counted, the counted value is proportional to the duration TH of the shaped wave b. .

Therefore, the repetition frequency of the clock pulse d is shown in Fig. 1 e.
When the frequency is divided by 1 and counted, the counted value becomes the duration TH- of the shaped wave b, so the amplitude maximum value time of the signal under test a is determined from the rising edge of the shaped wave b. It is equivalent to counting up to . Therefore, after counting from the reference signal to the rising edge of the shaped wave b using a clock pulse with the same period as the clock pulse d, the duration TH of the shaped wave b is counted using a clock pulse e whose frequency is divided by 1, and each count value is By adding up, the amplitude maximum value time T of the signal under test a is obtained. The time until Since the amplitude maximum value time TO is always constant regardless of the amplitude change of the signal under test a, accurate phase difference measurement can always be performed even when the amplitude of the signal under test a differs.
Next, a specific example of the present invention will be explained with reference to FIG.

In Fig. 2, the reference signal (Fig. 3 f) is output from terminal P1.
is sent, a shaped wave g of the signal under test is sent from terminal P2, and a clock pulse (h in Figure 3) for counting the phase difference between the reference signal and the signal under test is sent from terminal P3. be done.

The shaped wave g is sent to the set terminal of each of the JK flip-flops 1 and 2, and at the same time is sent to the JK flip-flop via the inverting amplifier 3.
It is also sent to the flip-flop 4 set terminal.

Each JK flip-flop 1, 2, and 4 performs an inverting operation each time a pulse is applied to its trigger terminal when its reset terminal is high, and its Q output is low when its reset terminal changes from high to low. level, the Q output is set to high level. The reference signal f sent from the terminal P1 is sent to the trigger terminal of the JK flip-flop 4.

At this time, since the reset terminal of the JK flip-flop 4 is at a high level, the Q output is inverted to a high level (FIG. 3, 1) and remains at a high level until the rising edge of the shaped wave g. The inverted output i of the JK flip-flop 4 is sent to the NAND circuit 5 together with the clock pulse h, and during the duration of the high level of the inverted output 1, the clock pulse (
Figure 3 j) is sent. This clock pulse j is NAN
It is sent to one input of NAND circuits 7 and 8 via D circuit 6. The other inputs of the NAND circuits 7 and 8 are led to the Q and Q outputs of the JK flip-flop 1, respectively. At this time, JK flip-flop 1
Since the reset terminal is at a low level, the Q output is at a low level and the Q output is at a high level. Therefore, clock pulse j
is sent through the NAND circuit 7 to the addition terminal of the reverse counter 9, and the clock pulses j are sequentially added and counted. When the shaped wave g is sent out, the Q output of the JK flip-flop 4 is set to a low level by its rising edge.

Therefore, the clock pulse h cannot pass through the NAND circuit 5, and the output of the NAND circuit 5 is held at a high level. Also, during the duration of the shaped wave g, the JK flip-flop 2's reset terminal is kept at a high level, so that the JK flip-flop 2 performs an inverting operation in response to the clock pulse h. Therefore, during the duration TH of the shaped wave g, a pulse train with the repetition period of the clock pulse h divided by one is sent out, as shown in FIG. 3k. This frequency-divided pulse train k is led from the NAND circuit 7 through the NAND circuit 6 to the addition terminal of the reversible counting circuit 9, where it is added and counted. Therefore, since the reverse counting circuit 9 adds and counts the clock pulse train j and the frequency-divided pulse train k, the counted value is calculated from the reference pulse f to the center position T of the shaped wave g, as described above.

In other words, it is equal to the time T until the amplitude maximum value time of the signal under measurement. Next, the phase difference between the reference signal f and the shaped wave g (
Consider the case where the reference signal f'' is located within the duration TH of the shaped wave g'' as shown in FIG. 4, where the time difference) becomes relatively small. In this case, first, the JK flip-flops 1 and 2 are activated by the shaped wave gl sent from the terminal P2.
After each of the set terminals becomes high level, the reference signal f' is sent out from the terminal P1.

Therefore, the JK flip-flop 1 is inverted by the reference signal f'', causing the Q output to be at a high level and the Q output to be at a low level.On the other hand, the JK flip-flop 2 is inverted by the reference signal f'', and the Q output is at a low level. The inverting operation is performed by the inverted clock pulse, and a one-frequency pulse train is sent out.

This frequency-divided pulse train kl passes through the NAND circuit 6
It is sent to one input of D circuits 7 and 8. In the JK flip-flop 1, the Q output remains at a low level and the Q output remains at a high level until the reference signal fl is sent out, and the reference signal f''
Q. is transmitted until the falling portion of the shaped wave gl. The Q output levels are each inverted. Therefore, the frequency-divided pulse train k'' sent from the NAND circuit 6 is sent to the addition terminal of the reversible counting circuit 9 during T1 from the rising edge of the shaped wave g'' to the reference signal f'. After the reference signal f'' is sent out, the signal is sent to the subtraction terminal during T2 until the falling edge of the shaped wave g'. Therefore, the reversible counting circuit 9 performs addition counting during T1, and performs counting during T2. Since performs subtraction counting, the result is equivalent to performing subtraction counting for T (!, twice I (2Tφ,)) from the reference signal f' to the center position T of the shaped wave g'. As for the counting pulse, since the one-frequency pulse train k' is counted as described above, the counted value (absolute value) is the time Tφ from the reference signal f' to the center position T of the shaped wave g'. As explained above, in the present invention, the phase difference (time difference) with respect to the amplitude maximum value (minimum value) time of the signal under test is measured, so that , it is possible to always perform accurate phase difference measurements without being affected by amplitude changes of the signal under test.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the principle of the invention, FIG. 2 is a block diagram showing an embodiment of the invention, and FIGS. 3 and 4 are waveform diagrams for explaining its operation. 1...JK flip-flop (comparison circuit), 2
・・・・・・ JK flip-flop (frequency divider circuit), 3
...Inverting amplifier, 4...JK flip-flop (gate signal generation circuit), 5...NAND circuit (first gate), T... Nando circuit (
(second gate), 8... NAND circuit (third gate), P1... connected signal input terminal, P2...
...Measurement waveform input terminal, P3...Clock pulse input terminal.

Claims (1)

[Claims] 1 Gate signal generation that generates a gate signal only from the reference signal to the start of the measured waveform when a reference signal is input first and then a measured waveform whose phase difference with this signal is to be compared is input. a first gate that allows a clock pulse to pass only during the period in which the gate signal exists, and a frequency dividing circuit that generates a wave divided by half the frequency of the clock pulse only during the period in which the waveform to be measured exists; If the reference signal is input before the waveform under test, the first
When the measured waveform is input before the reference signal, a first output is first generated, and when the reference signal is input, the first output disappears and a second output is generated. a comparator circuit configured as such, a reversible counting circuit having an addition terminal and a subtraction terminal; It consists of a second gate that leads to a terminal, and a third gate that leads the clock pulse or the frequency-divided wave that has passed through the first gate by the second output of the comparison circuit to the subtraction terminal of the reversible counting circuit. Phase difference measuring device.