JPS5946094A - Method of producing conductor circuit for printed circuit board - Google Patents
Method of producing conductor circuit for printed circuit boardInfo
- Publication number
- JPS5946094A JPS5946094A JP15609382A JP15609382A JPS5946094A JP S5946094 A JPS5946094 A JP S5946094A JP 15609382 A JP15609382 A JP 15609382A JP 15609382 A JP15609382 A JP 15609382A JP S5946094 A JPS5946094 A JP S5946094A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- plating
- circuit pattern
- printed circuit
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
不発明はプリント回路板用勇坏回路の製造力ll÷に関
L、特に…′気メッキ処理によ(用+jl路パターンを
形成するフルアディティブ法によるフリント回路板用導
体回路の製造方法に保々。[Detailed Description of the Invention] The invention relates to the manufacturing ability of flint circuits for printed circuit boards, especially for flint circuit boards by full additive method of forming circuit patterns by air plating process. A method of manufacturing conductor circuits.
近年、プリント回路数用4体1す1路の・縛危方チとし
て、銅張積層板全出兆基拐(7た一リブトラクチイブ法
によるエツチングで回路パターンケ形成ずゐ万浩や、メ
ッキ法に工υ橢…°性金属ケ」11.相びセろアディテ
ィブ法で回路パターンケ形成し1い6゜これら従来の方
法による製造V(おいて5回路パターンの仕よけ金メッ
キは、パターンの形成後■Iコ気メッキにより銅等の上
に施芒]1.るのが一般的である。このためf115分
的に仕上げ金メッキk bluす除マスク全用いるが、
可極としでの・・ターンが必沙でめり、(爪立パターン
の仕上げメッキは乾式メッキ法である蒸着万江等マ′[
2か形成でへないといり欠点を刹していた。In recent years, copper-clad laminates have been widely used as a 4-piece 1-in-1 bonding method for printed circuits, such as the formation of circuit patterns by etching using the 7-piece rib tractive method, and the plating method. 11. Form the circuit pattern using the additive method 1 and 6 Manufacture by these conventional methods It is common to apply gold plating on copper, etc. by using plating.For this reason, a complete gold plating mask is used for finishing gold plating.
As for the turn of the pole, the turn is very sharp, (the final plating of the nail stand pattern is done by dry plating method, evaporated Mane Toma' [
2. It had a shortcoming in formation.
不発明は上記欠点全解消し、乾式メッキによらず、湿式
メッキ法である電気メッキ法により、孤立パターンの仕
上げ金メッキ金泥すことケ可能にしたものである。The present invention eliminates all of the above-mentioned drawbacks, and makes it possible to perform finishing gold plating of isolated patterns using electroplating, which is a wet plating method, instead of using dry plating.
N下図面とともに不発明の実施例VCついて詳細に説明
する。An uninvented embodiment VC will be described in detail with reference to the drawings below.
第1図は、従来の製造における部分仕上げ釜メッキ1a
’(i7施したプリント回路板用導体回路の101面を
示す略図で、第2図はX発明による115分仕上は金メ
ッキ1a(i7施しfcプリント回回路用用導体回路H
jf面を示す略図である。Figure 1 shows partial finishing pot plating 1a in conventional manufacturing.
(This is a schematic diagram showing the 101st surface of a conductor circuit for printed circuit boards applied with i7. Figure 2 is a schematic diagram showing the 101st side of a conductor circuit for printed circuit boards applied with i7.
It is a schematic diagram showing a jf plane.
不発明のに!遣方法は、金属板上に回路パターンとなる
部分ν〕、外の表iW+全絶縁材料でめるレジスト剤で
マスク1〜、さらに別に製造した穴明された高分子フィ
ルムのマスクを被せ、仕上は金メッキ1b全金Ml上に
電気メッキVこ、lニジ形成する。次に高分子フィルム
のマスクを取り除き、仕上げ金メッキ1bをれた金属板
を可気銅メッキ法により銅パターン2を形成する。次に
非導屯性尚分子材料で出来たベース基板4に接着剤3を
ロールコータ−で塗イ1jシ、仮乾燥後 この接7n剤
ろゲh’+It t、 * iuと、先に形成した鋼パ
ターン2の101を台ぜ、加熱1〜、回路パターンであ
る仕上は金メッキ11)と銅パターン2をベース基板4
に接7tf転げして、孤立しに部分仕上げ金メツキ1b
i有するフリント回路J目導体回路を得ることができた
。Even though it was uninvented! The method is to place the part that will become the circuit pattern on the metal plate, mask 1~ with a resist agent made of iW+all-insulating material on the outside surface, and then cover with a separately manufactured mask of a polymer film with holes, and then finish. Electrolytic plating V is formed on the gold plating 1b all over the gold Ml. Next, the polymer film mask is removed, and a copper pattern 2 is formed on the metal plate with the final gold plating 1b by vaporized copper plating. Next, use a roll coater to apply the adhesive 3 to the base substrate 4 made of a non-conductive molecular material, and after temporary drying, the adhesive 7n, h'+It t, * iu, is formed first. Place the steel pattern 2 101 on the base board 4, heat it 1~, finish the circuit pattern with gold plating 11) and place the copper pattern 2 on the base board 4.
Roll 7tf in contact with it and partially finish gold plating 1b in isolation.
It was possible to obtain a flint circuit J-th conductor circuit having i.
不発明は以上詳ユホした如く製造されるので、孤立した
回路パターンの仕上はメッキが湿式メッキ法により製造
o1面となり、量産がし−やすくなり製造コストも低下
した。Since the invention is manufactured as described in detail above, the finishing of the isolated circuit pattern is done by wet plating, which makes mass production easier and reduces manufacturing costs.
第1図は従来の製造に卦ける1915分仕上は金メッキ
1aを施したプリント回路用2H坏回路の凹面を示す略
図で、第2図は本発明による%l+分什土は金メツキ1
b全力+j L、たプリント回路用膚捧回路の11ノ1
面を示す略図である。
+a、Ib・・・・・仕上げ金メッキ
2・・・・・・金回パターン 6・・・(及后バリ4
・・・・・・ベース基板Fig. 1 is a schematic diagram showing the concave surface of a 2H folding circuit for printed circuits with a gold plating 1a finish of 1915 minutes according to conventional manufacturing, and Fig. 2 shows a concave surface of a 2H folding circuit for printed circuits with a gold plating finish of 1a according to the present invention.
b Full power + j L, 11 No. 1 of the skin dedicated circuit for the printed circuit
FIG. +a, Ib...Finish gold plating 2...Gold plating pattern 6...(Afterwards burr 4
・・・・・・Base board
Claims (1)
機甲導体回路の製造において、2#甫性金属の表面上に
回路パターンとなる部分以外の表面を、絶縁材ネ’)T
あるレジスト剤でマスクする工程と、レジスト剤でマス
クされ” 導7m、 性@Hのレジスト創面側の表面に
、商分子ノイルム等で選択的に穴あけされた別のマスク
材を破ぜでマスクし。 穴明けされたH41s分のみに電気メッキ等により金等
の仕上げメッキを梼車性金域の表面に繍すL程と、金等
の仕上げメッキを施した4厄住金属に銅等の導通用回路
パターンfc亀気メッキにより形成した後、形成1ノt
だ回路パターンを回路基板のベースとなる烏分子材料に
接着剤を介して、高分子材料上に回路パターンを形成す
る工程とを有するプリント回路板用4坏回路の!!造力
の。[Claims] In manufacturing a printed circuit armor conductor circuit in which a circuit pattern is formed by electroplating, the surface of the 2# conductive metal other than the part that will become the circuit pattern is coated with an insulating material (T).
There is a process of masking with a certain resist agent, and then another masking material with holes selectively drilled with commercial molecular Neulum etc. is masked by tearing on the surface of the wound side of the resist masked with the resist agent. . Finishing plating such as gold is embroidered on the surface of the metal area of the trolley by electroplating only on the hole H41s, and conductive metal such as copper is applied to the metal 4 which has been plated with finish plating such as gold. After forming the general circuit pattern by FC turtle plating, 1 knot is formed.
A four-layer circuit for printed circuit boards, which includes the process of forming a circuit pattern on a polymeric material by applying an adhesive to the polymeric material that serves as the base of the circuit board! ! of creative power.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15609382A JPS5946094A (en) | 1982-09-08 | 1982-09-08 | Method of producing conductor circuit for printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15609382A JPS5946094A (en) | 1982-09-08 | 1982-09-08 | Method of producing conductor circuit for printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5946094A true JPS5946094A (en) | 1984-03-15 |
Family
ID=15620152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15609382A Pending JPS5946094A (en) | 1982-09-08 | 1982-09-08 | Method of producing conductor circuit for printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5946094A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04104502U (en) * | 1992-01-23 | 1992-09-09 | 義晴 橋 | ruler scale |
US6167834B1 (en) | 1986-12-19 | 2001-01-02 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
US6399514B1 (en) | 1991-06-27 | 2002-06-04 | Applied Materials, Inc. | High temperature silicon surface providing high selectivity in an oxide etch process |
JP2010118633A (en) * | 2008-11-12 | 2010-05-27 | Samsung Electro-Mechanics Co Ltd | Printed circuit board having buried solder bump and manufacturing method therefor |
-
1982
- 1982-09-08 JP JP15609382A patent/JPS5946094A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6167834B1 (en) | 1986-12-19 | 2001-01-02 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
US6399514B1 (en) | 1991-06-27 | 2002-06-04 | Applied Materials, Inc. | High temperature silicon surface providing high selectivity in an oxide etch process |
JPH04104502U (en) * | 1992-01-23 | 1992-09-09 | 義晴 橋 | ruler scale |
JP2010118633A (en) * | 2008-11-12 | 2010-05-27 | Samsung Electro-Mechanics Co Ltd | Printed circuit board having buried solder bump and manufacturing method therefor |
US8039762B2 (en) | 2008-11-12 | 2011-10-18 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board having a buried solder bump and a circuit layer flush with an insulating layer |
US9021690B2 (en) | 2008-11-12 | 2015-05-05 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing printed circuit board having buried solder bump |
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