JPS5945695A - Ic memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to electrically erasable read only memory circuits (EEPR).
OM) + related to improvements in IC memory.

(b) Technology Background With the development of semiconductor technology, a variety of IC memories have been provided. Read-only memory circuit/element (ROM)
It is a nonvolatile memory that can read out the stored contents any number of times, and the memory will not be lost even if the power supply is cut off for a period of time.

ROM 1 also provides the transfer of numbers, for example, for applications that do not need to be rewritten once stored, such as character donot data, and for programs for initialization operations in systems, such as the frequency of rewriting. There are some methods that can be applied to applications that require a rewrite function even at long time intervals, although the number of rewrites is small. In this case, a normal memory is provided for the latter (it operates as a ROM during write/read operations, and the stored contents are erased by a different operation and new data is written). EEP that can
It is related to ROM.

(C) Conventional technology and problems Conventionally, EEPROM has a finite number of 1, preferably 10
It has a life including 1N of 1 to 1011 times, and its limit Mv
l! Memory operation is maintained with iF. Therefore, when the EEPROM is incorporated into a system and used, the write-in frequency is extremely low and there is no need to be aware of the 1-input life, so the doubling cycle is not managed at all. However, there is no problem with it.
Compared to this, if there is a relatively high number of writers, E EPR
Set up a circuit to manage OM and count it.
When the delay reaches a limit of Jt, the EEPROM is replaced in order to avoid abatement that is likely to occur later. FIG. 1 shows a block diagram of a conventional EEI ROM equipped with a write count management means. In the figure, 1 is a first control section, 2 is a second control section, 3 is a first storage section, 4 is a second storage section, 5 is a counter, and 6 is a comparison section. The first constraint 1 part l receives address data ADD1, constraint +1 (1 signal C0NTl and W
In addition to controlling the write operation size or the read operation of the first storage unit 3 by giving E, address data ADD2 and control (i\ number C0NT2 are given to control the number of writes to the first storage unit 3). Control is performed to write/read the counting data DATA2 in a partial area of the first storage section 3.The second control section 1 2 receives the write enable Gogo WE from the first control M section 1. CL to the old count data held by counter 5 each time.
Send K and add l to argument data DATA.
2 is sent to the first control section 1.

In this way (the first control point δV part 1 is DATAI and DA
TA21 gets stuck in each n different area of the first storage unit 3-
\The first storage unit 3 that performs write and read control is an EEPR
It is a storage section configured by OM and performs convolutional reading under the control of the first control section 1.

The second memory section 4 is constituted by, for example, a mask-shaped memory circuit (ROM) dedicated to bladder extraction, which stores the management value of the number of times of writing. Of course, it is a fuse type ROMt or EEPR which has been written in advance by an appropriate A writing means externally.
It may also be configured by OM.

No matter how many fL+, for example, when the write count management value is 103 times, the 10-bit data of 1111101000 is held, and when the write count is 10' times, the 17-bit data of 11000011010100000 is always held.

The above-mentioned second control [2] sets the initial state when the power is turned on, and then performs the first recording.
For each WE signal received from
Each time the DATA 2 is stored in the storage section 3, it is sent to the comparison section 6 under the control of the first control section 1. On the other hand, the control unit 1 signal C0NT3) of the second control unit 2 is therefore the comparator 6.
Compare T A 2 with the management value received from the second storage unit 4 and output the judgment result from the output terminal (OUT), for example, DAT.
A2 (When it is a management value, it sends a high level to enable writing; when it is a management value, it sends a low level to indicate that writing is not possible, and sends O; the first storage unit 3 has reached the specified number of writes. In this way, in the past, various external additional circuits were provided in order to compare the count data of the number of writes with the control value and manage the first BC according to the EEPROM1. In addition to requiring extra space, it was necessary to send out DATA2 together with the general-purpose data DATAI for inspection in order to grasp the proximity of the count data DATA2 to the control value.

In addition, although not shown in the drawings, it is necessary (therefore, it is necessary to provide a separate selection means to separate DATAI and DATA2).

(dl Purpose of the Invention Purpose of the Invention) A circuit for processing the number of input voltages and an EEPROM for storing general-purpose data are provided on the same board to eliminate wasted mounting space and to store multiple management values
In addition to making it easier to understand the state of proximity to the final control value by remembering and collating it, it is also possible to separate general-purpose data and counting data into separate circuits so that both data are output to the same terminal. The present invention aims to provide an IC memory based on EEPROIVN which has easy management means without any problems.

(e) Structure of the Invention This purpose (J same--the first to store general-purpose data on the substrate 10)
storage means, means for counting the number of writings in the first storage means, second storage means for storing the number of writings (MF') for counting the number of writings (Koharu Erito's management value), and counting by means for visiting the counter V means. A third MF' storage means for storing data, a means for comparing the count data of the third storage means with a plurality of management values in the second storage means t, and the first and third storage means The second storage means is configured with a fixed or electrically erasable read-only storage circuit, and each time the control section receives a hanging signal from the first warning means, The counting means adds the old count data l in the third storage means to update the total V data, and actually sends the argument data to the comparison means to compare it with the control value and send out the judgment result. This can be achieved by providing an IC memory characterized by the following characteristics.

(f) P, Ming's Embodiment"L, An embodiment of the sewage invention with reference to the drawings 5
explain. FIG. 2 shows a block diagram of an IC memory consisting of an EEPROM 1 equipped with a write count control means according to an embodiment of the present invention. In the figure ζ, Ia is the first control section,
2a is the second control section, 3 is the first storage section, 4a is the second storage section, 5 is the counter, 6a is the comparison section, and 7 is the second section 1f!
Department. Note that lO indicates the same substrate area in one embodiment of the present invention. A first storage unit 3 having co-traced codes as in FIG.
and counter 5 are equivalent to the conventional ones and have common functions. At this time, the first recording section 3 receives only the excitation control of the general-purpose data DATA1 from the first control section 1a, and the first recording section 3 receives only the excitation control of the general-purpose data DATA1 at 1! EEPR not subject to motion control
OMEN Sei-Koyoru I) A, T A 1 operates as a dedicated memory. Other first i1 control unit 1aS second control unit 2a.

The second extension part 4a and the comparison part 6a also have a basic function similar to that of the conventional component having O.1 without a suffix, and perform partially different operations.

The first control unit 1a outputs the address data ADDL control signal C0NTl and write enable WEI to the first storage unit 3 according to the data received from the bus, and outputs the general-purpose data DA.
Write TAI, give ADDI and C0NTl, and write Fl! Perform a river movement.

The @2 control unit 2a performs the initial state l', '' constant operation and the total IHt'i control operation in response to input of the knowledge source as in the conventional case.

However, unlike before, the old counting data (TG EI) ROΔ・
The argument data is obtained from the third storage unit 7, which is a memory dedicated to argument data, and is set in the counter 5, and every time the WEI is received, the clock CLK is sent to the counter 5 and incremented by 1, and the counted data is Sends DATA2 to the third storage unit 7, and at the same time, outputs the second depressed I sound 1; ? a 11 roses I rose C
0NT2 and write enable WE2 in the third storage unit 7.
put out 1y" and DATA2, let it be rented and DA
TA2 is sent to the comparator 6a. This is the third memory capital 7
is stored in an EEPROM, and its address is the same as before, such as 10 bits indicating 10 seconds or IO1'.
This is a series of bit data such as 17 bits indicating , and does not particularly require address data. 200th Pi Memorandum 4
A is also a mask type ROM that controls the power management value i1 as before.
It consists of a single heats type ROM or EEFROM. Unlike conventional models, the control value for joining alongside is memorized. For example, if the write times σ final tube' value is 10' times, IJIIIO
looo and forecast tube 3litre value 9XIQ”times l1100
00100 with the same number of bits.

Then write it down in your memory. And this floor 2nd part 4al koreren F; 1. Comparison of the above management value 6116
D consisting of the same bit θ as the management value to be sent 7'
ATA2 and the second control section 2a are the control section M CO1'J T
3, it is repeatedly compared for each bit configuration unit, and when DA'I'A2<each management f[, high level l is sent -b:, and when DATA2≧management value, If you don't want to leave the low level, for example DATA2
When the number of sheets falls below the management value t, the comparison section ()al outputs 1 for the final management value and l for the forecast management value l, and DATA2 outputs both management values. When the value is between the values, the output is 0, and if DATA2 does not reach the final control value, the output 00 is sent from the output terminal OUT.
In series with a1. DATA2
If we repeat the comparison in series in units of 1 thin bit, we get DA
0 when TA2 becomes equal to f6F: control value or goes around 10 times
When DATA2 is continuously detected as 0 and the final management value is not yet opened, it is displayed starting with 1 according to the setting of the forecast management value, and the degree of approach to the f4P final management value can be detected.

(g) As stated above in ``Effects of the Invention'', the present invention improves the conventional EEPRQ.
Compared to the external circuit used to manage the number of times M is written, the method is configured as a single chip on the same board, which reduces the mounting space and also allows for the design of a dedicated distribution section for measurement data. (・The conventional first control section is E E P
RCI M can be easily used by simply controlling the memory without having to consider any control means for managing the number of writes per ipl, and it is also possible to obtain the maximum P tube (sweeping degree for the value and EEP).
This is useful because it allows you to easily manage the gogome returns in the ROMI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an EEPROM equipped with a conventional external circuit for managing the number of inputs; FIG.
FIG. 2 is a block diagram of an IC memory using PR and OM. See the diagram 1. la is 'IC1hJ XI tt:i
, 2.2atJ second control section, 3 is the first B memory section, 4.4
a is the 2nd note, 1st note, 5c, counter, 6.6a, J ratio, 11t7, 2nd i, and 7 are the 3rd, 7th, and 4th part.

Claims (1)

[Claims] On the same number nine, storage means for storing R+1 pieces of general-purpose data, means for writing 1jJl number of the first storage means, iQ, the initial number σ door 11 in the number reduction number. a second storage means for storing and storing logical values; a third storage means for storing argument data;
It is provided with means for comparing the word 1n data of the 4th stage of ff with the management value of the number in the second storage means; circuit, the second WC storage means is fixed or electrically erasable read-only memory +i'? Consisting of an I'ij circuit,
Each time the control unit receives the Ichiyoshigo signal from the storage means, the control section uses the argument means to add 1 to the old training data stored in the means 1 and 11 of Section 3. Update the total V data,
Furthermore, the IC memory is characterized in that the first number data is outputted by a single-axis means, compared with a control value, and the 1'11 result is sent out.