JPS5943613A - MOS operational amplifier - Google Patents

Abstract

PURPOSE:To attain high-speed operation, by connecting a buffer amplifier to an output terminal of a cascode amplifier and forming a capacitive negative feedback path from the output terminal to a connecting point between two transistors forming the cascode amplifier. CONSTITUTION:A node 3 in the cascode amplifier 6 from the output terminal 8 of the buffer amplifier 7 is provided with the negative feedback path. Thus, the impedance of the node 3 is decreased, the time constant produced by a stray capacitance Cs is minimized, resulting in that the 2nd pole frequency of the cascode amplifier 6 is increased, allowing to attain the high-speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to increasing the speed of an operational amplifier (hereinafter referred to as an operational amplifier) configured using MOS transistors.

[Prior art]

In order to operate a MOS transistor at high speed, it is effective to use a so-called short channel device with a shortened gate length. However, as the channel length becomes shorter, the so-called short channel effect reduces the hearth-drain conductance (hereinafter referred to as
The inconductance (abbreviated as 0) increases rapidly, and the load resistance of the increased stage decreases! -7. Amplification level decreases. On the other hand, if multiple amplification stages are connected in order to obtain amplification, stray capacitance generated at the crotch will cause loss at high frequencies, impeding high-speed operation. In order to eliminate this drawback, it is effective to use the well-known cascode amplifier configuration.

In the Zunawaji cascode amplifier, by combining a grounded source amplification stage and a grounded gate amplification stage, it is possible to construct an amplifier equivalent to two amplification stages, while lowering the impedance at the connection point between both amplification stages. This allows the high-frequency loss between the legs to be minimized and high-frequency characteristics comparable to that of a single-stage amplifier can be achieved. Complementor IJM with the above characteristics
As a circuit configuration suitable for O8 (hereinafter referred to as CMO8,,!) device, P, R, Gray et al.
mePractical Aspects of
5w1tchedCapacitor Filter
r Design″1nProc.

l5CAS '81 April 1981
There is a folded cascode type one-stage amplifier described in .

FIG. 1 shows the basic configuration of the above circuit, and in the figure, 1 indicates a slot and 2 indicates an output terminal. Also, 9 and 10 are each N
and P-type first and second MOS transistors;4.
Reference numeral 5 indicates a DC constant current source that supplies a bias current. The box 10) I-range jumper 9 in the figure operates as a source grounding, and the 20th) 1-range jumper 10 operates as a gate-I/grounded amplifier to constitute a cascode amplification stage.

Figure 2 shows the typical characteristics of this circuit.
represents the DC gain (hereinafter referred to as Gpc), and 12 represents the cut-off wave number of the amplifier, the so-called first ball frequency (hereinafter referred to as ω,
), 13 has an amplifier gain of 1, that is, O(lF3
(',: indicates a frequency (hereinafter referred to as ω), ~le frequency (hereinafter referred to as ω2).

These characteristic values are determined by simple analysis. Note that G1 and G2 are transistors 9.
10, oml, Gm2 is the mutual contactance of the transistor 9.1o, C1 is the load capacitance connected to the output node 21, and C8 is the stray capacitance connected to the connection point 3 of the l-range shifter 9.10. show.

In the conventionally known circuit shown in FIG. 1, the DC gain GDc can have a value equivalent to two amplification stages. In addition, the stray capacitance CF generated at the connection point 3 of the l-lunge lid 9.10
4 is the so-called second pole ω2 indicated by 14 in FIG.
However, since the input impedance on the source side of the Hellangian diverter 10 is sufficiently low, the time constant decreases, and as shown in Fig. 2, the second ball frequency ω2 is set sufficiently higher than the frequency ω1 at which the gain is 1. It becomes possible to do so. This is a necessary condition for the operational amplifier to operate stably.

This circuit has the following advantages, but on the other hand, since the frequency O)1 at which the gain is 1 is determined by the load capacitance CL, there are significant restrictions on the load driving conditions in order to maintain high-speed operation. imposed. Furthermore, when using a short channel device of 3 μm or less, for example, the short channel effect causes G
, , G2 increases significantly, GDc becomes less than 60 dB, and the performance is significantly inferior compared to general-purpose operational amplifiers which have 80 to 100 dB at GDC.

Fig. 3 shows a method for improving the drawbacks of the conventional example shown above.
Reference numeral 7 indicates a separate buffer amplifier, and reference numeral 8 indicates an output terminal thereof.

By connecting the buffer amplifier 7 to the output terminal 2 of the cascode amplification stage 6 as shown in the figure, the cascode amplification stage 6
It is possible to always keep the load constant and stabilize the characteristics. Furthermore, by providing the buffer amplifier 7 with a constant gain, it is also possible to prevent the gain from decreasing due to the short channel effect.

By giving the buffer amplifier 7 a gain, the second
In the gain characteristic shown in the figure, the gain increases in a -like manner at all frequencies, so in the conventional example shown in Fig. 1, the second pole ω2
In contrast, in this improved example, the second ball occurs in the region where the gain is 1 or more, and the well-known 2
Due to the operating principle of the operational amplifier, stable operation can be expected when f, i < j: Therefore 01,
It is necessary to reduce ω by taking measures such as increasing ω, and to make the gain at C2 less than 1, which makes it difficult to operate the operational amplifier circuit at high speed.

[Purpose of the invention]

An object of the present invention is to improve the problems of the conventional example described above, and to provide an MO8 operational amplifier that enables high-speed operation while ensuring sufficient DC gain GDc, and minimizes the influence of the load capacitance value on the characteristics. It is something.

[Summary of the invention]

The present invention is based on a cassette: node shape or folding force scallop.
Output terminals of the cascade type amplifier (1st and 20' to which a separate buffer amplifier is connected and form a cascade amplifier from the output terminal of the L type buffer amplifier) By forming a capacitive negative feedback path to the second
4 Mir frequency ω2 is increased to enable high-speed operation of 14 Bearn/''.

[Embodiments of the invention]

FIG. 4 is an AC equivalent circuit showing the first embodiment of the present invention. In the figure, Gm1, (1m2, ()1, G2' are the first
The first and second amplifiers constituting the cascade amplifier shown in the figure
Mutual conductance of transfer lid 9 and '10,
and the drain contactance is -4o, and the DC gain of the buffer amplifier 7 is A.

To explain the present invention qualitatively, by providing a negative feedback path from the output terminal 8 of the buffer amplifier 7 to the cascade amplifier 6 ())/-domain 3, By lowering the beadance, the capacitance C becomes 0, S1-1/I.

The purpose is to minimize the time constant generated by ω2, thereby increasing the second pole frequency ω2 of the cascode amplification stage.The effects of the present invention will be explained in detail using the following equations.

The transfer function F (81) from the input terminal 1 to the output terminal 8 of the equivalent circuit shown in FIG.
In the formula, H is H= (G, +808+5Oc) (G, 4-8C1, -
IGl,)+02(80,+oL), and S indicates the Laplace-transformed angular frequency.

Equation (4) is very complicated, but for example, for a MO8I-lunge lid, gate length is 2 to 3 μm, gate width is 100 to
When using a device of about 500 μm, 01, G2; 1o
-'s-J, o-58om, +om2:: 10"
s ~ i 0 ' 8C210-13p and C2 is expected to be 108 to 109 radians/sec, so when performing numerical calculations at the upper rudder frequency, the approximation of G, +SC8, :;SC8 is To establish. Furthermore, the load admittance GL of the cascode amplification stage can be made extremely small by circuit improvements as shown in the second embodiment described later, so that the following approximation is also possible. As a result, 11 in formula (4) is H
; 82(C,+Cc)C,, It can be approximated as follows. Rewriting equation (4) using these approximations simplifies it. According to the above equation (5), the second pole frequency ω2 is expressed as L. It is true that Equation 6) was obtained on the assumption that Cs is sufficiently smaller than CL. On the other hand, the fourth
In the equivalent circuit shown in the figure, if C0 is set to 0 (!:),
That is, when the present invention is not applied, it is approximated by equation (4),
The second pole frequency ω2 obtained from the above equation (7) is expressed as and coincides with the result shown in the equation (3). That is, by applying the present invention to Kokichi, the second pole frequency ω2
can be increased by ACL/Cs. Therefore, if the gain A of the buffer amplifier 7 in FIG. 4 is sufficiently large, it becomes possible to effectively increase the second pole frequency.

In the first embodiment, as shown in FIG. 4, a sufficiently small 4f admittance GL was assumed as the load on the cascode amplifier. In order to reduce this GL, it has been well known to use a cascode connection in the load circuit, but the stray capacitance C/8 generated in this cascode load circuit is The second pole frequency ω2 is lowered by the same effect as in 08. As shown in the first embodiment, the present invention provides a capacitive negative feedback path from the output terminal 8 of the post buffer amplifier 7 to the connection point of the stray capacitance. 8 is also very effective in preventing the second pole frequency from becoming low.

A second embodiment of the present invention will be described in detail below.

FIG. 5 is an equivalent circuit showing a second embodiment of the present invention.

In the figure, Gm3 and G3 are cascode-type enlarger cass-1-
G4 is the mutual contactance and drain contactance of the third transistor constituting the double-ended load circuit, and G4 is the drain contactance of the fourth transistor.

Further, C/ is a stray capacitance generated at the connection point of the third and fourth transistors, and C/c is a capacitance that determines the amount of feedback from the output terminal 8. Note that the cascode amplification stage in the figure has a mutual conductance G'm to simplify the explanation.
! and ()1' only. Transfer function P'(s
) is shown using similar approximations as shown in the first embodiment above. As is clear from equation (9), the transfer function P'(s) of this circuit is set as the second pole frequency ω2 if the gain A of the buffer amplifier 7 is sufficiently high and C6' is larger than C,/I, has a value of The result of equation (10) is very similar to the result of equation (6) shown in the first embodiment, and it can be seen that similar effects can be obtained.

Further, when C6' is set to zero, that is, when the present invention is not implemented, F'(s) is expressed as, and its second pole frequency ω2 is expressed as follows. This is similar to the result of equation (8) above, and the second
It can be seen that the same effects as in the first embodiment can be obtained in the embodiment. Furthermore, formula (9) c! = As is clear from a comparison of equation (5), in the second embodiment, the transfer function F'(s)
is the zero point frequency ω.

have. Generally, in order to increase the effective bandwidth of an operational amplifier, a method is known in which a zero point is set separately near the second pole frequency to offset the phase rotation.
Since the zero point can be estimated at any frequency by appropriately selecting the value of ', it is possible not only to simply increase the second pole frequency but also to obtain the above-mentioned phase rotation canceling effect.

Although the embodiments of the present invention have been described above using equivalent circuits, the sixth embodiment
An example using actual transistors will be described with reference to the drawings. This embodiment shows an example in which the present invention is applied to a folded cascode type differential amplifier circuit. In the figure, 1 and 1' indicate differential input terminals (Ml.

M'1), (Ni.2Md), (M3.M; ),
(M4.M2) indicate the above-mentioned first to fourth transistors connected in a differential pair, respectively. Also c8
, C; are the stray capacitances generated in the transistor electrodes, wiring, etc., and Cc, C, and l are the first stray capacitances, respectively.
゜Capacitor hi constituting the negative feedback path shown in the second embodiment:
It is.

FIG. 7 shows the characteristics of the operational amplifier circuit shown in FIG.
Moreover, it has a gain of about 15 dB at the same frequency. Therefore, it cannot withstand use as a stable amplifier (・1), but if 06PP is used for each of Co and C16, ω2 will rise to 60 Ml-(z, and the gain at the same frequency will be less than OdB, so it will be stable enough. It can be seen that the cascode amplifier stage 6 can operate in this manner.The number 11 in the figure shows the frequency characteristics of the cascode amplification stage 6 alone, and both the gain and bandwidth have been significantly improved by implementing the present invention. Figure 8 shows the load capacitance dependence of a single cascode amplifier and an amplifier implementing the present invention.In the figure, 14 and 15 are cascode 11-stage amplifiers with small and large load capacitances, respectively. On the other hand, 12 and 13 are amplifiers in which the present invention is implemented, and the load capacitance is small and the load capacitance is small, respectively. When the present invention is implemented, only slight characteristic fluctuations are observed in the region where the gain is O dB or less, and the effectiveness of the present invention can be understood.

〔Effect of the invention〕

As explained above, by implementing the present invention, it is possible to significantly improve the gain and band characteristics at the same time by adding only a few parts to a conventional cascode amplifier, and furthermore, it is possible to significantly improve the load capacitance dependence of the amplifier. It is possible to significantly reduce the amount.

Although the embodiment has been described using a folded cascode amplifier, it goes without saying that the present invention can be applied to any other cascode amplifier.

[Brief explanation of drawings]

FIGS. 1 to 3 show conventionally known cascode amplifiers and improved examples thereof, each showing an equivalent circuit, an example of characteristics, and an example in which a buffer amplifier is connected. 4-5 show equivalent circuits of the first and second embodiments of the present invention, FIG. 6 shows an embodiment using actual MOS transistors, and FIGS. 7-8 show equivalent circuits of the first and second embodiments of the present invention. Examples of improved characteristics with and without implementation of the present invention are shown. 1. Operational amplifier input terminal, 2. Cascode stage output terminal, 3. Cascode stage connection terminal, 6. Cascode amplifier, 7. Buffer amplifier, 8 Operational amplifier output terminal. Representative Patent Attorney Susuki 1) Yuki Toshi 1311 Certain 4-Diagram Procedure Amendment (Method) Display of Case 1982 Patent Application No. 153905 Name of Bow Invention ~ 1 (Waka'5F who makes a mountain king of JS operational amplifier)) ( ;Formula i: I rl stand made
Work place!゛、；'、１? X-:, 1
．． 11 Katsu Shigeyo Rihito”□ °“゛ □゛ □゛” Usui Ill
Interest 7:61. Ilyun correction command θIT, 3
Attached: November 30, 1981, contents of the arrest, 1 volume, 1 volume, A1 (no changes in content). 61-

Claims (1)

[Scope of Claims] 1. A first source-grounded MoS transistor to which an input signal is applied to its gate electrode; - its source electrode is connected to the drain electrode side of said transistor; and its gate electrode is connected to a predetermined bias potential; A separate buffer amplifier is connected to the second 1-OS transistor (thus constituted by the cascode type amplifier's second 1-MOS transistor) to which the voltage is applied, and the cascode stage is 2. An MO8 operational amplifier characterized in that a negative feedback path is provided at a connection point between the drain electrode of the first transistor and the source electrode of the second transistor via a capacitor. Connect the drain electrode of the third transistor to the drain electrode of the transistor, connect the drain electrode of the fourth transistor to the source electrode of the third transistor, and connect the drain electrode of the fourth transistor to the gate electrode of the third transistor. connects the buffer amplifier to the drain electrode of a second transistor of a cascode amplifier having a cascode load, each of which is given a predetermined bias potential; 4. An MOS operational amplifier characterized in that a negative feedback path is provided via a capacitor at the connection point of the drain electrode of the transistor in claim 1.3. 2 transistor attributes (P and N
MO8, which is characterized in that the molds) are contradictory to each other.
@ Arithmetic amplifier.