JPS5940580A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS5940580A JPS5940580A JP57150537A JP15053782A JPS5940580A JP S5940580 A JPS5940580 A JP S5940580A JP 57150537 A JP57150537 A JP 57150537A JP 15053782 A JP15053782 A JP 15053782A JP S5940580 A JPS5940580 A JP S5940580A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- thin film
- gate
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は薄膜半導体を基板として用いたMO8型電界効
果トランジスタを構成要素とする半導体集積回路に関し
、薄膜半導体上に形成される酸化膜の形成方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having an MO8 field effect transistor as a component using a thin film semiconductor as a substrate, and relates to a method for forming an oxide film formed on the thin film semiconductor.
アモルファス薄膜半導体や多結晶薄膜半導体を基板とし
て用いたMO3i14界効果トランジスタの研究開発が
さかんにおこなわれている。それは、薄膜MO8型電界
効果トランジスタを構成要素とする半導体集積回路装置
が実現可能となると、種々の大きなメリットが出てくる
からである。たとえば、大「[Jなフストダウンが期待
できるのと、大型の工a及び多層構造のIC等が実現し
て、ICの大きな応用範囲がうまれる。Research and development of MO3i14 field effect transistors using amorphous thin film semiconductors or polycrystalline thin film semiconductors as substrates is being actively conducted. This is because if it becomes possible to realize a semiconductor integrated circuit device using thin film MO8 type field effect transistors as a component, various great advantages will emerge. For example, we can expect large-scale stop-downs, and the realization of large-sized ICs and multilayer ICs, which will create a wide range of applications for ICs.
現在、いたる所で研究開発されつつあるこの薄膜MO3
電界効果トランジスタ及び集積回路装置にも大きな問題
点がいくつか存在する。This thin film MO3 is currently being researched and developed everywhere.
There are also some major problems with field effect transistors and integrated circuit devices.
その大きな問題の中に、ゲート膜耐圧低下の問題やリー
ク電流の増大の問題、スレッショルド電圧を作用するス
テイトの問題、それに酸化膜中への電荷の注入問題等が
あり、特性上、信頼性上安定した量産ができない状態に
ある。Some of the major problems include a reduction in gate film breakdown voltage, an increase in leakage current, a state that applies a threshold voltage, and charge injection into the oxide film, which affect characteristics and reliability. We are in a state where stable mass production is not possible.
従来の製造方法について第1図〜第3図に例を。Examples of conventional manufacturing methods are shown in FIGS. 1 to 3.
挙げて以下に説明する。These will be listed and explained below.
第1図に示すように、石英ガラス基体1の上に気相成長
5102膜2を形成し、その上にP型多結晶シリコン層
3を形成し選択的にエツチングする。As shown in FIG. 1, a vapor phase growth 5102 film 2 is formed on a quartz glass substrate 1, and a P-type polycrystalline silicon layer 3 is formed thereon and selectively etched.
第2図に示すように、その上にゲート酸化膜4を形成し
、ゲート′NJ極配m5を形成する。さらに+
イナン打込みによって、N 拡散層6を形成する。As shown in FIG. 2, a gate oxide film 4 is formed thereon to form a gate 'NJ electrode pattern m5. Furthermore, an N diffusion layer 6 is formed by +inane implantation.
第6図に示すように、気相成長5102膜7を形成した
後、ホトエツチングにより、コンタクトホールのあなあ
けをした後、At蒸着をして選択エツチングをしてAj
配線8を形成する。As shown in FIG. 6, after forming a vapor phase grown 5102 film 7, a contact hole is bored by photoetching, and then At vapor deposition is performed and selective etching is performed to form Aj.
Wiring 8 is formed.
以上のようにゲート酸化膜には熱酸化膜、特に02ガス
雰囲気中で酸化するドライ熱酸化膜が使用されるのが一
般的である。そして、その酸化温度も1100℃〜12
00℃と高温を必要としている。低温で酸化したり、高
温でも加湿酸化すると基板の多結晶化が進みアスビリテ
ーと言われる突起が、基板からゲート酸化膜内へ突き出
た形で成長し、そこに電界集中がおきて耐圧劣化をきた
圧劣化をきたしているが、現在よりよい酸化膜の形成方
法について検討しているのが現状である。As described above, a thermal oxide film, particularly a dry thermal oxide film that is oxidized in an 02 gas atmosphere, is generally used as the gate oxide film. And the oxidation temperature is also 1100℃~12
It requires a high temperature of 00℃. Oxidation at low temperatures or humid oxidation at high temperatures will cause the substrate to become polycrystalline, causing protrusions called asbilites to grow protruding from the substrate into the gate oxide film, causing electric field concentration there and deteriorating breakdown voltage. Although the pressure has deteriorated, we are currently investigating a better method for forming an oxide film.
他の方法として気相成長の8102膜を成長させ、熱ア
ニールをする事によってゲート膜として使用していく方
法等についても、検討されているが、特性の不安定性が
問題になっている。Other methods are being considered, such as growing an 8102 film by vapor phase growth and using it as a gate film by thermal annealing, but instability of the characteristics is a problem.
又、薄膜をのせる基体の材質の面や酸化炉、ボート等の
装置及び治具の面から酸化温度を下げる要求が強い。Furthermore, there is a strong demand for lowering the oxidation temperature from the viewpoint of the material of the substrate on which the thin film is placed and the equipment and jigs such as oxidation furnaces and boats.
本発明は吹上のような欠点について改良を加えたもので
あり、本発明の目的は耐圧特性のすぐれたゲート膜を形
成する事にあり、本発明の他の目的は酸化温度を低下す
る事にある。The present invention is an improvement on the drawbacks such as blow-up, and the purpose of the present invention is to form a gate film with excellent voltage resistance characteristics.Another purpose of the present invention is to reduce the oxidation temperature. be.
第4図〜第6図に例を挙げて以下に本発明について説明
する。The present invention will be described below with examples shown in FIGS. 4 to 6.
第4図に示すように石英ガラス基体11の上に気相成長
5102膜12を形成し、その上にP型多結晶ンリコン
層13を形成し選択的にエツチングする。その上に気相
成長5102膜14を、必要なゲート膜厚よりも薄い膜
厚で形成し、さらに、酸化性雰囲気中で熱酸化させ、第
5図に示すように所定の厚みのゲート酸化膜15を得る
。その上にゲート電極配m16を形成し、上からイオン
打込+
みをしてN 拡散層17を形成する。第6図に示すよう
に、気相成長5102膜18を形成し、ホトエツチング
によりコンタクトホールのあなあけをした後、At蒸着
をして選択エツチングをしてAt配線19を形成する。As shown in FIG. 4, a vapor phase grown 5102 film 12 is formed on a quartz glass substrate 11, and a P-type polycrystalline silicon layer 13 is formed thereon and selectively etched. A vapor-phase grown 5102 film 14 is formed thereon to a thickness thinner than the required gate film thickness, and then thermally oxidized in an oxidizing atmosphere to form a gate oxide film of a predetermined thickness as shown in FIG. Get 15. A gate electrode arrangement m16 is formed thereon, and ions are implanted from above to form an N diffusion layer 17. As shown in FIG. 6, a vapor phase grown 5102 film 18 is formed, a contact hole is bored by photoetching, and then At is deposited and selectively etched to form an At wiring 19.
以上のように、本発明の方法によると、熱酸化前に気相
成長のSin、を形成しておくために、熱が加わる時に
おきる結晶化を防止できる事と、熱酸化時に発生するア
スピリティ(突起)の発生防止に役立つ。そのため耐圧
が充分ある。As described above, according to the method of the present invention, since the vapor-phase grown Sin is formed before thermal oxidation, it is possible to prevent crystallization that occurs when heat is applied, and to prevent aspiration ( Helps prevent the occurrence of bumps). Therefore, it has sufficient pressure resistance.
さらに、熱酸化も気相成長の8102中を酸素等の酸化
剤が拡散し、薄膜半導体の表面にとおたつして、簿膜半
導体の表面を酸化して酸化膜を形成していくので、膜質
も熱酸化単独で形成された酸化膜と同等の品質を持つ。Furthermore, in thermal oxidation, oxidizing agents such as oxygen diffuse through the vapor-phase grown 8102 and reach the surface of the thin film semiconductor, oxidizing the surface of the thin film semiconductor and forming an oxide film, which improves the film quality. It also has the same quality as an oxide film formed by thermal oxidation alone.
なお、アスビリティー(突起)は低温はど発生、成長し
やすいが、本発明の方法によると低温でも発生、成長し
にくく、酸化温度を下げても、高品質のゲート酸化膜が
得られる。Incidentally, asabilities (protrusions) tend to occur and grow at low temperatures, but according to the method of the present invention, they are difficult to generate and grow even at low temperatures, and a high-quality gate oxide film can be obtained even if the oxidation temperature is lowered.
なお、本発明の方法の例としてP型の多結晶シリコン基
板を用いた例を示したが、lq型の多結晶シリコン基板
でも同様であり、アモルファスシリコン基板でも同様で
ある。又、他の素成の多結晶基板、アモルファス基板で
も同様である。Although an example using a P-type polycrystalline silicon substrate is shown as an example of the method of the present invention, the same applies to an lq-type polycrystalline silicon substrate, and the same applies to an amorphous silicon substrate. The same applies to polycrystalline substrates and amorphous substrates of other elemental compositions.
第1図〜第6図は従来方法による製造工程順の断面略図
である。
第4図〜第6図は本発明の方法による製造工程順の断面
略図である。
以下、次の通りである。
1.11・・・石英ガラス基体
2.12.14・・・気相成長5102膜6.16・・
・P型多結晶シリコン層
4.15・・・ゲート酸化膜
5.16・・・ゲート電極配線
6.17・・・N+拡散層
7,18・・気相成長5102膜
8.19・・・At配線
以 上
出願人 株式会社諏訪精工舎1 to 6 are schematic cross-sectional views of the manufacturing process according to the conventional method. 4 to 6 are schematic cross-sectional views of the manufacturing process according to the method of the present invention. The following is as follows. 1.11... Quartz glass substrate 2.12.14... Vapor phase growth 5102 film 6.16...
・P-type polycrystalline silicon layer 4.15... Gate oxide film 5.16... Gate electrode wiring 6.17... N+ diffusion layer 7, 18... Vapor phase growth 5102 film 8.19... At wiring and above Applicant: Suwa Seikosha Co., Ltd.
Claims (1)
基板として用いたM OS型電界効果トランジスタを構
成要素とする半導体集積回路装置において、該アモルフ
ァス半導体薄膜、又は該多結晶半導体薄膜上に気相成長
による酸化膜を形成した後、酸化雰囲気中で熱酸化する
事によってゲート酸化膜を形成する事を特徴とする半導
体集積回路装置の製造方法。 2)該酸化雰囲気中に塩酸ガスを含有する事を特徴とす
る特Wr請求範囲第1項記載の半導体集積回路装置、の
製造方法。[Scope of Claims] 1) A semiconductor integrated circuit device comprising a MOS field effect transistor using an amorphous semiconductor thin film or a polycrystalline semiconductor thin film as a substrate, the amorphous semiconductor thin film or the polycrystalline semiconductor thin film A method for manufacturing a semiconductor integrated circuit device, comprising forming an oxide film thereon by vapor phase growth, and then forming a gate oxide film by thermally oxidizing the film in an oxidizing atmosphere. 2) A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that the oxidizing atmosphere contains hydrochloric acid gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57150537A JPS5940580A (en) | 1982-08-30 | 1982-08-30 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57150537A JPS5940580A (en) | 1982-08-30 | 1982-08-30 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5940580A true JPS5940580A (en) | 1984-03-06 |
Family
ID=15499032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57150537A Pending JPS5940580A (en) | 1982-08-30 | 1982-08-30 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5940580A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04165679A (en) * | 1990-10-29 | 1992-06-11 | Semiconductor Energy Lab Co Ltd | Insulating gate type semiconductor device |
JPH0637317A (en) * | 1990-04-11 | 1994-02-10 | General Motors Corp <Gm> | Thin-film transistor and its manufacture |
US6607947B1 (en) | 1990-05-29 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device with fluorinated layer for blocking alkali ions |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS595672A (en) * | 1982-07-02 | 1984-01-12 | Seiko Epson Corp | Manufacture of thin film transistor |
-
1982
- 1982-08-30 JP JP57150537A patent/JPS5940580A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS595672A (en) * | 1982-07-02 | 1984-01-12 | Seiko Epson Corp | Manufacture of thin film transistor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637317A (en) * | 1990-04-11 | 1994-02-10 | General Motors Corp <Gm> | Thin-film transistor and its manufacture |
US6607947B1 (en) | 1990-05-29 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device with fluorinated layer for blocking alkali ions |
US7355202B2 (en) | 1990-05-29 | 2008-04-08 | Semiconductor Energy Co., Ltd. | Thin-film transistor |
JPH04165679A (en) * | 1990-10-29 | 1992-06-11 | Semiconductor Energy Lab Co Ltd | Insulating gate type semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5170231A (en) | Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current | |
US6228728B1 (en) | Method of fabricating semiconductor device | |
JP2612040B2 (en) | MOS-FET using β-SiC and manufacturing method thereof | |
JP2004088103A (en) | Liquid crystal display manufacturing method | |
JPS5940580A (en) | Manufacture of semiconductor integrated circuit device | |
KR100389570B1 (en) | Method for manufacturing thin gate silicon oxide layer | |
JPH06260644A (en) | Manufacture of semiconductor device | |
KR19990013304A (en) | How to crystallize amorphous membrane | |
JPS5931068A (en) | Method for manufacturing semiconductor integrated circuit device | |
JP3203652B2 (en) | Semiconductor thin film manufacturing method | |
JPH02203564A (en) | Silicon carbide semiconductor device | |
JPH03205830A (en) | Manufacture of semiconductor device and polycrystalline germanium | |
JPS63119576A (en) | Method of forming active region of thin film transistor | |
KR960004902B1 (en) | Polycrystalline Silicon Thin Film Manufacturing Method | |
JPH0196923A (en) | Epitaxial growth method | |
KR19990023052A (en) | How to crystallize amorphous membrane | |
JPH039534A (en) | Field effect transistor using silicon carbide | |
JPH0393273A (en) | Method for manufacturing thin film semiconductor devices | |
JPH11111985A (en) | Manufacture of thin-film transistor and liquid crystal display device | |
JPH01276617A (en) | Manufacturing method of semiconductor device | |
KR100472855B1 (en) | Polycrystalline silicon thin film manufacturing method of semiconductor device | |
JPH0319340A (en) | Manufacturing method of semiconductor device | |
JPS62124736A (en) | Silicon thin-film and manufacture thereof | |
JPH03257818A (en) | Manufacturing method of semiconductor device | |
JPH05144730A (en) | Manufacture of semiconductor device |