JPS593927A - Thin film etching method - Google Patents
Thin film etching methodInfo
- Publication number
- JPS593927A JPS593927A JP11369682A JP11369682A JPS593927A JP S593927 A JPS593927 A JP S593927A JP 11369682 A JP11369682 A JP 11369682A JP 11369682 A JP11369682 A JP 11369682A JP S593927 A JPS593927 A JP S593927A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- vacuum chamber
- thin film
- etching
- chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 26
- 238000005530 etching Methods 0.000 title claims description 20
- 239000010409 thin film Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims description 51
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000009434 installation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 description 12
- 239000007789 gas Substances 0.000 description 12
- 239000000460 chlorine Substances 0.000 description 8
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 6
- 229910052801 chlorine Inorganic materials 0.000 description 6
- 150000001805 chlorine compounds Chemical class 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241001441724 Tetraodontidae Species 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- -1 hydrogen tetrachloride Chemical class 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 210000003141 lower extremity Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明はシリコン（Ｓｌ）等の半導体基板上に形成シた
アルミニウム膜のような素子形成用の薄膜のエツチング
方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in a method for etching a thin film for forming elements, such as an aluminum film, formed on a semiconductor substrate such as silicon (Sl).
０：ｌ）技術の背景
最近工Ｃ，ＬＳＩ等の半導体装置を製造する際Ｓ１基板
から半導体装置を形成するためのウェハー処理工程を一
貫して連続して処理するインプロセス工程がとられるよ
うになってきている。これは各工程間で１クエハーの滞
留を防止し、工程に要する人手を省力化し、ウェハー上
に塵やゴミ等が付着してそのために形成される半導体装
置の歩留が低下しないようにするためである。0:l) Background of technology Recently, when manufacturing semiconductor devices such as C and LSI, an in-process process has been adopted in which the wafer processing process for forming the semiconductor device from the S1 substrate is performed consistently and continuously. It has become to. This is to prevent one wafer from stagnation between each process, save the manpower required for the process, and prevent dust and dirt from adhering to the wafer, which will reduce the yield of semiconductor devices formed. It is.
（Ｃ）従来技術と問題点
このようなインプロセス工程の一環として最近ロードロ
ック方式を用いてＳｉ基板上に形成されているＡｅのよ
うな半導体素子形成用薄膜をドライエツチングして所定
のパターンに形成する方法が用いられている。(C) Prior art and problems Recently, as part of such in-process steps, a thin film for forming semiconductor elements such as Ae, which is formed on a Si substrate, is dry-etched into a predetermined pattern using a load-lock method. A method of forming is used.
ここで従来のこのようなロードロック方式を用いたドラ
イエツチング方法について第１図および第２図を用い力
から説明す石。Here, the conventional dry etching method using such a load lock method will be explained from the viewpoint of force using FIGS. 1 and 2.
第１図、第２図は従来のこのようなエツチングに用いる
装置の概略図である。各真空室６，７゜８はそれぞれ排
気口！３，４．５を通じて排気され、ゲートバルブプ２
Ａ、２Ｂ、２Ｃ，２Ｄで仕切られている。FIGS. 1 and 2 are schematic diagrams of a conventional apparatus used for such etching. Each vacuum chamber 6,7°8 has an exhaust port! 3, 4.5 is exhausted through gate valve pu 2.
It is divided into A, 2B, 2C, and 2D.
ここで真空室６はＡＩ等の薄膜を形成したＳｉ基板９が
導入される入口側真空室でこれに隣接する真空室７はこ
の中に基板設置台１０とそれに対向する電極１１が設け
られており、該設置台ｌＯと電［１１間には高周波電源
１２よυ高周波電圧が印加されるようになっている。Here, the vacuum chamber 6 is an entrance-side vacuum chamber into which a Si substrate 9 on which a thin film of AI or the like is formed is introduced, and the adjacent vacuum chamber 7 is provided with a substrate installation table 10 and an electrode 11 facing it. A high frequency voltage υ from a high frequency power source 12 is applied between the installation table 10 and the voltage source 11.
また各真空室７には四塩化度素（ＣＣｊ？４）のような
エツチングガスを導入するガス導入孔１８が設けられて
いる。また該真空室７には隣接して基板９が出力される
ような出口側真空室８が設けられている。Further, each vacuum chamber 7 is provided with a gas introduction hole 18 for introducing an etching gas such as hydrogen tetrachloride (CCj?4). Further, an outlet side vacuum chamber 8 from which a substrate 9 is outputted is provided adjacent to the vacuum chamber 7.
このようなロードシック方式のドライエツチング装置を
用いてＳＮ基板９上に形成したＡＩの配線膜を所定のパ
ターンにエツチングする場合について述べると第２図に
示すようにまずＳｉ基板９をベルト１４等を用いて運搬
する。Ｓ−基板９が・ゲートパルプ２Ａに近付いた段階
で入口側真空室６を大気圧としくリーク用パルプは図示
せず）８１基板９が入口側真空室６内へ挿入される。そ
の後ゲートパルプ２Ａを閉じ、真空室６を排気後、ゲー
トパルプ２Ｂを開きＳ′Ｌ基板９を隣接の真空室７へ導
く。ここでゲートバルブプ２Ｂを閉じガス導入孔１３よ
りＣＣｅ４ガヌを０．Ｉ’ｒｏｒｒの真空度になるまで
導入し、高周波電源１２を用いて基板設置台１０と電極
１１間に高周波電圧を印加しＣＣ（１４のガスプラズマ
を形成する。このようにすると、ＣＣｅ４ガスより塩素
フジ力／ｌ／ （Ｃｌ”、が形成され、か″
と〕ｃｅ”で基板上のＡｌ ｌ塩化アルミニウム（Ａｌ
（Ｊａ）の形で除去される。To describe the case where an AI wiring film formed on the SN substrate 9 is etched into a predetermined pattern using such a road-sick type dry etching device, first the Si substrate 9 is placed on a belt 14, etc., as shown in FIG. Transport using. When the S-substrate 9 approaches the gate pulp 2A, the inlet vacuum chamber 6 is brought to atmospheric pressure, and the leakage pulp (not shown) 81 substrate 9 is inserted into the inlet vacuum chamber 6. Thereafter, the gate pulp 2A is closed, and after the vacuum chamber 6 is evacuated, the gate pulp 2B is opened and the S'L substrate 9 is introduced into the adjacent vacuum chamber 7. Here, close the gate valve 2B and apply 0.0% CCe4 gas through the gas introduction hole 13. A high frequency voltage is applied between the substrate mounting table 10 and the electrode 11 using the high frequency power supply 12 to form a CC (14) gas plasma. chlorine fuji force/l/ (Cl", is formed, and the aluminum chloride (Al
It is removed in the form of (Ja).
その後エツチングを終了したＳｉ基板９を更にベルト１
４を用いて運搬しゲートパルプ２Ｃを開いて出口側真空
室８内へ導入し、その真空室を大気に戻した後更にべｌ
） １４を用いて運搬し、ゲートバルブ２Ｄを開いて大
気中へ運び出すようにしている。After that, the etched Si substrate 9 is further transferred to the belt 1.
4 to transport the pulp, open the gate pulp 2C, introduce it into the outlet side vacuum chamber 8, return the vacuum chamber to the atmosphere, and then further remove it.
) 14 to transport it, and open the gate valve 2D to transport it into the atmosphere.
ところで前記したエッチ、フグ後のＡｌのｌ’ｊｉ’！
線膜や該Ａｌ配線膜をパターニングするためのその上に
形成したホトレジスト膜上にはＣｆとｌとが反応して生
成されたＡｌ（Ｊ？ａやその他の塩素化合物が残留して
おり、大気中に存在している微量な水分と反応して塩化
水素酸（Ｈ（，７？）が形成され、このＨＣｌによって
再び所定のパターンに形成されたＡ７？配線膜がエツチ
ングされて除去される欠点を生じる。By the way, the Al'ji' after the above-mentioned etch and blowfish!
Al(J?a) and other chlorine compounds generated by the reaction of Cf and L remain on the photoresist film formed on the wire film and the photoresist film formed thereon for patterning the Al wiring film, and are exposed to the atmosphere. The drawback is that hydrochloric acid (H(,7?) is formed by reacting with a small amount of moisture present in the film, and the A7? wiring film formed in a predetermined pattern is etched and removed by this HCl. occurs.
そこで従来は真空室７で、基板９上に残留しているＡＩ
Ｉｃｅ３やその他の塩素化合物や塩素等を除去するため
にエツチング鐵該基板を四弗化炭素（ＯＦ、）ガスや水
素（Ｎ２）ガスのプラズマ中にさらしていたが充分にＡ
（ｌｃｌｓを除去するには長時間かかり処理能力が低下
する問題がある０又、最近出口側の真空室８で基板９上
に残留しているＡ６（Ｊａを除去するため、該真空室８
内へ加熱した窒素（Ｎ２）ガスを流し、基板を加熱して
除去することも試みたが、このようにすると長時間熱処
理をしないと効果的にｌ？０１−ａやその他塩素等を除
去できない不都合を生じる。Therefore, in the past, the AI remaining on the substrate 9 was removed in the vacuum chamber 7.
In order to remove Ice3 and other chlorine compounds and chlorine, the etching iron substrate was exposed to plasma of carbon tetrafluoride (OF) gas and hydrogen (N2) gas, but
(There is a problem that it takes a long time to remove the lcls and the processing capacity is reduced.In addition, in order to remove the A6 (Ja) remaining on the substrate 9 in the vacuum chamber 8 on the exit side, the vacuum chamber 8
I tried to remove the substrate by flowing heated nitrogen (N2) gas into the substrate, but this method was not effective unless heat treatment was performed for a long time. This causes the inconvenience that 01-a and other chlorine etc. cannot be removed.
（ｄ） 発明の目的
本発明は上述した問題を除去し、ロードロックた
方式を用い１ドライエツチング法で、基板上のＡ／のよ
うな薄膜を形成した後の基板にに残留しているＡ Ｉ
Ｃｌ ３やその他塩素および塩素化合物を容易に除去で
き得るような、新規な薄膜のエツチング方法の提供を目
的とするものである。(d) Purpose of the Invention The present invention eliminates the above-mentioned problems and eliminates the residual A on the substrate after forming a thin film such as A on the substrate by one dry etching method using a load-locked method. I
The object of the present invention is to provide a novel thin film etching method that can easily remove Cl 3 and other chlorine and chlorine compounds.
（ｅ）発明の構成
かかる目的を達成するだめの本発明の薄膜のエツチング
方法ずは、素子形成用薄膜を形成した半導体基板を入力
側真空室、エツチング室へ順次導入後肢エツチング室の
基板設置台に設置し、エツチングガスを導入しながら基
板設置台上の基板上に形成されている素子形成用薄膜を
エツチングし、しかる後肢基板を出力側真空室を通過さ
せてから大気中に取シ出す方法において、前記基板を出
力側真空室に導入した時、該基板にマイクロ波を照射し
て基板を加熱し、基板上の薄膜に付着している残留物を
除去するようにしたこと−を特徴とするものである。(e) Structure of the Invention The method of etching a thin film of the present invention to achieve the above object is as follows: First, a semiconductor substrate on which a thin film for forming an element has been formed is sequentially introduced into an input side vacuum chamber and then into an etching chamber. A method in which the thin film for element formation formed on the substrate on the substrate installation table is etched while introducing etching gas, and the hindlimb substrate is passed through an output side vacuum chamber and then taken out into the atmosphere. characterized in that when the substrate is introduced into the output side vacuum chamber, the substrate is heated by irradiating the substrate with microwaves to remove residues attached to the thin film on the substrate. It is something to do.
更には前記出力側真空室の真空度を０．８ Ｔｏｒｒ以
下の圧力としたことを特徴とするものである。Furthermore, the vacuum degree of the output side vacuum chamber is set to a pressure of 0.8 Torr or less.
（ｆ） 発明の実施例
以下図面を用いて本発明の一実施例につき詳細に説明す
る。(f) Embodiment of the Invention An embodiment of the invention will be described in detail below with reference to the drawings.
第３図は本発明の薄膜のエツチング方法を示す概略図で
前述した基板の出力側真空室２１の上部壁面には石英ま
たはセラミック等のマイクロ波透過窓２２を設けている
。そしてこのマイクロ波透過窓には連通して銅等で形成
したマイクロ波導波管２８を設は該導波管２８内部にマ
イクロ波を照射するようにマグネトロン２４を設置して
いる。FIG. 3 is a schematic diagram showing the thin film etching method of the present invention, in which a microwave transmitting window 22 made of quartz or ceramic is provided on the upper wall surface of the output side vacuum chamber 21 of the substrate described above. A microwave waveguide 28 made of copper or the like is connected to the microwave transmission window, and a magnetron 24 is installed to irradiate the inside of the waveguide 28 with microwaves.
このようにした状態でＡｌの配線膜を所定のパターンに
前述したようにドライエツチングしたＳｉ基板２５をべ
／シト２６を用いて出力側真空室２１の内部に挿入する
。そしてゲートバルブ２７．２８を閉じた状態でマグネ
トロン２４を用いて、出力４００Ｗ、周波数２．４５Ｇ
Ｈ２，のマイクロ波を基板に照射する。するとＳｉ−基
板２５は２０秒程度で約２００℃まで温度が上昇し約１
分間保つことで基板上に残留しているＡＩｊｃ１３や塩
素、塩素化合物等は殆んど除去される。このようなマイ
クロ波で照射して基板を加熱すると、基板は短時間でか
つ均一な温度分布で加熱され、残留している塩素やＡｌ
Ｃ（Ｉ３等の塩素化合物が効果的に除去される。In this state, the Si substrate 25, on which the Al wiring film has been dry-etched into a predetermined pattern as described above, is inserted into the output side vacuum chamber 21 using the substrate 26. Then, using the magnetron 24 with the gate valves 27 and 28 closed, the output is 400 W and the frequency is 2.45 G.
The substrate is irradiated with microwaves of H2. Then, the temperature of the Si-substrate 25 rises to about 200°C in about 20 seconds, and the temperature rises to about 1
By keeping it for a few minutes, most of the AIjc13, chlorine, chlorine compounds, etc. remaining on the substrate are removed. When a substrate is heated by irradiation with such microwaves, the substrate is heated in a short time and with a uniform temperature distribution, and the remaining chlorine and Al are heated.
Chlorine compounds such as C(I3) are effectively removed.
ここでマイクロ波を照射する基板が設置されている出力
側の低真空室の真空度はｏ、 ｓ ’ｒｏｒｒ以下の圧
力に保つことが必要で、これ以上の圧力に保つと低真空
室の内部に存在しているガスがマイクロ波で励起され、
プラズマを生じ、基板表面と反応するという不都合が生
じる。The degree of vacuum in the low vacuum chamber on the output side, where the substrate to be irradiated with microwaves is installed, must be maintained at a pressure below o,s'rorr; if the pressure is kept above this, the inside of the low vacuum chamber will be damaged. The gas present in the is excited by microwaves,
This has the disadvantage of generating plasma and reacting with the substrate surface.
また本発明の方法によるとマイクロ波は導波管２３を通
過して８１基板２５上にのみ照射され、装置の金属部分
の箇処にはマイクロ波が吸収されないので、自動化した
基板の搬送機構に悪影響を及ばずこともない。Furthermore, according to the method of the present invention, the microwaves pass through the waveguide 23 and are irradiated only onto the substrate 25, and the microwaves are not absorbed by the metal parts of the device. There are no negative effects.
このよりにＡｊｌ’Ｏ１ａ等の塩素化合物が除去された
基板は、従来のように大気中に存在している水分によっ
て、所定のパターンにエツチングされているＡＩＩの配
線膜が再び侵されることもなく、所望のパターンにエツ
チングされ九Ａ、ｌ配線膜を有する高信頼度の半導体装
置が得られる。As a result, in the substrate from which chlorine compounds such as Ajl'O1a have been removed, the AII wiring film etched into a predetermined pattern will not be corroded again by moisture present in the atmosphere, unlike in the past. A highly reliable semiconductor device having a 9A, 1 wiring film etched into a desired pattern is obtained.
また出力側真空室内で熱処理される時間も短縮され、低
コストの半導体装置が得られる。また以上の実施例の他
にマイクロ波を導波管を通さずに直接出力側真空室の基
板に照射してもよい。Furthermore, the time required for heat treatment in the output-side vacuum chamber is also shortened, and a low-cost semiconductor device can be obtained. In addition to the above embodiments, microwaves may be directly irradiated onto the substrate in the output vacuum chamber without passing through the waveguide.
（２）発明の効果
以上述べたように本発明のエツチング方法によれば、簡
単な装置で薄膜のエツチング後の熱処理時間の短縮した
低コストの半導体装置が得られ、更に所定のパターンに
エツチング後れた配線膜が、エツチングガスの残留成分
によって侵されることがないので高信頼度の半導体装置
が得られる利点を生じる。(2) Effects of the Invention As described above, according to the etching method of the present invention, a low-cost semiconductor device with a shortened heat treatment time after etching a thin film can be obtained using a simple device, and furthermore, a predetermined pattern can be etched into a predetermined pattern. Since the etched wiring film is not attacked by residual components of the etching gas, a highly reliable semiconductor device can be obtained.
４・、 図面の簡単な説明
第１図、第２図は従来の薄膜のエツチング方法を示す概
略図、第８図は本発明の薄膜のエツチング方法を示す概
略図である。4. Brief Description of the Drawings FIGS. 1 and 2 are schematic diagrams showing the conventional thin film etching method, and FIG. 8 is a schematic diagram showing the thin film etching method of the present invention.
図において、２Ａ、、 ２Ｂ、 ２０．２Ｄ、 ２７．
２８はゲートパルプ、３，４．５は排気孔、６，７．８
は真空室、９．２５は８１基板、１０はＳｉ基板設置台
、１１は対向電極、１２は高周波電源、１８はガス導入
孔、１４．２６はベルト、２１は出力側真空室、２２は
マイクロ波透過窓、２８は導波管、２４はマグネトロン
を示す。In the figure, 2A, 2B, 20.2D, 27.
28 is gate pulp, 3, 4.5 is exhaust hole, 6, 7.8
9.25 is the 81 substrate, 10 is the Si substrate installation stand, 11 is the counter electrode, 12 is the high frequency power supply, 18 is the gas introduction hole, 14.26 is the belt, 21 is the output side vacuum chamber, 22 is the micro A wave transmission window, 28 is a waveguide, and 24 is a magnetron.
Claims (2)
側真空室、エツチング室へ順次導入後、該エツチング室
の基板設置台に設置し、エツチング室ヌを導入しながら
基板設置台上の基板上に形成されている素子形成用薄膜
をエツチングし、しかる後該基板を出口側真空室を通過
させてから大気中に取り出す方法において、前記基板を
出口側真空室に導入した時、該基板にマイクロ波を照射
して基板を加熱することを特徴とする薄膜のエツチング
方法。(1) After introducing the semiconductor substrate on which the thin film for element formation has been formed into the entrance side vacuum chamber and the etching chamber in sequence, place it on the substrate installation stand of the etching chamber, and while introducing the etching chamber, place the semiconductor substrate on the substrate installation stand. In a method in which a thin film for element formation formed on a substrate is etched, and then the substrate is passed through an exit vacuum chamber and then taken out into the atmosphere, when the substrate is introduced into the exit vacuum chamber, microscopic A thin film etching method characterized by heating a substrate by irradiating waves.
ｒ以下の圧力としたことを特徴とする特許請求の範囲第
（１）項に記載の薄膜のエツチング方法。(2) The degree of vacuum in the pressure side low vacuum chamber is 0.8'ror.
A method for etching a thin film according to claim 1, characterized in that the pressure is less than or equal to r.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11369682A JPS593927A (en) | 1982-06-29 | 1982-06-29 | Thin film etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11369682A JPS593927A (en) | 1982-06-29 | 1982-06-29 | Thin film etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS593927A true JPS593927A (en) | 1984-01-10 |
Family
ID=14618855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11369682A Pending JPS593927A (en) | 1982-06-29 | 1982-06-29 | Thin film etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593927A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60150633A (en) * | 1984-01-18 | 1985-08-08 | Kokusai Electric Co Ltd | Loadlock chamber of plasma etching device |
| EP0247603A2 (en) * | 1986-05-29 | 1987-12-02 | Fujitsu Limited | A method for stripping a photo resist on an aluminium alloy |
| JPS6482550A (en) * | 1987-09-25 | 1989-03-28 | Toshiba Corp | Surface treatment |
| JPH01294880A (en) * | 1988-05-19 | 1989-11-28 | Mitsubishi Electric Corp | Dry etching device |
| EP0596364A2 (en) * | 1992-10-27 | 1994-05-11 | Nec Corporation | Method of producing semiconductor device having buried contact structure |
| FR2720854A1 (en) * | 1993-12-28 | 1995-12-08 | Fujitsu Ltd | Method of manufacturing semiconductor devices with aluminum wiring by etching and heating under vacuum. |
| EP0725430A2 (en) * | 1995-02-03 | 1996-08-07 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device having capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5691436A (en) * | 1979-12-26 | 1981-07-24 | Fujitsu Ltd | Method for heating semiconductor substrate |
| JPS5747876A (en) * | 1980-09-03 | 1982-03-18 | Toshiba Corp | Plasma etching apparatus and method |
-
1982
- 1982-06-29 JP JP11369682A patent/JPS593927A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5691436A (en) * | 1979-12-26 | 1981-07-24 | Fujitsu Ltd | Method for heating semiconductor substrate |
| JPS5747876A (en) * | 1980-09-03 | 1982-03-18 | Toshiba Corp | Plasma etching apparatus and method |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60150633A (en) * | 1984-01-18 | 1985-08-08 | Kokusai Electric Co Ltd | Loadlock chamber of plasma etching device |
| EP0247603A2 (en) * | 1986-05-29 | 1987-12-02 | Fujitsu Limited | A method for stripping a photo resist on an aluminium alloy |
| US6486073B1 (en) | 1986-05-29 | 2002-11-26 | Fujitsu Limited | Method for stripping a photo resist on an aluminum alloy |
| JPS6482550A (en) * | 1987-09-25 | 1989-03-28 | Toshiba Corp | Surface treatment |
| JPH01294880A (en) * | 1988-05-19 | 1989-11-28 | Mitsubishi Electric Corp | Dry etching device |
| EP0596364A2 (en) * | 1992-10-27 | 1994-05-11 | Nec Corporation | Method of producing semiconductor device having buried contact structure |
| EP0596364A3 (en) * | 1992-10-27 | 1994-06-29 | Nec Corp | Method of producing semiconductor device having buried contact structure |
| FR2720854A1 (en) * | 1993-12-28 | 1995-12-08 | Fujitsu Ltd | Method of manufacturing semiconductor devices with aluminum wiring by etching and heating under vacuum. |
| EP0725430A2 (en) * | 1995-02-03 | 1996-08-07 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device having capacitor |
| EP0725430A3 (en) * | 1995-02-03 | 1998-05-27 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device having capacitor |
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