JPS593892B2 - Power-on reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-on reset circuit, and more particularly to a circuit for clearing the contents of a flip-flop circuit included in a monolithic integrated circuit to a certain state when the power is turned on. It is related to.

Generally, when a monolithic integrated circuit is powered on, the contents of the flip-flop circuits included therein vary depending on the state of the circuits.

For this reason, conventionally, in order to align the contents of the flip-flop circuit in a certain direction when the power is turned on, a clear pulse generation circuit is used, or a charge/discharge circuit consisting of a capacitor and a resistor is provided, and an external clear terminal is pressed with a push button or the like to clear the circuit.
The current situation is that the contents of the flip-flop are cleared one by one by generating errors. However, such conventional methods require an external clear terminal or a special circuit to generate a clear pulse, which has the drawback of increasing the number of parts and requiring power-up. It is also troublesome to perform the clearing operation every time. SUMMARY OF THE INVENTION An object of the present invention is to provide a power-on reset circuit that automatically aligns the contents of a flip-flop circuit in a certain direction upon power-on without requiring such extra components.

According to the present invention, the present invention is a power-on reset circuit that resets the contents of a flip-flop circuit in a monolithic integrated circuit to a constant value when power is turned on, and has a threshold voltage higher than the input threshold voltage of the flip-flop circuit described above. The inverter has an input terminal to which a voltage that follows the power supply voltage is applied, and a reset signal output terminal is connected to the power supply via an impedance element, and the reset signal is applied for a period from when the power is turned on until the output of the inverter changes. A power-on reset circuit is proposed, which is characterized by having an output circuit that outputs a power-on reset circuit.

Embodiments of the power-on reset circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows one embodiment of a power-on reset circuit according to the invention, in which the power supply voltage VDl) and ground are common to the power supply voltage and ground of the monolithic integrated circuit. In the figure, a p-channel transistor 1 and a resistor 2 are connected between a power supply and ground, and the resistor 2 may be a MOS transistor. The output of this resistor 2 is input to a first inverter made up of transistors 3, 4 and 5, and the output of the first inverter is inputted to a second inverter made up of transistors 6, 7 and 8. This first inverter is a circuit for stopping the resetting signal, and the threshold voltage is set so that the output changes to a low level when the power supply voltage becomes higher than the threshold voltage of the flip-flop circuit. This is to stop the reset signal after the flip-flop circuit has been reliably reset. The second inverter is a circuit for delaying the output of the first inverter, and its threshold voltage is set lower than that of the first inverter. This is to ensure that a constant pulse width reset signal can be obtained even when the power supply voltage rises steeply.Furthermore, the threshold voltage of the third inverter is set equal to that of the first inverter. By using the resistor 9, a voltage that follows the power supply voltage is generated at the @ point when the power is turned on, so that the flip-flop circuit that receives the set signal can be reset immediately when the power supply voltage becomes operable. Can be done. Further, the output of the third inverter is outputted from the output terminal 14 via inverters 12 and 13 as necessary. The output terminal 14 serves as a reset terminal for the flip-flop circuit. Next, the operation of the circuit configured as shown in FIG. 1 will be explained with reference to FIG.

In A and B of Fig. 2, curves 4, @, ○, and @ indicate the voltage changes at points 4, ◎, (c), and @ in Fig. 1, respectively, and the threshold voltage 1 in Fig.
The description will be made assuming that VTHP and 1VTHNI are each 1 volt. Note that A in FIG. 2 shows a case where the power supply voltage gradually increases, and B in FIG. 2 shows a case in which the power supply is a step input, but there is no difference in their operation. First, in circuit 1, resistor 2
The voltage 4 increases with the supply voltage, and that voltage is the threshold voltage of the first inverter, in this case 3V.
When , the output voltage 9 of the first inverter starts to fall, and when in the circuit its output voltage reaches the threshold voltage of the second inverter, in this case 2V, current starts flowing through the second inverter and its output becomes The voltage changes as if it were 0. Next, when the output voltage 0 rises and reaches the threshold voltage of the third inverter, 3V in this case, the 5 points become low level and the reset signal is released. Although the circuit shown in FIG. 1 is an example constructed with a CMOS circuit, it is also possible to construct it with MOS transistors of the first polarity.

An example thereof is shown in FIG. The circuit shown in FIG. 3 is almost the same as the circuit shown in FIG.
6 and 27, a third inverter consisting of a resistor 28, transistors 29 and 30, an output terminal 33, and a second circuit including inverters 31 and 32 as necessary. It is composed of circuits. Although FIG. 3 shows the case of an N-type MOS transistor, it is clear that a completely similar circuit can be constructed using a P-type MOS transistor by simply changing the polarity of the transistor. In the circuit of Fig. 3, each point 4, ◎, ◎, O corresponds to each point 4, ◎, ◎, @ in Fig. 1, respectively.
, and the voltage changes at each point are almost the same as those shown in FIG. Of course, in the circuits described above, the circuits shown in FIGS. 1 and 3 may be omitted if the amount of delay is small. As explained in detail above, according to the present invention, the contents of the flip-flop circuit can be automatically reset in a certain direction as soon as the power is turned on without requiring an external clear terminal. This effect is significant.

[Brief explanation of the drawing]

FIG. 1 shows the first circuit of the power-on reset circuit according to the present invention.
Example of FIG. 2 is an explanatory diagram of the operation of the circuit according to the present invention,
FIG. 3 shows another embodiment of the circuit according to the invention. In the figure, 1 is a first circuit, B is a second circuit, and B is a third circuit.

Claims (1)

[Scope of Claims] 1. A power-on reset circuit for resetting the contents of a flip-flop circuit in a monolithic integrated circuit to a constant value upon power-on, the circuit having a threshold voltage higher than an input threshold voltage of the flip-flop circuit; An inverter to which a voltage that follows the power supply voltage is applied to the input terminal and a reset signal output terminal are connected to the power supply via an impedance element, and outputs a reset signal for a period from when the power is turned on until the output of the inverter changes. A power-on reset circuit comprising an output circuit. 2. The output circuit includes a delay circuit that delays the output of the inverter, and stops outputting the reset signal after a certain period of time after the output of the inverter changes. The power-on reset circuit described in item 1.