JPS5935036B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to processing for selecting a frequency-divided signal in a desired octave range in an electronic musical instrument that generates a sound source signal by frequency division.

As a conventionally known tone generator for electronic musical instruments, there is one that uses a frequency dividing circuit.

In this method, the highest frequency signal is successively frequency-divided by multiple stages of frequency dividing circuits to obtain square wave pulse signals of multiple frequencies in parallel. For example, if the number of notes in one octave is 12 and the number of octaves is 5, 60 types of frequency signals can be obtained in parallel. These frequency signals, or sound source signals, are selected according to key presses on the keyboard.
When a plurality of sound generation channels are provided to enable simultaneous generation of a plurality of sounds, all frequency signals are supplied to each sound generation channel, and for each sound generation channel, the frequency signal of the sound assigned to that channel is selected. In this case, since all frequency signals must be supplied to the selection circuits of each channel, there is a drawback that the number of frequency signal supply lines increases considerably. In order to eliminate such drawbacks, Japanese Patent Application No. 52-71822 (
JP-A No. 54-6518), the title of the invention is ``Frequency signal generator'', which generates frequency-divided signals of multiple frequencies by superimposing them, and these frequency-divided signals are generated by superimposing frequency-divided signals of multiple frequencies, and these frequency-divided signals are generated by a number of wirings smaller than the number of frequency-divided signals. Devices have been proposed that are capable of transmitting signals. In the apparatus described in the specification of Japanese Patent Application No. 52-71822, a square wave signal consisting of binary logic levels of "1" and "0" is generated by digitally superimposing a plurality of frequencies, and at least Each time the logic level of the square wave with the highest frequency is inverted, the logic level data of the square wave signals of other frequencies at that time are serialized and generated, thereby superimposing a plurality of frequency signals.

Then, by replacing the logic level data of each of the serialized square wave signals with parallel data and storing each of them, continuous square wave waveform signals of a plurality of frequencies are obtained in parallel. The invention of the present application is to enable an electronic musical instrument using a frequency division force type as a sound source device to efficiently generate only a frequency division signal of a desired pitch (range) selected by pressing a key or the like. purpose.

To achieve this objective, an electronic musical instrument using a frequency signal generator as a sound source device as described in the specification of Japanese Patent Application No. 52-71822 (Japanese Unexamined Patent Publication No. 54-6518) has a desired octave range. It is proposed to enable efficient selection of frequency-divided signals. According to this invention, a plurality of frequency-divided signals obtained by sequentially dividing the highest frequency of each note name are used in
-6518) are generated for each note name in a serialized state (in a dynamic state) using the force formula as described in the specification, and these dynamically superimposed multiple frequency-divided signals are separately generated. When converting (playing) to a static state, dynamically selects only the frequency-divided signal of the octave range to which the pressed key belongs, without reproducing all the frequency-divided signals, Only the selected frequency-divided signal is converted to a static state. Therefore, according to the present invention, frequency-divided signals of other ranges (or pitches) that are not pressed remain in the form of superimposed frequency-divided data, and are output as individual frequency-divided signals. is not manifested.

This significantly simplifies the circuit configuration and wiring around the frequency division output when configuring the sound source circuit of an electronic musical instrument using the frequency division method. In other words, the biggest drawback of sound source circuits using the conventional frequency division method is that the frequency signals (divided signals) of pitches corresponding to all keys are always clearly available (ready to use).
Considering that in reality, the number of keys that are pressed at the same time is one to several keys, about 10 keys at most, it is necessary to prepare frequency-divided signals corresponding to many other keys. This was wasted time, and this was a factor in increasing the redundancy of the sound source circuit using the frequency division method. In contrast, according to the present invention, the frequency-divided signal corresponding to each key is hidden in the form of dynamically superimposed frequency-divided data, and only the frequency-divided signal corresponding to the pressed key is hidden. It is extracted from within and generated (manifested) as a sound source signal that can specifically generate an audible sound. Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings.

In FIG. 1, the sound source circuit portion which constitutes the main part of the present invention is constituted by superimposed frequency division signal generation sections 11-1 to 11-12 and independent frequency division signal generation sections 12-1 to 12-n.

The electronic musical instrument 10 shown in FIG. 1 is capable of generating multiple tones at the same time, and if the maximum number of simultaneous tones is n, musical tone generation series 53-1 to 5 are generated corresponding to n sound generation channels.
3-n are provided, respectively. Although the internal outline of only the musical tone generation series 53-1 is illustrated, the other musical tone generation series 53-2 to 53-n have the same configuration. The key press detection circuit 55 is connected to the keyboard 5
4, the key being pressed is detected, and information representing the pressed key is supplied to the sound generation assignment circuit 56. The sound generation assignment circuit 56 is for allocating the sound of the pressed key to an appropriate sound generation channel. Key data KD of the pressed key is generated corresponding to the assigned sound channel. The key data KD includes note data N representing the note name of the pressed key assigned to the channel, octave data O1 representing the octave range of the key, . Key-on data K1, which becomes "1" when the key is pressed and becomes "0" when the key is released, is included. The key data KD corresponding to each channel is used in the tone generation series 53-1 to 53-n corresponding to that channel. For example, the key data KDl (note data N1, octave data O key-on data K1) of the key assigned to the first channel is used in the tone generation series 53-1 corresponding to the first channel. Also, the key data KD2 (note data N2) of the key assigned to the second channel is
, octave data 02, key-on data K2) is the second
Key data KDn of the key used in the musical tone generation sequence 53-2 corresponding to the channel and assigned to the n-th channel
(Nn, OO, Kn) is used in the tone generation sequence 53-n corresponding to the n-th channel. As the key press detection circuit 55 and the sound generation assignment circuit 56, for example,
The device described in the specification of No. 00879 (Japanese Unexamined Patent Publication No. 52-24518) entitled "Key switch detection processing device" or any other appropriate device can be used.

In the above device, the key data KD of each channel is generated from the sound generation allocation circuit 56 in a time-divisional manner, but in such a case, each musical tone generation series 53-1 to 53-n
key data (Nl,
Ol, Kl or N2, O2, K2...NO
, On, Kn) are respectively latched and converted to a static state for use. Superimposed frequency division signal generation section 11
-1 to 11-12 are each of the 12 pitch names C≠, D, D≠...
... are provided corresponding to B and C, respectively.

Each of the superimposed frequency-divided signal generators 11-1 to 11-12 generates at least the highest frequency among a plurality of frequency-divided signals in a relationship (in an octave relationship) obtained by successively dividing the frequency signal corresponding to each note name. Each time the amplitude level of each frequency-divided signal is inverted, data representing the amplitude level of each frequency-divided signal at that time is sequentially output in series. Superimposed frequency division signal generation section 11-
FIG. 2 shows details of the superimposed frequency division signal generating section 11-12 for the C◆ sound as an example of the signals 1 to 11-12. In the figure, multi-input type logic circuit elements such as AND circuits and OR circuits are illustrated using the diagrammatic method as shown in FIGS. 3a and 3b.

This draws one input line on the input side and draws multiple signal lines orthogonal to this input line. The intersection point between the signal line of the signal to be input to the circuit and the input line is surrounded by a circle. For example, the conditional expression for the AND circuit in Figure 3a is A-B-D=Q, and the conditional expression for the OR circuit in Figure 3b is A.
+B+C=Q. Further, the delay flip-flop employs the diagrammatic method shown in FIG. 3c, and although the clock pulses for controlling the input/output timing are not particularly shown, they are all controlled by a common clock pulse. The period of this clock pulse is called one bit time.
The superimposed frequency division signal generation section 11-12 can be roughly divided into a digital oscillation section 14 and a frequency division data creation section 15.

The digital oscillator 14 counts clock pulses at a desired frequency division ratio to generate a fundamental pulse signal P of a desired frequency, and the frequency division data generator 15 sequentially divides the frequency of this fundamental pulse signal P. Digital data (ie, frequency-divided data) regarding a plurality of frequency-divided signals are created. This frequency-divided data is sent out serially via lines 13-12. The digital oscillator 14 includes a 7-stage/1-bit shift register 16 in which seven delay flip-flops and OR circuits are successively connected in cascade, and data A6 and A7 at the sixth and seventh stages of the shift register 16.
and a circuit consisting of the AND circuit 17, the NOR circuit 18, and the NOR circuit 19 that receives the basic pulse signal P, and the first to sixth stages of the shift register 16. It includes a maximum length counter (maximum length counter) consisting of a NOR circuit 20 into which data A1 to A6 of A bit time wide output '1' is produced. The output "1" of the AND circuit 21 is outputted as a basic pulse signal P via the delay flip-flop 22 and the AND circuit 23 to the OR circuit 24, or from the AND circuit 25 to the OR circuit 24. The maximum length counter is set to an initial state by the basic pulse signal P applied via line 26. Therefore, the maximum length counter consisting of the shift register 16 and the like repeats counting from the initial state every time the basic pulse signal P is applied. The modulo number of the maximum length quanta, that is, the oscillation interval of the digital oscillation unit 14 is determined by the input connection state of the AND circuit 21 and the output of the AND circuit 21 by the delay flip-flop 22.
It is determined according to the control of whether or not to delay the process via .
The output data A1 to A7 of each stage of the shift register 16 is input to the AND circuit 21 directly or via an inverter.

In the example of FIG. 2, data Al, A2, A5, A6 and A
7 is directly input, and data A3 and A4 are inverted by an inverter and input. Therefore, when the contents of the maximum length counter, that is, the data A1 to A7 of the shift register 16 are "110011r", the input conditions of the AND circuit 21 are Al, A2, A3, A4, A5, A6,
A7 is established, and the AND circuit 21 generates an output "1".

When the signal on the control line 27 is "1", the AND circuit 23
is enabled, AND circuit 25 is disabled, and a signal delayed by one bit time via delay flip-flop 22 is selected.

When the signal on the control line 27 is 80 degrees, the AND circuit 23 is inoperative, the AND circuit 25 is enabled, and the output of the AND circuit 21 is selected as is (without delay). Therefore, the input connection state of the AND circuit 21 is changed to the maximum length by the pulse signal P on the line 26.
The data contents A1 to A7 are detected when a predetermined number of N clock pulses (not shown) counted from when the counter was set to the initial state are applied to (each delay flip-flop of) the shift register 16. When the signal on the control line 27 is set to 0, the basic pulse signal P is generated at an interval of N bit time (N base), and when the signal on the control line 27 is 1°, the pulse is generated. Signal P occurs at intervals of N+1 bit times (N+1 base). After all, the digital oscillator 14 divides the frequency of the clock pulse for the delay flip-flop to generate the basic pulse signal P, and the frequency division ratio is approximately set by the input connection state of the AND circuit 21. Depending on the signal on control line 27, slight changes are made. The actual oscillation period of the basic pulse signal P obtained by frequency division is the clock pulse period (
For example, it is scaled by around 1 μs). The frequency division data creation unit 15 includes delay flip-flops FFL to FF.
7 memory registers capable of serial shift operation, and 1
a bit adder 28 and a carry output C of the adder 28;
It has a delay flip-flop 29 which delays the signal by one bit time and returns it to the carry input Cl via an OR circuit 30 and an AND circuit 31, and performs a serial addition operation.

During the serial addition operation, the frequency division data creation section 15 serially shifts the contents of the delay flip-flops FFl to FF7, and converts the pulse signal P given from the oscillation section 14 into the data of the least significant bit (the bit of the delay flip-flop FFl). Add to. Control of whether to perform a serial addition operation, that is, a shift operation of delay flip-flops FF1 to FF7, or a memory operation is performed by the output of the set-reset type flip-flop 32. When the output of the flip-flop 32 is 'r', the signal on the shift line 33 becomes '1', the signal on the memory line 34 becomes '0', and the upper delay flip-flop 'F'
The held data is sequentially shifted from F7 to the lower delay flip-flop FF1. Then, the output data of the lowest delay flip-flop FF1 is added to the basic pulse signal P or the carry signal from the delay flip-flop 29 in an adder 28, and the result is input to the highest delay flip-flop FF7. flipflop 3
When the output of 2 is ``0'', the signal on the memory line 34 is ``1'', the signal on the shift line 33 is ``0'', and the data held by the delay flip-flops FF1 to FF7 are self-held. Flip-flop 32 produces a set output "1" only for a bit time corresponding to the number of stages of the register consisting of delay flip-flops FF1-FF7.

To explain this point with reference to FIG. is set. At this time, the signal "1" is read into the second to seventh stages of the shift register 16 via the line 26, and the signal "0" is read into the first stage via the line 26 and the NOR circuit 19.
Since "A" is read, at time slot T2 after one bit time, data A1 to A1 are read as shown in FIG. 4b.
A7 becomes ゛011111F゜. Since this data is sequentially shifted to the right, data A1 to
A7 changes, time slot T8 after 7 bit time
In this case, data A7 of the seventh stage of the shift register 16 falls to O'. This data A7 is inverter 3
6 and is inverted as shown in FIG. 4c and applied to flip-flop 32's set input R. Therefore, the flip-flop 32 is set only for 7 bit times (time slots t1 to T7) from the time when the basic pulse signal P rises to 1F, as shown in FIG. 4d, and produces a set output of "1". . Signal 1C applied to OR circuit 35
is an initial clear signal that becomes "1" when the power is turned on. The data held by each delay flip-flop FFl to FF7 in the memory state (memory line 34 is "1") is represented by Q1 to Q7, and the data output from the delay flip-flop FF1 in the shift state (shift line 33 is "1") is represented by Q1 to Q7. is shown in FIG. 4e. That is, between time slots T and T7, delay flip-flop FF1 outputs data Q1 to Q7 held in registers FF1 to FF7 in series from the lowest order.
The output of this delay flip-flop FFl is the AND circuit 3.
7, applied to the addition input A of the adder 28 via the OR circuit 38; To explain the serial addition operation, first, at time slot t1, the basic pulse signal P is added to the OR circuit 30.
, is added to the addition input Cl of the adder 28 via the AND circuit 31. The AND circuit 31 outputs the signal 61 of the shift line 33.
This makes it possible to operate from time slot t1 to time slot T2. In this time slot t1, the least significant bit data Q is output from the delay flip-flop FF1.
Since 1 is added to the adder 28, the pulse signal P and the least significant bit data Q1 are added. The addition result (this is referred to as Q1') is transferred from the output terminal S to the delay flip-flop F.
Input to F7 and carry output C at that time. is added to the delay flip-flop 29. Next time slot T2
At , the pulse signal P disappears, but the carry signal from the lower bit temporarily held in the delay flip-flop 29 is applied to the addition input Ci and added to the data Q2. Thereafter, the carry signal from the addition result of the lower bits and the data Q3 to Q7 of the upper bits are sequentially added, and the serial addition ends at time slot T7. At the end of this, when the time slot T8 is reached, the flip-flop 32
Since the output of the memory line 34 becomes "0" and the output of the memory line 34 becomes "1", the addition results performed in the time slots t1 to T7 are self-held in each of the delay flip-flops FF1 to FF7. By the series addition in 15, the basic pulse 7.P(y±, 1.,
±, ±, ↓, ±, ±. 62P428'16232'64
The respective frequencies are divided at a frequency division ratio of 2128, and frequency-divided data corresponding to the logic level of each frequency-divided signal is stored and held in each delay flip-flop FF1 to FF7, respectively.

The frequency division data Q1 to Q7 created as described above in the frequency division data creation section 15 are connected to the line 39, the OR circuit 40,
It is output in series via the AND circuit 41.

The AND circuit 41 is enabled to operate only during the time slots t1 to T7 in FIG. 4 by the output of the flip-flop 32, and the frequency-divided data is output only during this time. That is, the output data Q1-Q7 of the delay flip-flop FF1 generated as shown in FIG. Ru. Since the aforementioned serial addition operation is performed after the delay flip-flop FF1, the frequency-divided data Q1-Q7 outputted via line 39 represents the previous serial addition result. By the way, in the time slot t1, the basic pulse signal P is outputted to the line 13-12 via the OR circuit 40 and the AND circuit 41.

Since this basic pulse signal P is always "1" in the time slot t1, it has priority over the frequency-divided data Q, and the data Q1 is canceled. Therefore, the superimposed frequency division signal generation section 1
The contents of the data sent from line 1-12 to line 13-12 are as shown in FIG. 4f. That is, the frequency division data Q2
By serializing ~Q7, we are effectively superimposing the divided signals. The basic pulse signal P appearing at the beginning of the frequency-divided data Q2 to Q7 is used as a timing signal for extracting desired frequency-divided data Q2 to Q7 in the individual frequency-divided signal generators 12-1 to 12-n. It is extremely important to superimpose such a timing signal P together with the frequency-divided data Q2 to Q7 in order to know the time slot where the superimposed frequency-divided signal is located. In the example shown in FIG. 2, slight switching changes in the generation intervals of the basic pulse signals P are made in a fixed combination while four pulse signals P are generated.

This combination is determined depending on the setting position of the switch 42.
The switch 42 has four terminals Bl, B2, B3, and B4, and the basic pulse signal P is connected to the grounded terminal B1.
The signal "1" is not given even once during the period in which the signal "1" is given. The lowest frequency division data Q1 is input from the delay flip-flop FFl of the frequency division data generation section 15 to the terminal B2, and the signal "1" is input twice while the four basic pulse signals P are applied. Given. delay flip-flop F
Frequency division data Q1 and Q held in Fl and FF2
2 is applied to an AND circuit 43 and an OR circuit 44, the output of the AND circuit 43 is applied to terminal B3, and the output of the OR circuit 44 is applied to terminal B4. Therefore, the signal "1" is supplied to the terminal B3 only once during the generation of four basic pulse signals P. Further, the signal "1" is applied to the terminal B4 three times while the four basic pulse signals P are generated. The values of the frequency division data Ql and Q2 of the lower 2 bits and each terminal B1 to B of the switch 42
Table 1 shows the relationship with the value of the signal added to 4. The output of switch 42 is applied to control line 27 via delay flip-flop 45 to control the frequency division ratio of digital oscillator 14, that is, the generation interval of basic pulse signal P.

As mentioned above, if the frequency division ratio set by the AND circuit 21 is N-ary, when the signal on the control line 27 becomes ``1'', the basic pulse signal P is generated at the N+1-ary frequency division ratio, and the line When the signal No. 27 becomes "0", it is generated at an N-adic frequency division ratio. Therefore, the frequency division ratio for generating the basic pulse signal P in the digital oscillator 14 is always N-ary when the switch 42 is set to terminal B1, but N-ary and N+1 when it is set to terminal B2. It is a repetition of decimal, and terminal B3
When set to , N-base continues three times and then becomes N+1-base only once, and when set to terminal B4, N-base continues once and then N+1-base three times. In the example of FIG. 2, switch 42 is set at terminal B4.

The input condition of the AND circuit 21 in the digital oscillator 14 is "AltA2pA3pA4pA5pA6pA
7'', which means that the maximum length counter in the configuration shown in the figure is set to 112 (N=112). The generation state of the basic pulse signal P in this case is shown in FIG. 5a. The numbers in FIG. 5a indicate the number of clock pulses included therebetween, that is, the division ratio with reference to the clock pulses. As mentioned above, the AND circuit 41 outputs the basic pulse signal P and then the frequency-divided data Q.
2 to Q7 are output in series. Figure 5b is line 13
-12, this frequency-divided data string Dl, D2, D3
This shows the state of occurrence of... Each frequency-divided data string Dl, D2, D3, . . . includes frequency-divided data Q2 to Q7, respectively, with the basic pulse signal P at the head, as shown in FIG. 4f. Since the frequency division data Q2 having the smallest frequency division ratio is obtained by frequency-dividing the basic pulse signal P, its value is inverted to "1" or 80 degrees every time two reference pulse signals P are generated. Therefore, if a frequency-divided data string is generated at the generation period of the basic pulse signal P, the data string with the same content will be Dl, as shown in FIG. 5b.
It continues twice like Dl, D2, D2...
Each of the frequency-divided data sequences Dl, D2, D3, . . . may be generated only once, but there is no particular problem even if they occur twice as in this example. Each frequency division data string Dl, D
As an example of the data contents in 2, D3, . . . , frequency-divided data Q2 and Q3 are extracted and shown in FIGS. 5c and 5d. Frequency-divided data sequence Dl over a longer period of time,
Table 2 shows changes in the data contents of D2....
Among the frequency-divided data Q2 to Q7, the frequency-divided data Q2 repeats inversions of 011 and 10' at the fastest cycle.

Therefore, the signal generated based on the frequency-divided data Q2 is the signal with the highest frequency. As is clear from the numbers shown in FIG. 5a, in the example shown in FIG. 2, the frequency signal obtained based on the frequency division data Q2 is obtained by dividing the delay slip-flop and driving clock pulse by ±. That is, the frequency divider 451 and Q2 are obtained by dividing the basic pulse signal P by 1, and in this example, the clock pulse is divided by 1121 times. This is because four basic pulse signals P are generated by performing frequency division three times.

The frequency signals obtained based on the frequency division data Q3, Q4, Q5, Q6, and Q7 are obtained by dividing the highest frequency signal corresponding to the frequency division data Q2 by -2, 1111, -, -, and 1, respectively.

Therefore, 428216'32 is also generated by superimposing (serially) data of a plurality of frequency signals having an octave relationship.

The reason why the switch 42 is provided to allow slight changes in the frequency division ratio is so that it is possible to obtain delicate frequency division ratios that cannot be divided by only the maximum length counter using the 7-stage shift register 16. This is because.
That is, if the AND circuit 21 is operated when the maximum length counter is in the Nth order, the switch 42 is activated.
4N base and 4N+ corresponding to the four terminals B1 to B4, respectively.
It is possible to obtain the frequency-divided data Q2 with slightly different frequency division ratios such as 1-base, 4N+2-base, and 4N+3-base. As described above, the frequency division data Q2 to Q7 are serially superimposed and outputted from the superimposed frequency division signal generating section 11-12 every time the basic pulse signal P is generated.

These superimposed frequency-divided signals are applied to each tone generation series 53-1 to 53-n via line 13-12. Other note names C,
The superimposed frequency division signal generating sections 11-1 to 11-11 regarding B, A+, . However, in each superimposed frequency division signal generation section 11-1 to 11-12, the digital oscillation section 1
The input connection state of the AND circuit 21 (Fig. 2) in 4 and the setting mode of the switch 42 (Fig. 2) for fine adjustment of the frequency division ratio are different from each other, and correspond to the musical tone frequency of each note name C-B. The frequency-divided data Q2 to Q7 can be generated by being superimposed on the respective output lines 13-1 to 13-12. AND circuit 21 in each generation section 11-1 to 11-12
Input conditions A1 to A7 and setting position B1 of switch 42
An example of ~B4 is shown in Table 3. In Table 3, the N column indicates the maximum value depending on the input connection state of the AND circuit 21.
The original frequency division ratio obtained by the length counter (shift register 16, etc.) is shown, and the columns 1, 2, 3, and 4 show each frequency division ratio when generating four basic pulse signals P. , and differs slightly depending on the setting position of the switch 42. The Q2 column is the sum of the above four frequency division ratios, that is, the frequency division ratio Q2 corresponding to the highest frequency among the frequency division data Q2 to Q7 for each note led to the output lines 13-1 to 13-12. This shows the frequency division ratio. The numbers indicating the direction and frequency division ratio indicate the period of the frequency division signal when the period of the clock pulse for driving the shift registers is set to 1.

For example, if the period of this clock pulse is approximately 1 μs, the period of the frequency signal obtained based on the C tone frequency division data Q2 is approximately 239 μs, and this frequency is approximately 418 μs.
It becomes 4Hz. This is the frequency of the 8-foot C8 note. Further, the period of the frequency signal obtained based on the frequency division data Q2 of the C4# sound is approximately 450 μs, and this period. The wave number is approximately 2217 Hz. This is the frequency of C7≠sound in the 8-foot system. Therefore, the frequency division data Q generated from each superimposed frequency division signal generation section 11-1 to 11-12
The highest frequency signals obtained based on 2 are C7◆J7J7◆POlA7+PB7s and C
It is an 8-tone signal. In addition, each generation unit 11-1 to 11-
12 is generated by superimposing six frequency-divided data Q2 to Q7, as described above. Here, the frequency-divided data Q3 to Q7 correspond to the frequency-divided data Q2 that is successively divided. Therefore,
Frequency division data Q7 corresponding to the lowest frequency is frequency division data Q2
It corresponds to the happy frequency division of
The frequency signal 3) is obtained based on the frequency division data Q7. Therefore, in FIG. 1, if the period of the clock pulse is approximately 1 μs, the divided data Q2~ corresponding to the musical sound source signal in the range from C2≠ to C8 in the 8-foot system.
Q7 is generated from each superimposed frequency division signal generating section 11-1 to 11-12. Lines 13-1 to 13-1 for each note name
The superimposed frequency-divided data Q2 to Q7 sent out in step 2 are added to all tone generation sequences 53-1 to 53-n, respectively.

The musical tone generation series 53-1 to 53-n are provided with note selection circuits 57-1 to 57-n, respectively, and each line 1
The superimposed frequency-divided data Q2 to Q7 of 3-1 to 13-12 are input to note select circuits 57-1 to 57-n, respectively. Note select circuit 57-1 (57-2 to 57-
Based on note data N, (N2...Nn) given from the pronunciation assignment circuit 56, the line (1
3-1 to 13-12) superimposed frequency division data Q
Select 2 to Q7. Each occurrence series 53-1 to 53-n
The superimposed frequency division data Q2 to 1 regarding the single note name selected by the note select circuits 57-1 to 57-n, respectively.
Q7 is input to individual frequency division signal generating sections 12-1 to 12-n, respectively. For example, when the first channel C note is assigned, the note data N1 represents the C note, and the note select circuit 57-1 uses the superimposed frequency divided data Q2 to Q7 of the line 13-1 corresponding to the C note. is selected and applied to the independent frequency division signal generator 12-1 via line 13A. FIG. 6 shows an example of the note select circuit 57-1. For example, if note data N1 is given as a 4-bit code signal in a time-sharing manner, after this code signal is decoded by the decoder 60, It is latched by the latch circuit 61.

Among the outputs of the latch circuit 61, only a single output corresponding to the note name represented by the note data N1 is "1". Twelve AND circuits 62 are provided corresponding to each note name.
The output of latch circuit 61 enables a single AND circuit 62. Superimposed frequency division data supply lines 13-1 to 13-12 corresponding to each note name are individually input to each AND circuit 62, and data corresponding to a single note name is inputted via the single AND circuit 62. Line (13-1 to 13-12
) is selected. The output of each AND circuit 62 is led to line 13A via OR circuit 63, and is applied to independent frequency division signal generating section 12-1. Note select circuits 57-2 to 57-o for other channels also have the same configuration as in FIG. 6. Independent frequency division signal generators 12-1 to 12-
n is provided for each musical tone generation series 53-1 to 53-n, and from among the superimposed frequency-divided data Q2 to Q7,
It functions to take out only frequency-divided data corresponding to the range of the sound assigned to the channel and generate a frequency-divided signal based on the frequency-divided data.

Therefore, octave data 01 to 00 representing the octave range of the sound assigned to the channel is added to each individual frequency division signal generator 12-1 to 12-n, and the range specified by this octave data 01 to 00 is The frequency-divided data (Q2 to Q7) are selected. FIG. 7 shows an example of the independent frequency division signal generation section 12-1, and the independent frequency division signal generation sections 12-2 to 12-n of other channels have the same configuration.

The superimposed frequency-divided data Q2 to Q7 of the note name selected by the note select circuit 57-1 are input to the first stage S1 of the shift register 46 via the line 13A. The shift register 46 and delay flip-flops of the independent frequency division signal generation sections 12-1 (12-2 to 12-n) are clocked by the same clock pulse as that used in the superimposed frequency division signal generation sections 11-1 to 11-12. and operate synchronously. The 7-stage/1-bit shift register 46 is the first
A serial shift operation is performed sequentially from stage S1 to seventh stage S7.

Therefore, the frequency-divided data Q2 to Q7 sequentially read into the shift register 46 with the basic pulse signal P at the beginning via the line 13A are transferred to the first stage S as shown in FIG. 8a.
The stages are sequentially shifted from the first stage to the seventh stage S7. The frequency-divided data Q2 to Q7 that have been serially superimposed are parallelized in this shift register 46. The outputs of the first stage S1 to the third stage S3 of the shift register 46 are connected to data input terminals of a latch circuit 47, respectively. The latch circuit 47 latches the frequency division data (any of Q2 to Q7) corresponding to the tone range specified by the audio/z turn data 01, and returns it to a static state (normal frequency division signal state). In this example,
Since 8-foot system, 4-foot system, and 2-foot system sound source signals are generated respectively, the storage position of the latch circuit 47 is set to 3 bits corresponding to each foot system, but a single In the case of foot system only, 1 bit is sufficient. A signal obtained by inverting the output of the first stage S1 of the shift register 46 by the inverter 49 and the outputs of the second stage S2 to the seventh stage S7 are input to the NOR circuit 48.

This NOR circuit 48 is for detecting the basic pulse signal P (that is, the frequency-divided data string Dl, D2, . . .
(to detect the arrival of Further, the outputs of the fourth stage S4 to the seventh stage S7 of the shift register 46 are connected to AND circuits 64 to 67, respectively.
These AND circuits 64 to 67 output octave data 01
Frequency division data (Q2~
This is for dynamically selecting the force of Q7.
For example, if octave data 01 is supplied in the form of a code signal from the sound generation allocation circuit 56 in a time-division manner, this octave data 01 is decoded for each octave range by a decoder 69, and the output of this decoder 69 is sent to a latch circuit 70. Latch it to a static state.

Octave select data 0S decoded in this way
、． One of 0S2, 0S3, and 0S0 becomes "1". The relationship between octave data 01 and the octave select data 0S1 to 0S3, 0S0 obtained by decoding it and its tonal range are shown in Table 4. The range is based on the 8-foot system.C2≠~C3 is the first range, C
3≠~C4 is the second range, C4≠~C5 is the third range, C5
≠~C6 will be referred to as the fourth range.

If the octave data 01 is supplied in a static state from the tone allocation circuit 56, the latch circuit 70
is not necessary. Octave select data 0S1 corresponding to the first range is added to the AND circuit 67, and octave select data 0S2 corresponding to the second range is added to the AND circuit 67.
Join 6. Further, the 7-octave select data 0S3 corresponding to the third range is sent to the AND circuit 65, and the octave select data 0S2 corresponding to the fourth range is sent to the AND circuit 64.
will be added to each. Therefore, a single AND circuit (64 to 6
7) becomes operational. When the basic pulse signal P is shifted to the stage (one of S4 to S7) corresponding to the AND circuits 64 to 67 that are enabled to operate, the AND circuits 64 to 67
7 operates and applies the output "1" to the OR circuit 68. The arrival of the basic pulse signal P, that is, the arrival of the frequency-divided data Q2 to Q7, is detected as follows.

Since the frequency-divided data Q2 to Q7 are always sent after the basic pulse signal P, the line 13A must be
No signal appears at A (it is '0'). Therefore, the basic pulse signal P is applied to the first stage S1 of the shift register 46.
When the data is read, all outputs from the second stage S2 to the seventh stage S7 representing the signal states of the previous 6 bit times are 0'. This time is indicated by timing T,' in FIG. By reading the basic pulse signal P into the first stage S1 of the shift register 46, the output of the first stage S1 becomes '1', and the output of the inverter 49 becomes O'. The NOR circuit 48 includes the output of the inverter 49 and the second stage S2 to the seventh stage S.
7 is input, and an output "1" is produced at timing t1'.The output "1" of the NOR circuit 48 is applied to the set input S of the set-reset type flip-flop 50.

As a result, as shown in FIG. 8b, the flip-flop 5
0 is in the set state, and the output on the set side is delayed by one bit time by the delay flip-flop 51 as shown in FIG. 8c, and then applied to the AND circuit 52. In this way, the AND circuit 52 is set to an operable state. The outputs of the aforementioned AND circuits 64 to 67 are applied to the other inputs of the AND circuit 52 via an OR circuit 68, and also to the reset input R of the flip-flop 50.

Since the basic pulse signal P always precedes the frequency-divided data Q2 to Q7, when the output ``1'' is generated from the AND circuits 64 to 67 based on the basic pulse signal P, the first reset signal is sent to the flip-flop 50. Then, the flip-flop 50 is reset. At the same time, the condition of the AND circuit 52 is satisfied, and the output "1" of the AND circuit 52 is applied to the strobe input S of the latch circuit 47. When the flip-flop 50 is reset, the output of the delay flip-flop 51 becomes "0" after one bit time. Therefore, even if the output "1" is generated from the OR circuit 68 thereafter, the AND circuit 52 does not operate. Therefore, the strobe pulse SP applied from the AND circuit 52 to the latch circuit 47 occurs only for one bit time. The timing at which this strobe pulse SP occurs is the octave select data 0S, ~0
Determined by S3,0S0.

First, when the octave select data 0S0 is "1", the AND circuit 64 operates when the basic pulse signal P enters the fourth stage S4 of the shift register 46, and the strobe pulse SP is generated at timing T4' ( Figure 8d).

Therefore, frequency-divided data Q4, Q3, and Q2 are read into the latch circuit 47 from stages S1 to S3 of the shift register 46 (see FIG. 8a). Every time the frequency-divided data Q2 to Q7 are given, that is, together with the basic pulse signal P, the frequency-divided data strings Dl, D2, D3 . ...... (see Table 2), the frequency division data Q stored in the latch circuit 47 is
The data contents of 4, Q3, and Q2 are rewritten. The level of the signal output from each storage location of this latch circuit 47 (
"1", "0") change each time the logic level of each frequency division data Q2 to Q4 applied via the line 13A changes. Therefore, the superimposed frequency division signal generation units 11-1 to 11
Of the frequency-divided data generated from -12, only square-wave sound source signals corresponding to the frequency-divided data Q2 to Q4 of the tone range actually produced are outputted from the latch circuit 47. Figure 5 E
, f are used to illustrate that the output of the latch circuit 47 is a square wave signal, and show force wave sound source signals output from the latch circuit 47 based on the frequency division data Q2 and Q3. be. By the way, the latch circuit 47 that latches the data of the first stage S1 of the shift register 46
The output signal at the storage location is outputted via line 71 as an 8-foot sound source signal. In this example, the frequency division data Q
2 to Q7 are serialized in descending order of frequency division ratio, so
The second stage S2 of the shift register 46 contains data divided by one octave above the first stage S1. Therefore, the output signal at the storage location of the latch circuit 47 that latched the data of the second stage S2 corresponds to a 4-foot sound source signal, and is outputted via the line 72. Also, since the third stage S3 receives frequency-divided data one octave higher than that of the second stage S2, the output signal at the storage location of the latch circuit 47 that latches the data of the third stage S3 becomes a 2-foot sound source signal. and is output via line 73. When the octave select data 0S3 representing the third range is "1", the fifth stage S of the shift register 46
When the basic pulse signal P is input to 5, the strobe pulse S
P occurs.

Therefore, as shown in FIG. 8e, the strobe pulse SP is generated at timing T5', and the divided data Q5, Q4
, Q3 are latched by the latch circuit 47. Furthermore, when the octave select data 0S2 representing the second range is "1", the AND circuit 66 operates when the basic pulse signal P enters the sixth stage S6 of the shift register 46, and as shown in FIG. A strobe pulse SP is generated.
As a result, the frequency-divided data Q6, Q5, and Q4 are transferred to the latch circuit 4.
It is latched at 7. Further, when the octave select data 0S1 representing the first range is "1", the AND circuit 67 operates when the basic nocare signal P enters the seventh stage S7 of the shift register 46, as shown in FIG. 8g. The strobe pulse SP is generated at timing t'7. As a result, the frequency-divided data Q7, which is stored in the first stage S1 to the third stage S3 of the shift register 46,
Q6 and Q5 (see timing t/7 in FIG. 8a) are latched by the latch circuit 47. As described above, in the individual frequency division signal generation section 12-1 (12-2 to 12-n), only the frequency division signal in the range corresponding to octave data 01 (02 to 0n) is sent to line 71 (or 72, 73). Output via .

Although the frequency-divided signals of other sound ranges exist in the serially superimposed state of frequency-divided data Q2 to Q7, they do not exist as a single frequency-divided signal that can be used immediately. In the above example, since the number of foot systems is made plural, the latch circuit 47 is made to have multiple bits, and multiple frequency divided signals are generated, but this is different from generating unnecessary frequency divided signals as in the conventional case. Not that there is. If the foot system is made single, the latch circuit 47 will be made a single bit, and only a frequency-divided signal in a single octave range will be generated. The frequency division signals (square wave sound source signals) of each foot system generated from the individual frequency division signal generation units 12-1 to 12-n are applied to the switching circuits 58-1 to 58-n, respectively.

In the opening/closing circuits 58-1 to 58-n of each channel, key-on data Kl,
K2i... Controls opening and closing of the sound source signal based on Kn. The sound source signals output from the opening/closing circuits 58-1 to 58-n are mixed for each foot system between the musical tone generation series 53-1 to 53-n, and then supplied to a tone filter (not shown) or the like. . In the above example, the electronic extra device 10 is a compound musical instrument, but it goes without saying that the present invention can also be applied to a single musical instrument.

In that case, it is sufficient to have a single musical tone generation sequence (a single independent frequency-divided signal generation section). As explained above, according to the present invention, only the frequency-divided signal corresponding to the range selected by pressing a key etc. is generated, and the frequency-divided signals of other ranges are not generated independently, so that the sound source of the electronic musical instrument The redundancy of the frequency dividing circuit is improved, contributing to the simplification of the circuit configuration and cost reduction.

In particular, in the independent frequency division signal generation section, only the frequency division data corresponding to the desired tone range is selected from the dynamically superimposed frequency division data, so the frequency division data is latched. The number of latch circuits required for converting the selected data into a square wave signal is economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the electronic musical instrument of the present invention, FIG. 2 is a detailed circuit diagram showing an example of the superimposed frequency division signal generating section of FIG. 1, and FIG. 3 is a method of illustrating various circuit elements. FIG. 4 is a timing chart for explaining the operation of FIG. 2, and FIGS. A timing chart showing how the signals are generated in a superimposed manner; FIG. 1 is a block diagram showing an example of the note select circuit shown in FIG. 1, FIG. 7 is a circuit diagram showing an example of the independent frequency division signal generator shown in FIG. 1, and FIG. This is a timing chart. 10...Electronic musical instruments, 11-1 to 11-12.
...Superimposed frequency division signal generation section, 12-1 to 12-n
...Independent frequency division signal generation unit, 14...Digital oscillation unit, 15...Divide data creation unit, 1
6...Shift register, 53-1 to 53-n
...Musical sound generation series, 57-1 to 57-n...
...Note select circuit.

Claims (1)

[Claims] 1. Every time the amplitude level of at least the highest frequency divided signal among a plurality of frequency divided signals that are sequentially divided, data representing the amplitude level of each of these frequency divided signals is inverted. A first circuit that is assigned to different time slots and outputs serially, and data that corresponds to a range selected by pressing a key etc. from among the serialized data output from this first circuit is selected. and a second circuit that holds and outputs the selected data until data of the same range is given from the first circuit, and the selected data is selected from the second circuit by pressing a key or the like. An electronic musical instrument that independently generates a frequency-divided signal in the specified range. 2. The second circuit is connected to a shift register that reads serialized data outputted from the first circuit and sequentially shifts the data, and is capable of storing data at a predetermined storage location of the shift register. Claim 1, comprising: a latch circuit; and a circuit that applies a strobe pulse to the latch circuit when the data shift timing in the shift register corresponds to a range selected by pressing a key or the like. Electronic musical instruments listed in section.