JPS5933876A - MIS type semiconductor device - Google Patents

Abstract

PURPOSE:To improve the insulating breakdown strength of a gate insulated film, to reduce the resistance of a gate electrode, to prevent the disconnection of the stepped part of the gate electrode and to enable to ultrafinely form an element by contacting the gate insulated film with an insulator, and contacting the part of the gate electrode directly with the extension of the semiconductor film and utilizing the extension as part of the gate. CONSTITUTION:A substantially cross-shaped insular single crystal silicon film 34 having extensions 33, 34 extending in channel width direction is formed to n<+> type source and drain regions 35, 36 electrically decomposed on a sapphire substrate 21, a channel region 37 formed between the regions 35 and 36 and the channel region 37. Narrow oxidized units 27, 27 which reach the surface of the substrate 21 are buried between the region 37 and the extensions 33, 33, and an N-channel MOS transistor which is formed through a gate oxidized film 31 covered on the region 37 with a gate electrode 30 is formed on the region 37 and the extensions 33, 33. In this manner, the gate breakdown can be eliminated, thereby preventing the back channel effect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an MIS type semiconductor device having a structure in which a MIS transistor is formed on an insulating substrate.

[Technical background of the invention and its problems]

This type of MIS type semiconductor device, for example, 5O8 (Sili
Compared to bulk semiconductor devices using silicon substrates, semiconductor devices typified by con on 5apphire have smaller stray capacitances between wiring and the substrate, between diffusion layers and the substrate, etc.
In addition, since the isolation between elements is perfect, it has the advantage of realizing high-speed operation and high density.

Incidentally, the MO8 type semiconductor device having the above-mentioned SOS structure has conventionally been manufactured by the following method.

First, a p-type single crystal silicon film is deposited on a sapphire substrate 1 by vapor phase growth, and this is patterned using an anisotropic etching method to form an island-shaped silicon film 2 with a trapezoidal cross section.
(Illustrated in Figure 1(, )). Subsequently, an f-) electrode 4 made of, for example, arsenic doped polycrystalline silicon is formed on the p-type silicon film 2 via a dirt oxide film 3, and using this dirt electrode 4 as a mask, an n-type impurity is transferred to the p-type. A layered source made by doping silicon H2.

A drain region 5.6 is formed. Next, CVD is applied to the entire surface.
- 8in2 film 7 is deposited, contact holes 8 are formed in parts of the 5I02 film 7 corresponding to the source and drain regions 5 and 6;
After opening a hole 8 and depositing AtM on the entire surface, this is patterned to form source and drain electrodes 9 and 10 to manufacture a MOS transistor (as shown in FIG. 1(b)).
.

According to the above method, the island-shaped silicon film 2 can be separated in a simple process, but it has various drawbacks as follows. The first drawback is the effect of parasitic MO transistors generated on the side surfaces of the island-shaped silicon film 2. This is a MOS having a (100) plane orientation on the surface of the island-like silicon film 2).
S) Ranjinuta (100) side also many 81-8
This is due to the presence of 102 interface states. This parasitic MO8
) The transistor effect causes an increase in leakage current and a decrease in reliability. The second drawback is that the dielectric breakdown voltage of the dirt oxide film 3 grown on the side surface of the island-shaped silicon film 2 is low. That is, as shown in FIG. 2, the thermal oxide film 1, which becomes the ff-) oxide film 3, does not grow uniformly on the side surface of the island-shaped silicon film 2, and becomes thin near the interface of the sapphire substrate 1. . This is thought to be caused by oxygen deficiency at the interface of the zaphire substrate 1 at the end of the isolated island-like silicon film 2.

On the other hand, as another method for manufacturing a MOS transistor having an SO8 structure, a method using an isolation technique using selective oxidation as described below is known. First, a p''' type single crystal silicon film is grown in a vapor phase on a sapphire substrate 1, an oxide film and an oxidation-resistant silicon nitride film are formed on this silicon film, and then a silicon nitride film that will become an element isolation region is sequentially grown.・Flat turning is performed to form nine turns 12 of the silicon nitride film and a turn 13 of the oxide film.Next, using the silicon nitride film pattern 12 as an oxidation-resistant mask, heat treatment is performed in a high temperature oxygen atmosphere to form a field oxide film (element). A separation region) 14 is formed to form an island-shaped silicon film 15 (as shown in FIG. 3(, )).

Next, after removing the silicon nitride film pattern 12 and the oxide film pattern 13, a MOS transistor is fabricated on the island-shaped silicon film 15 in the same manner as described above (see FIG. 3(b)).
).

Although the above method can improve the above-mentioned decrease in dielectric breakdown voltage of the dirt oxide film, it has the following drawbacks.

■ Since long-time heat treatment at high temperatures is required to form the thick field oxide film 14, a large amount of interfacial charge is generated in the silicon nitride due to autodoping of At from the sapphire substrate 1, leading to an increase in leakage current. invite In particular, when a transistor is formed in the island-shaped silicon film 15 (in the n-channel width direction), the source.

The drain regions 5 and 6 conduct through the interface regardless of the voltage applied to the dirt electrode 4, producing a so-called packed channel effect.

■ After forming the field oxide film 14, silicon nitridation!
Strong stress is generated under the pattern 12, particularly near the thick field oxide film 14, and induces crystal defects in the silicon film 15. This results in deterioration of Devine characteristics, particularly an increase in leakage current.

5-(2) When forming the thick field oxide film 14, oxidation progresses laterally below the silicon nitride film turn 12, reducing the device size. This requires a margin in mask dimensions, which in turn becomes an obstacle to miniaturization of element dimensions and inter-element dimensions.

[Purpose of the invention]

The present invention solves all the problems of conventional element isolation technology,
It is an object of the present invention to provide a MIS type semiconductor device in which the dielectric breakdown voltage of the dirt insulating film is improved, the resistance of the dirt electrode is lowered, and the element is miniaturized.

[Summary of the invention]

The present invention provides source and drain regions of one conductivity type electrically isolated from each other on an insulating substrate, a channel region formed between these regions, and an extension υ connected to the channel region and extending in the channel width direction. An island-shaped semiconductor film having a substantially cross shape consisting of a protrusion is provided, and a narrow insulator serving as isolation between elements is provided between the channel region and the protrusion of the semiconductor film on the surface of the insulating substrate. furthermore, a dart electrode is provided on the channel region and the extension portion through a dart insulating film that covers at least the channel region, the dirt insulating film is in contact with the insulator, and the dart electrode is in contact with the insulator; The dielectric breakdown strength of the dart insulating film can be improved by bringing a part into direct contact with the extended part of the semiconductor film and using the extended part as part of the dart.
-) Lower resistance of the electrode, prevention of disconnection at the step part of the dart electrode,
The main goal is to achieve miniaturization of devices.

[Embodiments of the invention]

Next, the n-channel MO8LSI of the present invention is shown in FIG.
) to (, ) and the manufacturing method shown in FIGS. 5 and 6 will be described together.

(1) First, an insulating substrate (for example, a sapphire substrate) 2
A single crystal silicon film 22 was heteroepitaxially grown on the wafer 1 to produce an SOS wafer. Subsequently, a thin silicon nitride film 23 was deposited on the single-crystal silicon film 22, and a resist pattern 24 in which intended isolation regions were formed was formed on the nitride film 23 by photolithography. Subsequently, using the resist pattern 24 as a mask, the nitride film 23 is
was selectively etched away to form an opening 25 (
Figure 4 (, ) illustration).

(11) Next, the single crystal silicon film 22 exposed from the opening 25 of the nitride film 23 is etched using, for example, reactive ion etching (RIE) using the resist holes and turns 24 as a mask.
) was selectively etched to form a narrow groove portion 26 that reached the sapphire substrate 21 (as shown in FIG. 4(b)).

Subsequently, after removing the resist pattern 24, heat treatment was performed in a high temperature oxygen atmosphere using the silicon nitride film 23 having the opening 25 as an oxidation-resistant mask. At this time, the exposed inner surface of the groove 26 is oxidized and the oxidant 2 fills the groove 26.
7 was formed (as shown in FIG. 4(c)).

Next, the silicon nitride film 23 is removed, and a thermal oxidation process is performed to grow a thin oxide film on the entire single crystal silicon film 22.The hind oxide film is selectively removed to form an oxide film 27.
．． An oxide film 28 was left in the element region between 27 and a polycrystalline silicon film 29 was further deposited on the entire surface (as shown in FIG. 4(d)).

Note that, prior to depositing this polycrystalline silicon film 29, p-type impurity such as poron may be ion-implanted into the intended channel region of the element region in order to control the threshold value.

(I) Next, the polycrystalline silicon film 29 is patterned 17 to form a gate electrode 30, and the thin oxide film 28 is selectively etched away using the dirt electrode 30 as a mask to form a dirt oxide film 31. The single-crystal silicon film 22 was patterned to form an island-shaped single-crystal silicon film 34 having an element region 32 and an extension 33W orthogonal to the element region and located below the dart electrode 30. An n-type impurity such as arsenic is ion-implanted and activated to form n-type source and drain regions 35° and 36 in the element region 32 to form an n-channel MO8L.
A Sl, 'i film was produced (illustrated in Figures 4(e), 5, and 6). 5 is a plan view of FIG. 4 (, ), and FIG. 6 is a sectional view taken along line 9------ of FIG. 37 in the figure is a channel region formed between source and drain regions 35 and 36.

Therefore, the MO8LSI of the present invention is shown in FIGS. 4(e) and 5.
As shown in the figure and FIG. 6, n-type sources are electrically isolated from each other on a zaphire substrate 21.

Drain regions 35 and 36, a channel region 37 formed between these regions 35 and 36, and the channel region 37
an extension part 9 connected to the channel width direction and extending in the channel width direction;
An island-like single crystal silicon film 34 having a substantially cross shape consisting of 3 and 33 is provided, and the channel region 37 and the extension portion 3
A dart electrode 30 is embedded in a narrow oxidizer 27.27 reaching the surface of the sapphire substrate 21 between the channel region 37 and the extension portions 33, 33. An n-channel MO8) transistor is provided with a dirt oxide film 31 covering the transistor.

Therefore, both ends of the r-) oxide film 31 in the channel width direction are connected to the film 10 of the island-shaped single-crystal silicon film 34 and the oxide film 27, 27 having a uniform width formed in the thickness direction. It is possible to eliminate the problem of r-) destruction on the side surface of the mold island-like silicon film. In addition, the oxidants 2y, 27iJ, which cause element isolation, cannot be formed without performing high-temperature and long-term thermal oxidation treatment as in the conventional selective oxidation technology, and the back channel caused by autodoping of At from the sapphire substrate 21. effect can be prevented. Furthermore,
The gate electrode 30 is approximately the same as the island-shaped single crystal silicon film 34.
Since it is formed at a height of , the problem of disconnection can be solved and miniaturization can be achieved. Moreover, the gate electrode 30 made of polycrystalline silicon has an oxidant 2
Since the dirt electrode 30 is in direct contact with the low-resistance single-crystal silicon extension 33.33 that is electrically isolated at 7.27, the resistance of the dart electrode 30 can be reduced. Furthermore, since the distance between the device regions is determined only by the width of the groove when forming the oxidizer 27, 27, it is possible to
'High-density MO8L can be reduced to the limit of tank dimensions.
SI can be obtained.

Note that in the method described in the above embodiment, the insulator is formed by thermal oxidation treatment after forming the groove, but the present invention is not limited thereto. For example, in the steps shown in FIGS. 4(a) and 4(b), a groove 26 is formed in the single crystal silicon film 22, the resist pattern 24 and the nitride film 23 are removed, and the single crystal silicon film 22 is removed.
The surface is exposed (as shown in FIG. 7(, )). Subsequently, after depositing a -8IO2 film 38 on the entire surface so thickly that the trench 26 is sufficiently filled (as shown in FIG. 7(b)), CVD-
Etch the 8in2 film 38 and deposit CVD into the groove 26.
A method may be adopted in which the CVD-S s 02 body (insulator) 39 is formed by leaving the 8102 film (as shown in FIG. 7(c)).

In addition, in the method described in the above embodiment, the groove was formed by etching using the resist/arm turn as a mask, but this is not limited to this.
) to (f) may be used. First, a polycrystalline silicon layer 41 is formed on the surface of the single crystal silicon film 22 on the sapphire substrate 2 through an oxide film 4θ on the intended element region.
(as shown in FIG. 8(a)). Subsequently, after performing thermal oxidation treatment to form a thin thermal oxide film (not shown) on the surface of the single crystal silicon film 22 exposing the thick thermal oxide film 42 around the polycrystalline silicon pattern 41, a single crystal silicon film 42 is formed. 2
2. Remove the thin thermal oxide film on the surface (as shown in Figure 8(b))
. Subsequently, a thin metal film 43 such as At is deposited on the entire surface. At this time, the metal film 43 is hardly deposited on the stepped portion of the thick thermal oxide film 420 around the polycrystalline silicon/'P turn 41, or is deposited only thinly compared to other portions. Therefore, by slightly etching the metal film 43, the metal film 43 in the thick thermal oxide film 42 portion corresponding to the side surface of the polycrystalline silicon E-turn 41 is removed to expose the thermal oxide film 42 portion (eighth Figure (C) (Illustrated). Next, as shown in FIG. 8(d), the thermal oxide film 42 was removed and the metal film 43 on the thermal oxide film 42 was lifted off, and the thermal oxide film was removed around the sides of the polycrystalline silicon pattern 41. After exposing the silicon film 22 at the location, single crystal silicon M22YcRJE is applied using the remaining metal film 43' and the oxidized -13 = film 4θ as a mask.
Groove portion 4 that reaches the sapphire substrate 21 by being removed by
4.44 (as shown in FIG. 8(, )). Thereafter, as shown in FIG. 8(f), the remaining metal film 43' and oxide film 40 are sequentially removed. According to such a method, the thermal oxide film 42 around the polycrystalline silicon pattern 41 (especially on the side surfaces)
Since the groove portions 44 and 44 can be formed with dimensions corresponding to the film thickness, a narrow groove portion of 1 μm or less can be easily realized.

In addition, in the manufacturing method of the above embodiment, in order to completely prevent reverse leakage due to fixed charges in the insulator embedded in the groove or at the interface between the insulator and the single crystal silicon film, the groove is It is desirable to introduce impurities into the nearby single crystal silicon film.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide an MO8 type semiconductor device that achieves improved dielectric breakdown voltage of the dirt insulating film, lower resistance of the dirt electrode, and miniaturization of the element.

−14=

[Brief Description of the Drawings] Figures 1(a) and (b) are cross-sectional views showing the manufacturing process of an n-channel MO8+- transistor separated by air insulation according to the conventional method, and Figure 2 is a cross-sectional view showing the manufacturing process of an n-channel MO8+- transistor separated by air insulation according to the conventional method. ), (b)
3(a) and 3(b) are cross-sectional views showing the manufacturing process of an n-channel MO8LSI separated by the conventional selective oxidation method,
Figures 4(,) to (e) are cross-sectional views showing the manufacturing process for obtaining an n-channel MO8LSI'f, which is an embodiment of the present invention; Figure 5 is a plan view of Figure 4(,); Figure 6 is a sectional view taken along the line Vl-Vl in Figure 5, and Figures 7 (a) to (c).
8 is a cross-sectional view showing the step of embedding an insulator that acts as element isolation in the trench, and FIGS. 8(1) to 8(f) are cross-sectional views showing the step of forming the trench in a single-crystal silicon film. 21...Sapphire substrate, 22...Single crystal silicon film, 23...Silicon nitride film, 26.44...Groove portion, 27...Oxide, 30...e-) Electrode, 3・・・
- Dirt oxide film, 32... Element region, 33... Extension portion, 34... Island-shaped single crystal silicon film, 35... Layered source region, 36... N type drain region, 37・・・
・Channel area, 39-CVD-8in2 units. Applicant's agent Patent attorney Takehiko Suzue @
Ward 6

Claims (1)

[Claims] an insulating substrate, a source and drain region of one conductivity type provided on the insulating substrate and electrically isolated from each other, a channel region formed between the source and drain regions, and a region extending from the channel region in the width direction thereof. an island-shaped semiconductor film comprising an extension portion extending to a narrow insulator, and a narrow insulator provided between the channel region and the extension portion of the island-shaped semiconductor film so as to reach the insulating substrate surface trench; A MIS type semiconductor device comprising a dirt electrode provided on the channel region and the extension portion with a dirt insulating film covering at least the channel region.