JPS5931041A - thin film semiconductor device - Google Patents
thin film semiconductor deviceInfo
- Publication number
- JPS5931041A JPS5931041A JP14135382A JP14135382A JPS5931041A JP S5931041 A JPS5931041 A JP S5931041A JP 14135382 A JP14135382 A JP 14135382A JP 14135382 A JP14135382 A JP 14135382A JP S5931041 A JPS5931041 A JP S5931041A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- semiconductor device
- film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010409 thin film Substances 0.000 title claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 3
- 239000010936 titanium Substances 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 22
- 239000011229 interlayer Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 208000018721 fetal lung interstitial tumor Diseases 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は薄膜半導体装置の多層配線のコンタクト部の材
料構成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a material structure of a contact portion of a multilayer wiring of a thin film semiconductor device.
従来、薄膜半導体装置においては、第１図に薄膜ＭＯ８
ＰＥＴの断面図に示すごとく、絶縁基板１の一主面に形
成された半導体膜１２にソース拡散領域３、ドレイン拡
散領域４、ゲート絶縁膜５、ゲート電極６、層間絶縁膜
７および層間絶縁膜を介し、コンタクト・ホールを通し
て形成した電極配線層８により構成されていた。Conventionally, in a thin film semiconductor device, a thin film MO8 is shown in FIG.
As shown in the cross-sectional view of PET, a source diffusion region 3, a drain diffusion region 4, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, and an interlayer insulating film are formed on a semiconductor film 12 formed on one main surface of an insulating substrate 1. It was composed of an electrode wiring layer 8 formed through a contact hole.
しかし、上記従来技術では、例えば半導体膜２やゲート
電極６が多結晶シリコン半導体膜、電極配線層８が酸化
錫と酸化インジウムの混合物膜（以下工ＴＯ膜）で形成
された場合、下地シリコン材料が工Ｔｏ膜中に拡散し、
配線抵抗あるいは接触抵抗が増大するという欠点があっ
た。However, in the above conventional technology, when the semiconductor film 2 and the gate electrode 6 are formed of a polycrystalline silicon semiconductor film, and the electrode wiring layer 8 is formed of a mixture film of tin oxide and indium oxide (hereinafter referred to as TO film), the underlying silicon material diffuses into the To film,
This has the disadvantage that wiring resistance or contact resistance increases.
本発明はかかる従来技術の欠点をなくし、薄膜半導体装
置において、配線抵抗あるいは接触抵抗の小さな多層配
線のコンタクト構造を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a multilayer wiring contact structure with low wiring resistance or contact resistance in a thin film semiconductor device.
上記目的を達成するための本発明の基本的な構成は、薄
膜半導体装置において、絶縁基板上に形成された半導体
膜を用いて、いわゆる薄膜半導体装置を製作するに際し
、絶縁膜を介し、コンタクト・ホールを通して電極配線
との接続を行なうコンタクト部に於て、半導体層と電極
との間に銅。The basic structure of the present invention for achieving the above object is that when a so-called thin film semiconductor device is manufactured using a semiconductor film formed on an insulating substrate in a thin film semiconductor device, contacts are formed through the insulating film. Copper is placed between the semiconductor layer and the electrode in the contact area that connects to the electrode wiring through the hole.
クロム、チタン等の金属層を形成することを特徴とする
。It is characterized by forming a metal layer of chromium, titanium, etc.
第２図は本発明による一実施例を示す薄膜半導体装置の
断面図である。石英からなる絶縁基板１１の一主表面に
はＰ型多結晶ンリコン薄膜１２、該Ｐ型多結晶シリコン
薄膜１２にリンを拡散して形成したソース拡散領域１３
、ドレイン拡散領域１４が形成され、該ソース・ドレイ
ン拡散領域１３．１４にはさまれた半導体基板１３の表
面には酸化ミクロンからなるゲート絶縁膜１５、多結晶
シリコンからなるゲート電極１６が形成され、ＭＯＳ
ＦＬＩＴを構成する。該ＭＯ３ＦＥＴ上には酸化シリ
コン膜からなる層間絶縁膜１７が形成された後、コンタ
クト・ホールが形成され、下地多結晶シリコン層による
配線層と２層目の電極配線層との接続がなされる訳であ
るが、この場合例えばコンタクト・ホール部を通して無
電解銅メノギにより銅層１８を形成後、ＩＴＯ膜による
電極配線層１９をスパッタ蒸着後のホトリゾグラフィー
及びエツチング処理により形成する。FIG. 2 is a sectional view of a thin film semiconductor device showing one embodiment of the present invention. On one main surface of the insulating substrate 11 made of quartz, there is a P-type polycrystalline silicon thin film 12, and a source diffusion region 13 formed by diffusing phosphorus into the P-type polycrystalline silicon thin film 12.
, a drain diffusion region 14 is formed, and a gate insulating film 15 made of micron oxide and a gate electrode 16 made of polycrystalline silicon are formed on the surface of the semiconductor substrate 13 sandwiched between the source/drain diffusion regions 13 and 14. , M.O.S.
Configure FLIT. After an interlayer insulating film 17 made of a silicon oxide film is formed on the MO3FET, a contact hole is formed to connect the wiring layer made of the underlying polycrystalline silicon layer and the second electrode wiring layer. However, in this case, for example, after forming the copper layer 18 using electroless copper metal through the contact hole portion, the electrode wiring layer 19 using an ITO film is formed by photolithography and etching treatment after sputter deposition.
尚、電極配線１９はＩＴＯに限らずアルミニウム等地の
金属による配線でも良く、且つ層間金属層１８はフンタ
クト・ホール内にとどまらずコンタクト・ホール外には
み出して形成されても良い。The electrode wiring 19 is not limited to ITO, but may be made of a metal such as aluminum, and the interlayer metal layer 18 may be formed not only within the contact hole but also protruding outside the contact hole.
上記の如く、本発明によると下地薄膜半導体層と上部電
極配線層との間に他の金属層をはさんで形成することに
より、例えば下地半導体層がシリコンで、上部電極配線
層が工ＴＯの場合に、ＩＴＯが下地シリコン層からシリ
コンを吸収して配線抵抗あるいは接触抵抗を増大させる
のを、中間に形成した銅等のシリコンと相互拡散を起こ
し難い金層をはさむことにより、配線抵抗あるいは接触
抵抗の小なる電極配線の接続が可能となる効果がある。As described above, according to the present invention, by forming another metal layer between the base thin film semiconductor layer and the upper electrode wiring layer, for example, the base semiconductor layer is made of silicon and the upper electrode wiring layer is made of silicon. In some cases, ITO absorbs silicon from the underlying silicon layer and increases the wiring resistance or contact resistance, but by sandwiching a gold layer that does not easily cause interdiffusion with silicon such as copper formed in the middle, the wiring resistance or contact resistance can be increased. This has the effect of making it possible to connect electrode wiring with low resistance.
第１図は従来技術による薄膜半導体装置の断面図を、第
２図は本発明による薄膜半導体装置の断面図を示す。
１．１１・・・・・・絶縁基板
２．１２・・・・・半導体薄膜
６．１６・・・・・・ソース拡散領域
４．１４・・・・・・ドレイン拡散領域５．１５・・・
・・・ゲート絶縁膜
６．１６・・・・・・ゲート電極
７．１７・・・・・・層間絶縁膜
８．１９・・・・・・電極配線層
１８・・・・・・層間金属膜
以 上
出願人 株式会社諏訪精工舎
第１図FIG. 1 shows a sectional view of a thin film semiconductor device according to the prior art, and FIG. 2 shows a sectional view of a thin film semiconductor device according to the present invention. 1.11... Insulating substrate 2.12... Semiconductor thin film 6.16... Source diffusion region 4.14... Drain diffusion region 5.15...・
... Gate insulating film 6.16 ... Gate electrode 7.17 ... Interlayer insulating film 8.19 ... Electrode wiring layer 18 ... Interlayer metal Applicant: Suwa Seikosha Co., Ltd. Figure 1
Claims (2)
いわゆる薄膜半導体装置を製作するに際し、絶縁膜を介
してコンタクト・ホールを通して電極配線との接続を行
なうコンタクト部に於て、半導体層と電極との間に銅、
クロム、チタン等の金属層を形成することを特徴とする
薄膜半導体装置。(1) Using a semiconductor film formed on an insulating substrate,
When manufacturing so-called thin film semiconductor devices, copper, copper,
A thin film semiconductor device characterized by forming a metal layer of chromium, titanium, etc.
を酸化錫または酸化錫と酸化インジウムの混合物または
酸化インジウムとなすことを特徴とする特許請求範囲第
１項記載の薄膜半導体装置。(2) The thin film semiconductor device according to claim 1, wherein the semiconductor film is a silicon semiconductor film, and the electrode wiring material is tin oxide, a mixture of tin oxide and indium oxide, or indium oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14135382A JPS5931041A (en) | 1982-08-13 | 1982-08-13 | thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14135382A JPS5931041A (en) | 1982-08-13 | 1982-08-13 | thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5931041A true JPS5931041A (en) | 1984-02-18 |
Family
ID=15289992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14135382A Pending JPS5931041A (en) | 1982-08-13 | 1982-08-13 | thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931041A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61222180A (en) * | 1984-12-28 | 1986-10-02 | ソヒオ コマ−シヤル デイベロツプメント コムパニ− | Multilayer ohmic contact for p-type semiconductor and makingthereof |
| JPS63152010A (en) * | 1986-12-16 | 1988-06-24 | Hitachi Ltd | Production of thin film magnetic head |
| KR100332118B1 (en) * | 1999-06-29 | 2002-04-10 | 박종섭 | Method of forming a metal wiring in a semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5258491A (en) * | 1975-11-10 | 1977-05-13 | Hitachi Ltd | Semiconductor device |
| JPS53121489A (en) * | 1977-03-31 | 1978-10-23 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-08-13 JP JP14135382A patent/JPS5931041A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5258491A (en) * | 1975-11-10 | 1977-05-13 | Hitachi Ltd | Semiconductor device |
| JPS53121489A (en) * | 1977-03-31 | 1978-10-23 | Toshiba Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61222180A (en) * | 1984-12-28 | 1986-10-02 | ソヒオ コマ−シヤル デイベロツプメント コムパニ− | Multilayer ohmic contact for p-type semiconductor and makingthereof |
| JPS63152010A (en) * | 1986-12-16 | 1988-06-24 | Hitachi Ltd | Production of thin film magnetic head |
| KR100332118B1 (en) * | 1999-06-29 | 2002-04-10 | 박종섭 | Method of forming a metal wiring in a semiconductor device |
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