JPS5930146A - Microprogram debugging device - Google Patents

Abstract

PURPOSE:To form a titled device by only a gate controlling circuit which is debugged easily, by inserting forcibly an optional micro-instruction and executing it, when testing a hardware. CONSTITUTION:A device to be debugged 10 is in a usual executing state, when both an A-INH signal of a control line 22 and a D-INH signal of a control line 23, which are emitted from a microprogram execution controlling circuit 21 in a debugging device 20 are in an ineffective state. In this case, a micro-sequencer 11 in the device to be debugged 10 executes access to both a storage device 12 of the device to be debugged 10 and a debugging device 20 through a micro-address bus 13, and a micro-instruction to be executed actually is determined by a state of an ROM-INH signal of a control line 25 for switching a selector 14.

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to a microprogram debugging device that can efficiently perform microprogram debugging and hardware testing of a processor that employs a microprogram control method. (Background Art) Conventionally, in microprogram debugging and hardware testing of a processor that employs a microprogram control method, (1) a read-only storage device (hereinafter referred to as It) of a processor to be debugged (hereinafter referred to as debugged device); (referred to as OM)
(11) In addition to the ROM of the device being debugged, a storage device that can be rewritten many times (e.g., random access memory, registers) is provided. Prepare it in the device to be debugged, debug,
and during hardware testing, the latter storage device is used.
There was a way to run it. However, in method (1), if the storage device is +? , O.M.
Therefore, it is easy to deal with the modification of microprograms. Further, in order to realize the method (11), there is a drawback that a complicated control circuit such as clock control is required. (Problem of the Invention) An object of the present invention is to provide a debugging device that facilitates debugging of microprograms and can forcibly insert and execute microinstructions at will during hardware testing. A debugging device for testing a debugged device in which a read instruction decoder decodes and executes a read program in accordance with addressing of a microsequencer, the debugging device having a rewritable storage device and a microprogram execution control circuit; The microprogram execution control circuit outputs a control signal for inhibiting address updating of the microcontroller of the debugged device, and switches between the R&)M output of the debugged device and the output of the storage device of the debugged device to the instruction decoder. A microprogram debugging device such as an OJ function has a control signal for outputting a control signal for debugging and a control signal for putting the debugged device into a no-operation state. Switching between the outputs of It and OM of the device to be debugged and the output of the storage device of the debugging device is performed without clock control of the device to be debugged. (Structure and operation of the invention) FIG. 1 shows an embodiment of the invention. 1() is the device to be debugged, Moon is the microsequencer of device 1o, ]2 is It01VI of device 10, J3 is the microsequencer [1
micro address bus which is the output line of , 14 is the selector, I5 is f? , 0MI2 output lines, ]6 is a microinstruction register, and 17 is a microinstruction decoder. Further, 20 is a depacking device, and 21 is a microprogram execution control circuit. 22 is an address inhibit control line that is also released from the microprogram execution control circuit 21, and the main line #j control signal (hereinafter A-
(referred to as INI-1) is in a valid state, updating of sequencer 1■ is prohibited. B is the data input control line from which the microprogram execution control circuit 2 is also released.
When the main line control signal (hereinafter referred to as D-INH) is in a valid state, it gates the microinstruction decoder 17 and N
Put it in operation state. 2.1 is a storage device of the device 2o that can be refrosted many times. 25 is a control line that switches the selector I4, and when the main line control signal (hereinafter referred to as 101'vl -I N I 1 river and set) is in the valid state, the micro data bus 2 ('
Select 1. 2 (if 5[i can be rewritten 401 times)
: Micro data bus, 2, which is the output line of storage device 2/1.
7 is a preset address for 28 manual operation, and 28 is a selector. . The operation of the embodiment will be described in detail below with reference to FIGS. 1 and 2. First, a normal control state will be explained. When the debugged device 6 is in the normal execution state, the microprogram execution control circuit 21 in the debug device 20 releases the A-iNH signal of C) released control +<= 22 and the control line 2:3.
])-IN11 signals are both in an invalid state. At this time, the microsequencer 1 in the debugged device 10
1 accesses both the storage device 12 of the debugged device 10 and the debug device 24 via the micro address bus 13, and the micro instruction actually executed is IjOM-iNLJ on the control line 5 that switches the selector 14. Determined by the state of the signal. 11. OM-i N1-
If No. 1 is in an invalid state, the output line 15 of the storage device 12 of the device to be debugged 10 is selected, and if it is in a valid state, the output line 26 of the storage device 24 of the debugging device 20 is selected, and the microinstruction register is ] There are 60 inputs. Figure 2 shows A-INH,I) -INH,I(,OM
-INH is a diagram showing the relationship between each control signal and the switching state of an execution microinstruction, the A-INI-I signal,
When the D-INH signal and the tOM-IN1-1 signal are all in an invalid state, it is a normal state, and the memory device 120 of the debugged device 10 operates according to microinstructions (case A in FIG. 2). Next, set the processor state of the debugged device 10 to N. The case of setting it to the operation state will be explained. In this case, by enabling both the A-IN11 signal on the control line 22 and the I)4NI-1 signal on the control line 23,
Set the processor status of the debugged device 10 to No oper.
This becomes possible by setting it to the ation state. This means that the A-INI-1 of the control &122 becomes valid, which prohibits updating of the microsequencer 11, and the I)4-Nil signal of the control line becomes valid. This allows the microinstruction decoder 17 to
．． )-INliNll signal 1j-like No opera
This is for gate control to the tion command state. As a result, even though the clock is not being supplied to the debugged device 10, the two processors appear to be in a stopped state (
It becomes possible to create a state in which the state enters the No operation state) and continues to maintain the previous state (Second
Figure; 1. state). Next, a case in which the debugged device 10 is operated using the storage device 24 on the debugging device 20 side will be described. In this case, the R, OM-i Nll signals on the control line 25 are in a valid state, and the A4NI- (signal and control line 23
1) - This is possible by setting the INIINil signal state. By setting the A-INI-1 signal on the control line 22 to an invalid state, the sequencer 11 performs normal operation, and the memory device j2 of the debugged device 10 and the memory device 2 of the debugging device 20 are connected via the micro address bus 13.
・1 is accessed and the storage device I of the debugged device 10
The output of the storage device 24 of the debug device 20 is released onto the micro data bus 26. Among these released micro-instructions, the micro-instructions on the micro data bus 26 are sent to the selector 1 by the ILOM-I NI4 signal on the control line 25.
4 and becomes an input to the microinstruction register I6. The output of the microinstruction register 16 is connected to the control line 2.
: Since the D-INIINil signal state is in the state, the microinstruction decoder does not go into the No operation state, and by operating with a normal microinstruction decoder, the microinstruction device 2 and 10 of the memory device on the debugging device side can be read. is executed (FIG. 2: state 13). Next, a case will be described in which a microinstruction and a debugging device 2o are forcibly inserted and a hardware test is executed. In this case, the A4N11 signal on the control line 22 and the 1(
, OM-I This becomes possible by invalidating the D-1N ■■ signal on the control line 23 when the Nil signal is in the valid state. Since the A-INHNN signal is enabled, updating of the microsequencer II is prohibited, and the precent address 27 preset on the debugging device 20 side is A-INHNN.
It is selected via the selector path by the I Nll signal 22 and accesses the memory device 2/1 on the debug device side. Also, A1. a microinstruction on the microdata bus 15,
The microinstructions on the microdata bus 26 released from storage 2=1 of the debug device 20 are ++, 0.
Since the ~+ -, 1, and Nll signals are in the valid state, the micro data bus 2G is selected via the selector 1/1. 2; 3 J,) 41' Since the JII signal is in an invalid state, as a result, the microinstruction in the storage device 2/1 of the debug device 20 accessed at the preset address 27 is executed ( Figure 2;
condition C). Next, the single step operation of the microinstruction will be explained. In this case, the control lines 22 A, -
By changing the INN signal and the JJ4NIi signal on the control line 23 from the valid state to the invalid state by one clock width.

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3. It is assumed that the micro address bus 13 is accessing the storage device 12 of the debugged device 10 and the storage device 2=1 of the debugging device 20 via the selector 28. At this time, R, OM −I of the control line part
Depending on the state of the NN signal, either the micro data bus 15 or the micro data bus 26 is selected via the selector 14, and becomes an input to the micro instruction register 16, where it is stored. With the output of the microinstruction register 16 being the input to the microinstruction decoder 17,
By disabling the D-4NII signal on the control line 23, the microinstruction decoder 7 is enabled and a single step operation is performed. Also, the A-I Nil signal of the control @22 is connected to the I)-I of the control line 23.
By disabling the NIINil signal, the address of the microsequencer 11 is also updated (in the case of 13 or 1 in FIG. 2). The above operation description includes (1) execution in the storage device of the device being debugged, (ii) generation of a No operation state, (lit) replacing the storage device of the device being debugged with the storage device of the debugging device, and (Ov) We have explained how to execute (V) single-step operations in which microinstructions are forcibly inserted from the debugging device side, but these operations do not directly control the clock on the debugged device side (the clock is in the supplied state). ), realized by a simple gate circuit and control lines 22, 2.3, 25
+. ing. (Effects of the Invention) By implementing the present invention, there is an advantage that the matters enumerated below can be realized only by a simple G1□a control circuit without being directly applied to the clock division. (1) In addition to the read-only storage device on the debugged device side, a storage device on the debugging device side that can be changed over and over again can be used.Switching between the two storage devices can be performed using It, OM-
(2) If it is necessary to change the operating state of the device to be debugged to a stop state (No operating state) during debugging, the present invention A-
This can be easily realized using two control signals: 1NII signal and 1)-iNII signal. (3) A single step operation can be easily realized by invalidating the A, -1NII signal and the D-1,NH multiplied signal by one clock width. (4) Forced microinstruction insertion from the debug device side can be easily realized. (5) Timing problems such as delays in switching between storage devices on the debugged device side and the debugging device side, or set amplifier time can be easily compensated for by the I) 4NI+ signal, which requires special hardware. No need.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a debug system according to the present invention,
Fig. 2 is an operational diagram of the device shown in Fig. 1 -620...
...Debug device 21...Microprogram execution control circuit 22...Address inhibit control line 23...Data inhibit control line 2・1・
......Storage unit that can be rewritten many times...
...Rom-in-hipit control line 26...
...Micro data bus 27...Preset address path...Selector

Claims (1)

[Claims] In a debugging device for testing a device to be debugged, the program written in a 10fvl is decoded and executed by a read instruction decoder according to address specification of a microsequencer, and the debugging device includes a rewritable storage device and a microprogram execution control circuit. The microprogram execution control circuit outputs a control signal that inhibits updating of the address of the microsequencer of the debugged device, and outputs power to the instruction decoder by switching between the output of the ROM of the debugged device and the output of the storage device of the debugged device. A microprogram debugging device is characterized in that it is capable of outputting a control signal for debugging and a control signal for putting a debugged device into a no-operation state.