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JPS5929454B2 - Speed control device with balance notch calculation circuit - Google Patents

Speed control device with balance notch calculation circuit

Info

Publication number
JPS5929454B2
JPS5929454B2 JP51071749A JP7174976A JPS5929454B2 JP S5929454 B2 JPS5929454 B2 JP S5929454B2 JP 51071749 A JP51071749 A JP 51071749A JP 7174976 A JP7174976 A JP 7174976A JP S5929454 B2 JPS5929454 B2 JP S5929454B2
Authority
JP
Japan
Prior art keywords
speed
calculation circuit
balance
circuit
acceleration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51071749A
Other languages
Japanese (ja)
Other versions
JPS52153508A (en
Inventor
健司 森原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP51071749A priority Critical patent/JPS5929454B2/en
Publication of JPS52153508A publication Critical patent/JPS52153508A/en
Publication of JPS5929454B2 publication Critical patent/JPS5929454B2/en
Expired legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02TCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00Road transport of goods or passengers
    • Y02T10/60Other road transportation technologies with climate change mitigation effect
    • Y02T10/72Electric energy management in electromobility

Landscapes

  • Braking Systems And Boosters (AREA)
  • Electric Propulsion And Braking For Vehicles (AREA)
  • Control Of Velocity Or Acceleration (AREA)

Description

【発明の詳細な説明】 本発明は、各速度又は、各段の速度に於て、定速運転に
保持する定速制御装置を有する速度制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed control device having a constant speed control device that maintains constant speed operation at each speed or speed of each stage.

この種の速度制御装置は例えば、ハンプ(坂阜)操作場
で用いる押上機関車に備わつている。
This type of speed control device is installed, for example, in push-up locomotives used at hump operations.

この押上機関車を運転する場合、貨物列車を目的線別に
第1図に示す様なハンプヤードで散転する時、分解列車
長、ポイント切換のタイミング等により第2図に示す様
に刻々、指令速度5が変化する。なお、第1図に於て、
1は押上機関車、2は貨車、3は分離されて自由走行中
の貨車、4はハンプ頂上を示す。又6は実車速を示す。
散転能率上その指令速度5にすはやく追従させるために
、目標速度まで加速時に可能な限りの最高ノッチ(最大
出力)で加速し、又減速時には最低ノッチ(最小出力)
で減速させる為一定時限でノッチの上げ下げを行う制御
方式に於いて、つまり加速時はノッチアップ、減速時は
ノッチダウンを一定時限で行う制御方式において、目標
速度に達した時車速がオーバーシュート及びアンタンエ
ートしない様列車重量、押上げトルク、勾配等による走
行抵抗、指令速度等より決められる定速走行バランスノ
ッチを演算し、そのノッチに強制的に進段戻し制御を行
なう。
When operating this push-up locomotive, when the freight train is scattered around the hump yard for each destination line as shown in Figure 1, the command speed is changed every moment as shown in Figure 2 depending on the length of the disassembled train, the timing of point switching, etc. 5 changes. In addition, in Figure 1,
1 is a pushing locomotive, 2 is a freight car, 3 is a separated freight car running freely, and 4 is the top of a hump. Further, 6 indicates the actual vehicle speed.
In order to quickly follow the command speed 5 in terms of dispersion efficiency, when accelerating to the target speed, it accelerates at the highest possible notch (maximum output), and when decelerating, it accelerates at the lowest notch (minimum output).
In a control method that raises and lowers the notch in a fixed time period to decelerate, that is, in a control method that increases the notch during acceleration and down the notch during deceleration, when the target speed is reached, the vehicle speed overshoots and A constant speed running balance notch determined from the train weight, push-up torque, running resistance due to gradient, etc., command speed, etc. is calculated to prevent the train from untanging, and the advance control is forcibly returned to that notch.

ちなみに、ハンプヤードの定速度制御範囲は通常1〜5
Km/ れと超低速域の制御であり、押上げ荷重0〜1
000ton余りまでの全範囲に於て、±O、2Km/
れ程度の速度追従精度を要求されるのが一般である。
この時、バランスノッチを演算する方式として車速の加
減速度を検知し、その値によりバランスノッチを演算す
る事が一般的に考えられる。それは、次式により表わさ
れる。引張力F=W・α+ RW:列車重量 α:加(減)速度 R:走行抵抗 これにおいて、車速の加減速度を検出する一方式のブロ
ック図を第3図に示す。
By the way, the constant speed control range of hump yards is usually 1 to 5.
Km/ This is control in the ultra-low speed range, and the push-up load is 0 to 1.
In the entire range up to over 1,000 tons, ±O, 2Km/
Generally, speed tracking accuracy of this level is required.
At this time, it is generally considered that as a method of calculating the balance notch, the acceleration/deceleration of the vehicle speed is detected and the balance notch is calculated based on the detected acceleration/deceleration. It is expressed by the following equation. Tensile force F=W·α+ RW: Train weight α: Acceleration (deceleration) speed R: Running resistance In this case, a block diagram of one method for detecting acceleration/deceleration of vehicle speed is shown in FIG.

車輛端なιル減速装置に取付けられた速度発電機□より
車速に比例したパルス周波数が出力され、分配回路8へ
与えられる。この分配回路8は、ある一定時限Tごとに
交互に速度発電機Tからのパルス周波数を可逆カウンタ
9の(ト)又は(ト)入力端へ出力する。可逆カウンタ
90(−F)入力端に入力された時、可逆カウンタ9は
加算カウントし、(ト)入力端に入力された時は、先に
加算された値よりある一定時限T秒間だけ入力されたパ
ルス数を減算する。減算し終えた時の可逆カウンタ9に
残つた値がT秒間に変化したパルス周波数(Δf)でそ
れを減速換算し、定時限Tで割つたものがその時の加減
速度α、βとされる。α、β:加減速度 K:換算定数 Δf:パルス周波数偏差 T:パルス周波数カウント時間 以上の様に加減速度α、βを求めるには、ある時間(一
般に1〜10秒間)が必要である。
A pulse frequency proportional to the vehicle speed is outputted from a speed generator □ attached to a speed reduction device at the end of the vehicle, and is applied to the distribution circuit 8. This distribution circuit 8 alternately outputs the pulse frequency from the speed generator T to the (g) or (g) input terminal of the reversible counter 9 at certain fixed time intervals T. When input to the reversible counter 90 (-F) input terminal, the reversible counter 9 performs an addition count, and when input to the (G) input terminal, the value is input for a certain period of time T seconds from the previously added value. subtract the number of pulses. The value remaining in the reversible counter 9 when the subtraction is completed is converted into deceleration by the pulse frequency (Δf) that changed over T seconds, and the value divided by the fixed time limit T is used as the acceleration/deceleration α and β at that time. α, β: Acceleration/Deceleration K: Conversion Constant Δf: Pulse Frequency Deviation T: Pulse Frequency Count Time A certain amount of time (generally 1 to 10 seconds) is required to obtain the acceleration/deceleration rates α and β as above.

この為定速域に進入した場合もバランスノツチ演算回路
を働かせ強制進段・戻しを行うと、速度の波うち周期が
加減速度の演算時間に較べ長くない為(加速時間t〉2
T〜3Tの時間が必要)、真の加減速度が得られずかえ
つて誤動作の原因となり、速度追従を害する結果にもな
る。そのため、バランスノツチ演算回路は、一旦定速域
に第4図に示す様にA点で突入した場合に凍結するのが
普通である。尚、A点は、動力(モーター、エンジン等
)の追従遅れ、許容追従速度より決められるものであつ
て、必らずしも指令速度とは一致しない。然して、上記
のように加減速度を検知して速度変化時、目標速度進入
時のみバランスノツチを演算させ、定速域に入つた条件
ではバランスノツチ演算回路を凍結させる方式の速度制
御装置においては、第5図に示すように、加速時におけ
る車輪の空転等により、一瞬、実速度以上に見かけ上車
速が上昇して定速域に突入したときに、これを定速域に
入つたと判断してバランスノツチ演算回路が凍結される
場合がある。そして、このように一定時限でしかノツチ
のアツプおよびダウンの動作がない従来の速度制御装置
は、本来定速域に突入しているべき時間経過後において
もバランスノツチ演算回路が凍結され、車速が空転時に
おける実速度のままとなつていることがあり、また加速
時のオーバーシユート、減速時のアンダーシユート量も
大きくなる傾向にあるため、目標速度に到達してその付
近に安定するまで(バランスノツチになるまで)非常に
多くの時間を要し、バンプ運転の様に目標速度が頻繁に
変化するシステムにおいては問題が大きく、機能を満足
しない欠点があつた。本発明は、この様な従来の欠点を
改善することを目的としてなされたものである。
For this reason, even when entering the constant speed range, if the balance notch calculation circuit is activated to perform a forced advance/return, the wave period of the speed is not long compared to the calculation time of acceleration/deceleration (acceleration time t>2
(requires a time of T to 3T), true acceleration/deceleration cannot be obtained, which may even cause malfunctions and impair speed tracking. Therefore, the balance notch calculation circuit normally freezes once it enters the constant speed range at point A as shown in FIG. Note that the A point is determined based on the follow-up delay of the motive power (motor, engine, etc.) and the allowable follow-up speed, and does not necessarily match the command speed. However, in a speed control device that detects acceleration/deceleration as described above, calculates the balance notch only when the speed changes or approaches the target speed, and freezes the balance notch calculation circuit when the speed enters the constant speed range. As shown in Figure 5, when the vehicle speed momentarily rises above the actual speed due to wheels spinning during acceleration and enters the constant speed range, this is judged as entering the constant speed range. The balance notch calculation circuit may be frozen. In conventional speed control devices, where the notch is raised and lowered only within a certain period of time, the balance notch calculation circuit is frozen even after the time when the vehicle should have entered the constant speed range, causing the vehicle speed to drop. The actual speed may remain the same as when idling, and the amount of overshoot during acceleration and undershoot during deceleration tends to increase, so until the target speed is reached and stabilized around it. It takes a very long time (to reach the balance notch), which is a big problem in systems where the target speed changes frequently, such as in bump driving, and it has the drawback of not being fully functional. The present invention has been made with the aim of improving such conventional drawbacks.

本発明においては、空転等により一時的に見かけの速度
が上昇して定速域に至りバランスノツチ演算回路が凍結
された場合でも、その後の測定実速度と指令速度の比較
により空転を検出して、この検出により自動的にバラン
スノツチ演算回路の凍結を解除する構成とする。このよ
うにすれば、空転は一時的なものであるので、空転が無
くなつた時点でバランスノツチ演算回路は定常の演算を
閉始し、所要の動作を完遂する。
In the present invention, even if the apparent speed temporarily increases due to idling, reaches a constant speed range, and the balance notch calculation circuit is frozen, idling is detected by comparing the measured actual speed with the commanded speed. This detection automatically unfreezes the balance notch calculation circuit. In this way, since the slipping is temporary, the balance notch calculation circuit starts the steady calculation when the slipping stops and completes the required operation.

第6図は、本発明の一実施例を示すプロツク図である。FIG. 6 is a block diagram showing one embodiment of the present invention.

図中12は、指令速度パターン発生回路、7は車両速度
を検出する速度発電機、13は指令速度p(第4図の5
)と車速Va(第4図の6)を加算する加算器で、指令
速度5に対する実速度6の速度偏差ΔVを演算する。1
4は比較回路であり、第5図に示す目標速度Vpと車速
Vaとの速度偏差ΔVを定速域到達設定値ΔV2および
定速域における最大限の速度偏差Δ1比較し、その大小
によつてセツト、りセツト指令を定速域突入信号発生回
路15へ出力するようになつている。
In the figure, 12 is a command speed pattern generation circuit, 7 is a speed generator that detects the vehicle speed, and 13 is a command speed p (5 in Figure 4).
) and the vehicle speed Va (6 in FIG. 4), the speed deviation ΔV of the actual speed 6 with respect to the commanded speed 5 is calculated. 1
4 is a comparison circuit that compares the speed deviation ΔV between the target speed Vp and the vehicle speed Va shown in FIG. Set and reset commands are output to the constant speed range entry signal generation circuit 15.

つまりp−Va〉ΔV1でりセツト指令をVp−Va〈
ΔV2でセツト指令を定速域突入信号発生回路15へ出
力する回路である。
In other words, p-Va>ΔV1 sets the set command to Vp-Va<
This circuit outputs a set command to the constant speed region entry signal generation circuit 15 at ΔV2.

16は目標速度進入時すなわち速度変化時に加減速度演
算回路17が演算する加減速度により、バランスノツチ
を演算するバランスノツチ演算回路であり、上記セツト
指令、すなわち上記定速域突入信号発生回路15からの
定速域突入信号を受けると、その時点の算出値に凍結さ
れ、りセツト信号を受けると上記凍結が解除されるよう
になつている。
Reference numeral 16 denotes a balance notch calculation circuit that calculates a balance notch based on the acceleration/deceleration calculated by the acceleration/deceleration calculation circuit 17 when approaching the target speed, that is, when the speed changes. When a constant speed region entry signal is received, the calculated value at that time is frozen, and when a reset signal is received, the above-mentioned freezing is released.

この演算結果16により、加速時何ノツチ減算した所に
、又は、減速時何ノツチ加算した所にバランスノツチ(
バランストルク)があるかが燃料制御回路、及びブレー
キ回路に指令される。以上の構成により、第5図に示す
様な起動時及び高位の速度指令による加速時に、第4図
又は第5図に示す定速制御域突入点、つまり、A点に達
した事を比較回路14で判定し、定速域突入信号発生回
路15へセツト信号(トリカー信号)を送りバランスノ
ツチ演算を行うが、第5図に示す様に空転及び誤動作に
よつて瞬間的にA点を超えたかどうかを同じく比較回路
14で判定する。つまり、Vp−Va〉ΔV1の領域に
その后復帰すれば、それは空転ないし一時的誤動作と判
断し、定速域突入信号発生回路15の凍結回路をりセツ
トする為のりセツト信号を比較回路14より発生させる
。これにより真に定速域に達した時、バランスノツチ演
算を行い目標速度にオーバーシユートする事なくすばや
く収れんさせる。又、定速運転時低位の指令速度が入力
された場合には、減速させる為に必要によりブレーキを
掛けるが、その時、滑走ないし一時的誤動作によつて瞬
間的に定速域に突人したとしても、上記加速時と同様、
第6図の回路により凍結回路のセツト/りセツトを行う
ことにより、真に目標速度域に達した時にバランスノツ
チ制御が行われ、大きなアンダーシユートをする事なく
短時間のうちに目標速度に収れんする。以上述べたよう
に本発明装置によれば、測定時速度と指令速度との速度
偏差△Vを検出してこの検出値と、予め設定された各偏
差値△Vl,△V2とを比較し、この比較値に基づいて
バランスノツチ演算回路の凍結および凍結解除を行なわ
せるようにしたことにより、空転を瞬時にかつ連続的に
検出することが可能となつてバンプアートに於ける散転
能率も空転滑走ないし一時的誤動作に影響されず、定速
追従精度が指令速度変化時も定常時と同じ程度に制御出
来る為大巾に向上すると共に、定常時の追従精度を持つ
て散転時隔が決められる為にシステム簡素化が出来る。
Based on this calculation result 16, balance notches (
A command is sent to the fuel control circuit and brake circuit to determine whether there is a balance torque (balance torque). With the above configuration, the comparison circuit detects when the constant speed control region entry point shown in FIG. 4 or FIG. 14, a set signal (triker signal) is sent to the constant speed range entry signal generation circuit 15 to calculate the balance notch, but as shown in Fig. 5, the point A is momentarily exceeded due to slipping or malfunction. The comparator circuit 14 similarly determines whether or not it is the same. In other words, if the motor returns to the region of Vp-Va>ΔV1, it is determined that it is idling or a temporary malfunction, and a reset signal is sent from the comparator circuit 14 to reset the freeze circuit of the constant speed region entry signal generation circuit 15. generate. As a result, when the constant speed range is truly reached, balance notch calculation is performed to quickly converge without overshooting to the target speed. Also, if a low command speed is input during constant speed operation, the brakes will be applied as necessary to decelerate, but at that time, it is assumed that the vehicle suddenly enters the constant speed range due to skidding or temporary malfunction. Similarly to the above acceleration,
By setting/resetting the freezing circuit using the circuit shown in Figure 6, balance notch control is performed when the target speed range is truly reached, and the target speed is reached in a short time without significant undershoot. It converges. As described above, according to the device of the present invention, the speed deviation △V between the speed at the time of measurement and the command speed is detected, and this detected value is compared with each preset deviation value △Vl, △V2, By freezing and unfreezing the balance notch calculation circuit based on this comparison value, it is possible to detect slippage instantly and continuously, and the dispersion efficiency in bump art can also be improved. It is not affected by skids or temporary malfunctions, and the constant speed tracking accuracy can be controlled to the same degree as in the steady state even when the command speed changes, which greatly improves the accuracy. This allows the system to be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はバンプアート押上機関車ならびにそれによつて
散転される貨車を示す概略説明図、第2図はその押上機
関車の速度制御特性を示すグラフである。 第3図は、従来の加減速度測定装置の構成を示すプロツ
ク図である。第4図および第5図は、押上機関車の所定
速度への加速特性を示すグラフである。第6図は、本発
明装置の構成を示すプロツク図である。なお、図中同一
符号は同一又は相当部材を示す。1・・・・・・押上機
関車、2,3・・・・・・貨車、4・・・・・・バンプ
頂上、5・・・・・・指令速度、6・・・・・・実速度
、7・・・・・・速度発電機、8・・・・・・分配回路
、9・・・・・・可逆カウンタ、10・・・・・・デコ
ーダ、12・・・・・・指令速度パターン発生回路、1
3・・・・・・加算器、14・・・・・・比較回路、1
5・・・・・・定速域突入信号発生回路、16・・・・
・・バランスノツチ演算回路、17・・・・・・加減速
度演算回路。
FIG. 1 is a schematic explanatory diagram showing a bump art pushing locomotive and freight cars scattered by it, and FIG. 2 is a graph showing the speed control characteristics of the pushing locomotive. FIG. 3 is a block diagram showing the configuration of a conventional acceleration/deceleration measuring device. FIGS. 4 and 5 are graphs showing the acceleration characteristics of the pushing locomotive to a predetermined speed. FIG. 6 is a block diagram showing the configuration of the apparatus of the present invention. Note that the same reference numerals in the figures indicate the same or equivalent members. 1...Pushing locomotive, 2,3...Freight car, 4...Bump top, 5...Command speed, 6...Actual Speed, 7... Speed generator, 8... Distribution circuit, 9... Reversible counter, 10... Decoder, 12... Command Speed pattern generation circuit, 1
3... Adder, 14... Comparison circuit, 1
5... Constant speed region entry signal generation circuit, 16...
...Balance notch calculation circuit, 17... Acceleration/deceleration calculation circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 車輛速度を検出する速度検出器、この速度検出器の
検出出力をもとに加減速度を算出する加減速度演算回路
、指令速度Vpと上記検出器の検出速度Vaとの速度偏
差△Vを算出する加算器、前記速度偏差△Vを定速域到
達設定値△V_2及び定速域における最大限の速度偏差
△V_1と比較し、速度偏差ΔVが上記定速域到達設定
値△V_2以内のときセット信号を出力し、上記速度偏
差△V_1以上のときリセット信号を出力する比較回路
、および、上記セット信号を受けて定速域突入信号を発
生しバランスノッチ演算回路をその時点の算出値に凍結
し、上記リセット信号を受けてバランスノッチ演算回路
の凍結を解除する定速域突入信号発生回路を備えるバラ
ンスノッチ演算回路を有する速度制御装置。
1. A speed detector that detects the vehicle speed, an acceleration/deceleration calculation circuit that calculates acceleration/deceleration based on the detection output of this speed detector, and a speed deviation △V between the command speed Vp and the detected speed Va of the detector. The adder compares the speed deviation △V with the constant speed range reaching set value △V_2 and the maximum speed deviation △V_1 in the constant speed range, and when the speed deviation ΔV is within the above constant speed range reaching set value △V_2. A comparison circuit that outputs a set signal and outputs a reset signal when the speed deviation is △V_1 or more, and a balance notch calculation circuit that generates a constant speed region entry signal upon receiving the set signal and freezes the balance notch calculation circuit to the calculated value at that point. A speed control device having a balance notch calculation circuit, further comprising a constant speed region entry signal generation circuit that receives the reset signal and unfreezes the balance notch calculation circuit.
JP51071749A 1976-06-17 1976-06-17 Speed control device with balance notch calculation circuit Expired JPS5929454B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51071749A JPS5929454B2 (en) 1976-06-17 1976-06-17 Speed control device with balance notch calculation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51071749A JPS5929454B2 (en) 1976-06-17 1976-06-17 Speed control device with balance notch calculation circuit

Publications (2)

Publication Number Publication Date
JPS52153508A JPS52153508A (en) 1977-12-20
JPS5929454B2 true JPS5929454B2 (en) 1984-07-20

Family

ID=13469479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51071749A Expired JPS5929454B2 (en) 1976-06-17 1976-06-17 Speed control device with balance notch calculation circuit

Country Status (1)

Country Link
JP (1) JPS5929454B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197519A (en) * 1982-05-14 1983-11-17 Agency Of Ind Science & Technol Control system of servo system using friction transmission mechanism
US4904027A (en) * 1988-10-03 1990-02-27 American Standard Inc. Digital air brake control system

Also Published As

Publication number Publication date
JPS52153508A (en) 1977-12-20

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