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JPS5929427A - Production device system of semiconductor device - Google Patents

Production device system of semiconductor device

Info

Publication number
JPS5929427A
JPS5929427A JP57140253A JP14025382A JPS5929427A JP S5929427 A JPS5929427 A JP S5929427A JP 57140253 A JP57140253 A JP 57140253A JP 14025382 A JP14025382 A JP 14025382A JP S5929427 A JPS5929427 A JP S5929427A
Authority
JP
Japan
Prior art keywords
manufacturing
inspection
manufacturing equipment
proceed
equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57140253A
Other languages
Japanese (ja)
Other versions
JPH027178B2 (en
Inventor
Mototaka Kamoshita
鴨志田 元孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57140253A priority Critical patent/JPS5929427A/en
Priority to US06/506,677 priority patent/US4571685A/en
Priority to GB08317126A priority patent/GB2126374B/en
Publication of JPS5929427A publication Critical patent/JPS5929427A/en
Publication of JPH027178B2 publication Critical patent/JPH027178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P72/0471
    • H10P72/0612
    • H10P74/00
    • H10P74/23

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To automate sections as connectors among processes, and to change one part of the production line of the semiconductor device into a continuous production line by introducing an inspection device with an automatic inspection mechanism and giving instructions as treatment compensating a displacement section from a rated value. CONSTITUTION:A resist film 52 is applied onto a polycrystalline silicon film 51 formed through a process PN-1, thermally shrunk slightly for approximately 10min at approximately 50 deg.C, positioned and exposed, and developed by using a developer of the resist film 52, and external appearance is inspected and the whole is thermally shrunk for 1hr at approximately 200 deg.C when there is no abnormality. The polycrystalline silicon film 51 is etched in plasma by using a gas of a CF4 group, and the resist film 52 as a mask for etching is exfoliated and the film is advanced to an inspection system CN. When the processing width L of the polycrystalline silicon 51 is displaced at that time, the result is transmitted over a process PN+1 by the inspection system CN, heat is diffused in the lateral direction through a process as heat treatment by a nitrogen air- current after ion implantation, and a heat treatment furnace system is adjusted automatically so that effective channel length Leff is made the same as polycrystalline silicon gate electrode width L is used as a central value.

Description

【発明の詳細な説明】 本発明は半導体装置の生産装置システム、市に、半導体
装置を自動的に一貫生産する生産装置システムに関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a production equipment system for semiconductor devices, and a production equipment system for automatically and integratedly producing semiconductor devices in a city.

一般に半導体装置は、半導体の単結晶ウエーノ・を材料
とし、エピタキシアル成長、i、2化、レジスト力ロエ
(レジスト塗布、トぷ光、Sl、イチ:、エツチング)
、不純物ドープ(熱拡11シ又はイラン注入)気オii
 J2’i長(多結晶シリコン、♀2化姓素膜、殴化硅
緊膜など)、I工極配紳材ネ1刊着等々の一連のプロセ
スを約返し製造される。このようなそれぞれのプロセス
は互に関連があり、全体の流れの中で最逸東件が決する
Semiconductor devices are generally made from semiconductor single crystal wafer, and are manufactured using epitaxial growth, i, 2, resist coating, top light, SL, etching.
, impurity doping (thermal expansion or iranian injection) gas II
It is manufactured by repeating a series of processes such as J2'I length (polycrystalline silicon, ♀2 chemical film, hardened silicon film, etc.), I-engineering material, etc. Each of these processes is interconnected, and the best results are determined within the overall flow.

従来このプロセスの内でのfl+lI (Filは自動
化が進んで来ておシ、又、/?:1TiNデーj″のV
7積による品質管理技術も既に高度なものとなっている
。然し乍ら、プjjセス間、工程I)i」のつなぎの部
分は依然としで人手又ンj、単なるrノポットあるいt
;L ’;=4’庁I・■−5によυウェーハの受り渉
〕しかなされている。その/こめ前工秒の揺らぎの影響
−と後工眉で補正しようとJると、人手による個々のプ
ロセス内でのft1i制御に依らざるを得す、塵埃発生
源の「人」をト炸9;フィン内から省くことが囚シlで
あっプこ。
Conventionally, in this process, fl+lI (Fil has become increasingly automated, and /?:1TiNdayj'' V
The quality control technology using 7 products has already become sophisticated. However, the connecting parts between the processes and the process I) still need to be done manually, or by mere pots.
;L';=4'Only υ wafers are received and received by Office I・■-5]. If we try to compensate for the influence of fluctuations in the pre-processing time and post-processing, we will have to rely on manual control within each individual process, and the "human" source of dust will be exposed. 9; It is difficult to remove it from inside the fin.

本発明は工程間のつなぎとなる部分を自動化し半導体装
置の製造ラインの少なくとも一部分を一貫した生産ライ
ンにして、該半導体装置を製造する技術を提供するとと
を目的とする。
An object of the present invention is to provide a technology for manufacturing semiconductor devices by automating the connecting parts between processes and making at least a portion of the semiconductor device manufacturing line an integrated production line.

本発明は半導体装置の生産装置鈑システムに於て、ある
工程PNの製造装置MNと次の工程PN+1の製造装置
MN+1との間に、自動的な検査機構を持つ検査装置C
Nを導入し、その検査装置CNに予め検査項目の中央値
と許容範囲の上限と下限を設定しておいて、検査結果が
中央値ならそのま1割1品を次工程PN+1の製造装置
MN+1へ送るが検査結果が規格外であれば不良品とし
て次工穏PN+tの製造装置MN−1−1へ適寸せず、
又、規格内であっても中す値から正の側にずれていれば
次工程PN+1の製造装置M N+ 1あるいはそれ以
降の工程PN+Mの製造装置M N+Mに対し、該ずれ
の分を補償すべく処理をするような指示を出し、中央値
から負の側にずれていれば次工程Ph++xのfM造架
装置pi+1あるいはそれ以降の工程PN+Mの製造装
置MN+ Mに対し前記補償とは逆の方向の補償なすべ
く処理を行うよう指示をするようにして、次工程PN+
 1の製造装置F(; M N + 1へ通貫せるよう
製造ラインを構成し7゛ζことを特徴とする、半導体装
置の生産装置システムである。
The present invention provides an inspection apparatus C having an automatic inspection mechanism between a manufacturing apparatus MN of a certain process PN and a manufacturing apparatus MN+1 of the next process PN+1 in a production apparatus board system for semiconductor devices.
N is introduced, the median value of the inspection item and the upper and lower limits of the allowable range are set in advance on the inspection device CN, and if the inspection result is the median value, 10% of the product is transferred to the next process PN+1 manufacturing device MN+1. However, if the inspection result is out of specification, it will be considered a defective product and will not be sent to the manufacturing equipment MN-1-1 of the next factory PN+t.
In addition, even if it is within the specification, if it deviates from the neutral value to the positive side, the deviation will be compensated for the manufacturing equipment M N+ 1 of the next process PN+1 or the manufacturing equipment M N+M of the subsequent process PN+M. If it deviates to the negative side from the median value, the fM frame building device pi+1 of the next process Ph++x or the manufacturing device MN+M of the subsequent process PN+M will be compensated in the opposite direction to the above compensation. The next process PN+
This is a production equipment system for semiconductor devices, characterized in that the production line is configured so as to be able to pass through the manufacturing equipment F (; MN + 1) of 7゛ζ.

又、本発明は半導体装置の生産装置システムに於て、あ
る工程PN の製造装置MNと次の工程PN+xの製造
装置M、N + tとの間に、自動的な検査楼能を持つ
検査装置CNを導入し、その検査装置CNに予め検査項
目の中央1市と許容できる上限と下限の矧格値を設定し
ておいて、f!#育結果が中央値であればそのまま製品
を次工程へ進ませるが、検査結果が規格外であれば不良
品として次の工程PN+tのy1′!造装置MN+1へ
は進ませず、又、規格内であっても中央値から正の1目
11にずれていれば次の工程PN41の製造装置MN+
1あるいけそれり降の工程PN 4Mの製造装置MN+
uに対t7該ずれ分を補(Jl’すべく処理をするよう
指示を出すと共に工程PN の製造装置MNに対しては
中央値に近づけるようなΦ件にする指示を出し、又中央
値から負の側にずれていれば、次の工程PN−日の製造
装置M N + 1あるいはそれ以降の工程PN+Mの
製造装置MN+λ(に対し該ずれの分を前記とは逆向き
の補償をすべく処理をするよう指示を出すと共に、工程
PN の製造装置MNに対しては中央値に近づけるよう
な条件に変更する指示を出し、製品を次工程PN+1の
製造装置M N + 1へ進ませるような製造ラインを
構成したことを特徴とする、該半導体装置の生産装置シ
ステムである。
Further, the present invention provides an inspection apparatus having an automatic inspection floor function between a manufacturing apparatus MN of a certain process PN and a manufacturing apparatus M, N + t of the next process PN+x in a semiconductor device production equipment system. CN is introduced, and the central 1 city of the inspection item and the permissible upper and lower limit values are set in advance on the inspection device CN, and f! #If the test result is the median value, the product will proceed to the next process, but if the test result is out of specification, it will be considered a defective product and will be moved to the next process PN+t y1'! It will not proceed to manufacturing equipment MN+1, and even if it is within the specifications, if it deviates from the median by a positive 1 or 11, it will not proceed to manufacturing equipment MN+ for the next process PN41.
1 step down process PN 4M manufacturing equipment MN+
An instruction is given to u to compensate for the deviation (Jl') from t7, and an instruction is given to the manufacturing equipment MN of process PN to make the Φ value closer to the median value. If it deviates to the negative side, the manufacturing device MN + 1 of the next process PN− day or the manufacturing device MN + λ of the subsequent process PN + M (in order to compensate for the deviation in the opposite direction to the above) At the same time, an instruction is issued to the manufacturing equipment MN of the process PN to change the conditions to bring it closer to the median value, and the product is sent to the manufacturing equipment MN + 1 of the next process PN+1. This is a production equipment system for semiconductor devices, characterized in that a production line is configured.

本発明により工程PN の製造装置MNと次工程PN+
1の製造装WM N + 1との連結が可能となυ自動
化され、−月した半導体装置の製造が可能となる。
According to the present invention, the manufacturing apparatus MN of the process PN and the next process PN+
It is possible to connect the manufacturing equipment WM N + 1 to the manufacturing equipment WM N + 1 and to automate the manufacturing of semiconductor devices.

又、本発明によシ発展の源である人間が製造ライン中に
居る必要が無くなるので製造ラインを高い清浄度に維持
できる。更に又上記2つの効果により均一な品質で、半
導体装置を生産できるという付随する効果もある。更に
又、上記の効果によシ製造装置の稼動率を上げ生産性を
向上できる。
Furthermore, the present invention eliminates the need for humans, who are the source of development, to be present on the production line, making it possible to maintain a high level of cleanliness on the production line. Furthermore, due to the above two effects, there is also the accompanying effect that semiconductor devices can be produced with uniform quality. Furthermore, due to the above effects, the operating rate of the manufacturing equipment can be increased and productivity can be improved.

次に本発明の実施例を図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

先ず比較のため従来の方法を説明する。第1図、第2図
は従来の技術である。第1図は最終デストを終えた後で
データを分析し工程を変更する方法であり、良品率を高
めるべく工程を変更するには完成品の悄叩を必要上する
。又第2図の方法も第1図の如く完成品の情報もさるこ
とながら途中工程の情報で工程変更がなされてはいるが
、いずれも検査後、前工程の条件を変更するシステムに
なっておシ、その検査データは次工程へ送られていない
。従って一度中央値からずれだ製品はその「ずれ」の分
を最後まで補償されることなく持ち続けることになる。
First, a conventional method will be explained for comparison. FIGS. 1 and 2 show the conventional technology. Figure 1 shows a method of analyzing data and changing the process after the final dest, and changing the process to increase the rate of non-defective products requires shaking up the finished product. Furthermore, in the method shown in Figure 2, as shown in Figure 1, process changes are made based on not only information on the finished product but also information on intermediate processes, but in both cases the system changes the conditions of the previous process after inspection. Unfortunately, the inspection data has not been sent to the next process. Therefore, once a product deviates from the median value, it will continue to carry that ``deviation'' until the end without being compensated for.

それに対し第3図は本発明の一実施例の方式を説明する
だめの図である。即ち工程PN4−1 との間に検査機
能を持つシステムを導入し、工程PN を経た品物の力
0工寸法あるいは物理的測定値等が規格の中央値に対し
て正又は負にずれているか否かを検定し、例えば正にず
れていれはそれが規格内か否かを次に検定する。もし規
格外なら再工事をするか又は廃棄せざるを得ないが、規
格内であれば、次の工程PN+1に対し該品物は前工程
PN で正側にずれているという情報を与え、工HL)
N + sの条件を変更して該正側へのずれ分を工程P
N−+−1で補償する。もし負側にずれていた場合も同
様で、前記と逆向きに負側のずれ分を工程PN41で補
償するよう工8PN+xの条件変更を行う指示を力える
機構を持たせる。
On the other hand, FIG. 3 is a diagram for explaining the system of one embodiment of the present invention. In other words, we will introduce a system with an inspection function between process PN4-1 and check whether the force dimensions or physical measurement values of products that have passed through process PN deviate positively or negatively from the standard median value. For example, if there is a positive deviation, then it is verified whether it is within the standard. If it is out of specification, it will have to be reworked or discarded, but if it is within specification, information will be given to the next process PN+1 that the item has deviated to the positive side in the previous process PN, and the work HL )
By changing the conditions of N + s, the deviation to the positive side is calculated as process P.
Compensate with N-+-1. The same applies if there is a deviation on the negative side, and a mechanism is provided to issue an instruction to change the conditions of step 8PN+x so that the deviation on the negative side is compensated for in step PN41 in the opposite direction.

第4図は本発明の第2の実施例の方式を説明する図であ
る。即ち工8PNを経た製品の加工寸法あるいは物理的
測定値等が予め設定されている規格の中火値に対して正
又は負にずれていかか否かを先ず検定し、例えばもし正
にすれている場合、次にそのずれた分が規格内か規格外
かを相定する。
FIG. 4 is a diagram illustrating the method of the second embodiment of the present invention. That is, it is first verified whether or not the processed dimensions or physical measurement values of the product that has gone through the process 8PN deviate positively or negatively from the medium heat value of the preset standard. If so, then determine whether the deviation is within or outside the specifications.

その値が規格外の場合は再工事又は廃棄処分にせざるを
得ない。又規格内であれは次の工HPN+1に対し、該
製品は前工程PNで正側にずれているという情報を与え
、次工程PN+1の条件を変更して該正側へのずれ分を
工程PN+1で補償するようにする。又、規格内外に拘
らず正側にずれている情報は前工程PNへ伝えられ工程
PN 自身も条件を変更し是正するようにする。負側に
ずれていた場合も同様で工程2次+1には正側方向への
補イ1°tを、又工8PN にも正側への是正をそれぞ
れ指示するシステムを構成しておく。
If the value is outside the standard, the work must be rebuilt or disposed of. Also, if it is within the specifications, information is given to the next process HPN+1 that the product deviates to the positive side in the previous process PN, and the conditions of the next process PN+1 are changed to calculate the deviation to the positive side by process PN+1. to compensate for this. In addition, information that deviates to the positive side regardless of whether it is within or outside the standard is transmitted to the previous process PN, and the process PN itself changes its conditions and corrects it. Similarly, when the deviation is on the negative side, a system is configured to instruct the process 2nd +1 to make a correction 1°t in the positive direction, and also instruct the process 8PN to correct it in the positive direction.

このような第3図、第4図による方法を生産装置の中に
組込むことにより一貫生産システムにして製造する技術
を確立すると、製品の品質並びに製造ラインそのものが
安定になる。
By incorporating the methods shown in FIGS. 3 and 4 into production equipment and establishing a technology for manufacturing as an integrated production system, the quality of the product and the manufacturing line itself will become stable.

更に具体的に例をあけて説明する。第5図はMO8型電
界効果トランジスタを用いた集積回路の製造工程の一部
であυ、ゲート電極となる多結晶シリコンのエツチング
加工工程と次のソース・ドレイン形成工程とを示すもの
である。即ち多結晶シリコン膜成長工程PN−1を通シ
、多結晶シリコン加工工程PN を経てソース・ドレイ
ン形成工程1’rq+tへ至る部分である。詳細に評、
明すると第5しJ13ように工程PN−1で出来た多結
晶シリコンn−51の上にレジスト膜52を塗布し、約
50℃で10分はど軽く焼き締めた後、位置合わせ露′
)Y:を行い、然る後にそのレジスト膜52の現像液を
用いて現像し、外観を検査して異常が無けれは約200
℃で1時間焼き締める。次いでCFJ  系のガスを用
いて多結晶シリコンUN51をプラズマエッヂングし、
その後エツチングのマスクとなってイタレジスト膜52
を剥削し検査システムCNへ進ませる。ここでエツチン
グ後の多結晶シリコンのゲート電極の幅の検査データの
一例が第6図であり、今ウェハNの値が測定されたとす
る。寸法測定には市販のレーザー光を用いた測長機でよ
く、そこ迄のウェハーの搬送はエアベルト方式かロボッ
ト車によればよい。さてここでウェーハNのように第7
図(イ)のLの中央値2μIn に対し規格内(2μ±
0.2μ)ではあるが、多結晶シリコン71の加工l1
(lLが第7図[相]のように2.1μと正の側にすれ
ているとする。このウェーハは規格内なので第5図にて
そのt寸次のソース53、ドレイン54を形成するだめ
As イオン注入を行う工iPs+xへ進ませる。しか
しこの時検査システムCNより先の結果がこの工程PN
+1へ伝達されておシ、イオン注入後の窒素気流は10
00℃で30分熱処理をする工程にて熱処理時間を35
分にし0.1μの横方向への熱拡散を行なわせて実効チ
ャネル長Leffが、第7図(C) 、 (勇に示され
ているように多結晶シリコンゲート電極幅りが中央値で
あった場合と同じになるように自動的に熱処理炉システ
ムの調整を行う。これによシ、工程PN のシステムで
の揺らぎが工8PN+x のシステムで補イ阿されたこ
とになる。
This will be explained more specifically using an example. FIG. 5 is a part of the manufacturing process of an integrated circuit using an MO8 type field effect transistor, and shows the etching process of polycrystalline silicon that will become the gate electrode and the next process of forming the source and drain. That is, this is the part that passes through the polycrystalline silicon film growth step PN-1, passes through the polycrystalline silicon processing step PN, and then reaches the source/drain formation step 1'rq+t. Review in detail,
In the fifth step, as shown in J13, a resist film 52 is applied on the polycrystalline silicon n-51 made in step PN-1, and after being lightly baked at about 50°C for 10 minutes, alignment exposure is performed.
) Y:, and then developed using a developer for the resist film 52, and inspected the appearance.
Bake at ℃ for 1 hour. Next, polycrystalline silicon UN51 was plasma etched using CFJ-based gas, and
Thereafter, the itaresist film 52 serves as an etching mask.
It is scraped off and sent to the inspection system CN. Here, it is assumed that FIG. 6 shows an example of the inspection data of the width of the polycrystalline silicon gate electrode after etching, and that the value of wafer N has just been measured. A commercially available length measuring machine using a laser beam may be used for dimension measurement, and the wafer may be transported up to that point using an air belt method or a robot vehicle. Now, like wafer N, the seventh
The median value of L in Figure (a) is 2μIn, which is within the standard (2μ±
0.2μ), but the processing of polycrystalline silicon 71 l1
(Assume that lL is 2.1μ on the positive side as shown in Figure 7 [phase]. Since this wafer is within the standard, the source 53 and drain 54 of the same size as t are formed in Figure 5. No As Proceed to the process iPs+x where ion implantation is performed.However, at this time, the results from the inspection system CN are
+1, the nitrogen flow after ion implantation is 10
The heat treatment time is 35 minutes in the process of heat treatment at 00℃ for 30 minutes.
By performing thermal diffusion in the lateral direction of 0.1μ per minute, the effective channel length Leff is determined by the width of the polycrystalline silicon gate electrode being the median value, as shown in FIG. The heat treatment furnace system is automatically adjusted so that it is the same as in the case where the heat treatment furnace is used.As a result, fluctuations in the system for process PN have been compensated for by the system for process 8PN+x.

上述の例は第3図の流れに相当するが、ここで検査シス
テムCNの情報を同時に工程PN−1へ伝達しエツチン
グ装置システムを争件変更することによ9次のエツチン
グ時間をもう少し長くするよう1.+A整して横方向へ
のエツチング算を制御しLが2.0μに々るようにすれ
ば、これは第4図の実施例と対応することになる。
The above example corresponds to the flow shown in Figure 3, but the information from the inspection system CN is transmitted to process PN-1 at the same time and the etching equipment system is changed to make the ninth etching time a little longer. Good 1. If +A is adjusted and the etching calculation in the lateral direction is controlled so that L is equal to 2.0μ, this corresponds to the embodiment shown in FIG.

第8図は上記の例を更に模式図的に示した本のである。FIG. 8 is a book further schematically showing the above example.

即ちウェハ80が流れていく様子をベルトコンベヤーの
断面図風に記し、そJ+、に制御装置が連絡されている
。これを第5図と対応させながら説明すると、第8図に
て工よりウェハ80が多結晶シリコン成長H置81ヘベ
ルトコンベヤー81′で送り込まれる。この多結晶シリ
コン成長装置81を制御するのがコンピュータMN−1
,にでありこの=+yビューp MN−1、にハ親コン
ピュータRN−iに連結されている。必要ならこの親コ
ンピータ几N−1は更に上位コンピュータCPUへ結線
されている。ウエノ・80は多結晶シリコンが成長され
ると膜質検査装置CN−1へ送シ込まれ、ここで膜厚、
層抵抗、グレインサイズ等を検査され、その値が親コン
ピユータRN−t、RNへ送られる。その値が中央値よ
り正側、負側いずれにずれているか、又そのずれの値が
規格内かなどが処理され、その対策が親コンピュータ几
N−t、ILNから必要な制御装置へ指示される。もし
規格内であれはウエノヘ80はレジスト塗布装置82へ
送シ込まれ、レジスト液を例えば回転塗布される。然る
後、約100℃の乾燥炉83へ送り込まれ一定時間軽く
前処理として焼成された後、露光装置84でマスクパタ
ーンとウェハの位置合せを行って紫外線を露光される。
That is, the flow of the wafers 80 is depicted as a cross-sectional view of a belt conveyor, and a control device is connected to the belt conveyor. This will be explained in conjunction with FIG. 5. In FIG. 8, a wafer 80 is sent from a machine to a polycrystalline silicon growth station 81 by a belt conveyor 81'. The computer MN-1 controls this polycrystalline silicon growth apparatus 81.
, and this=+y view p MN-1, which is connected to the parent computer RN-i. If necessary, this parent computer N-1 is further connected to a higher-level computer CPU. When polycrystalline silicon is grown, Ueno-80 is sent to the film quality inspection device CN-1, where the film thickness and
The layer resistance, grain size, etc. are checked and the values are sent to the parent computer RN-t, RN. It is processed whether the value deviates from the median value to the positive side or negative side, and whether the value of the deviation is within the standard, and countermeasures are given to the necessary control devices from the parent computer N-t and ILN. Ru. If it is within the specifications, the coating material 80 is sent to a resist coating device 82, and a resist solution is applied, for example, by rotation. Thereafter, the wafer is sent to a drying oven 83 at about 100.degree. C. and lightly baked for a certain period of time as a pretreatment.The wafer is then aligned with the mask pattern in an exposure device 84 and exposed to ultraviolet light.

続いて、ウェハ80は現像装備″、85で現像され、外
観検査装[CN′で外観をチェックされiヒ後、150
℃の算囲気で焼成炉86中にてレジストを硬化させる。
Subsequently, the wafer 80 is developed in the developing equipment 85, and its appearance is checked in the visual inspection equipment CN'.
The resist is hardened in a firing furnace 86 at an ambient temperature of .degree.

その後ウェハ80をドライエツチャー87へl)込み、
多結晶シリコンをドライエツチングした後、プラズマア
ッシャ−88へ送ってレジスト膜を除去し、検査装置I
CNでチェックを受ける。この間レジスト塗布装置82
からプラズマアッシャ−88迄の装置はいずれもコンピ
ュータMNIからコンビーータMNr迄の制御を受り、
このコンピュータMNI〜MN7は親コンピュータ几N
必要なら更に上位コンピュータCPNへ結線されている
。検査装置CNにて多結晶シリコンのエツチングパター
ンの寸法、形状、などをチェックし、その値が規格内か
否かずれた値が正か負かなどの情報がそれぞれ親、コン
ピュータiLN 、 I(N+ 1.−上位コンピュー
タCI’Uへ伝えられ対t′L指示を仰ぐシステムとな
りている。前述の如き適切々指示がなされた後、規格内
ウェハは次のイオン注入装置E+9へ送り込まれ8吸・
肝のイオンを111示に基いてjjl’lj !lj!
(された売件で注入される。
After that, the wafer 80 is placed in the dry etcher 87,
After dry etching the polycrystalline silicon, it is sent to a plasma asher 88 to remove the resist film, and then transferred to the inspection equipment I.
Get checked by CN. During this time, the resist coating device 82
All of the devices from the plasma asher 88 to the plasma asher 88 are controlled by the computer MNI to the conbeater MNr.
These computers MNI to MN7 are parent computers 几N
If necessary, it is further connected to a higher-level computer CPN. The inspection device CN checks the dimensions, shape, etc. of the etched pattern of polycrystalline silicon, and information such as whether the values are within the specifications and whether the deviated values are positive or negative is sent to the parent and computers iLN and I(N+), respectively. 1. - The system sends the information to the upper computer CI'U and asks for the t'L instruction.After the above-mentioned appropriate instructions are given, the wafer within the specification is sent to the next ion implanter E+9, where it is 8-injected.
Based on the liver ion 111 jjl'lj! lj!
(It will be injected when the sale is made.

以上エツチング工程と不、f;II物ドープ工程間のつ
なき゛の部分(・(ついてU’4. ’!i ’c、し
たが、本発明は回様な考え方で全工程間をつなぐことが
出来る。それにより製造ラインは自己正常化能力を持つ
ことになり、又出来上った製品の品質も極めて均質なも
のが伊られるようになる。更に又本発明の実施例とし7
て工程PN での揺らぎを次工程PN+1 のみで捕(
:l’tする場合のみを例示したが、本発明は単にこの
ような場合のみでなく、工程PN の揺らぎを次工程P
N+1 あるいは必要ならそれ以降の工わで補償[7て
もよい3、更に又本発明の実施例では、第1図、第2図
で」6けられているような最終検査の結果が名工程に条
件変更を要求するルートを省いであるが、勿論必要なら
その機能を合わせ付加しても良いことは云う迄も無い。
Above is the connection between the etching process and the II doping process. As a result, the production line will have a self-normalizing ability, and the quality of the finished product will be extremely uniform.Furthermore, as an embodiment of the present invention,
Then, the fluctuation in process PN is captured only in the next process PN+1 (
:l't, but the present invention is applicable not only to such a case, but also to the next process P.
N+1 or, if necessary, compensation by subsequent work [7].Furthermore, in the embodiment of the present invention, the results of the final inspection as indicated by "6" in FIGS. Although the route for requesting condition changes is omitted, it goes without saying that the function may be added if necessary.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明と比較するために掲げた従来の
代表的な生導体装置ネ°1造プロセスを流す図、第3図
、第4図は本発明の第1、第2の実施例を示す半導体装
置製造プロセス線図、第5図A及びBはそれぞれ本発明
の実施例を更に詳細に説明する工程図とそれに対応する
半導体ウェーハの断面図、第6図、第7図は第5図をよ
り詳しく討明するだめの一部工程の品賀賀理図とウェー
ハ断面図であシ、第8図は更に第5図のjlrれを枠弐
図的に示しだシステム拾成図である。 なお図においで、51.71・・・・・・多結晶シリコ
ン、52・・・・・レジス)IIφ、53・・・・・・
ソース、54・・・・・・ドレイン、80・・・・・・
ウェハ、81・・・・・・多結晶シリコ7成&装置、8
1’・・・・・ベルトコンベヤー、82・・・・・・レ
ジスト塗布装置、83・・・・・・乾燥炉、84・・・
・・・露光装置、85・・・・・・現像装置0.86・
・・・・・焼成炉、87・・・・・・ドライエツチャー
、88・・・・・・プラズマアッシャ−189・・・・
・・イオン注入装歴である。 講工庫句よ託良 険久 (A )             / Q)+234
54178、−   、−  Nつ1−ハ (作1順) 斤7G 個
Figures 1 and 2 are diagrams showing the manufacturing process of a typical conventional live conductor device for comparison with the present invention. FIGS. 5A and 5B are process diagrams illustrating the embodiments of the present invention in more detail, and corresponding cross-sectional views of semiconductor wafers, FIGS. 6 and 7, respectively. Figure 5 is a diagram of Shinagari and a wafer cross-sectional view of a part of the process to explain Figure 5 in more detail. It is a complete drawing. In the figure, 51.71...polycrystalline silicon, 52...regis) IIφ, 53...
Source, 54...Drain, 80...
Wafer, 81... Polycrystalline silicon 7 formation & equipment, 8
1'...Belt conveyor, 82...Resist coating device, 83...Drying oven, 84...
...Exposure device, 85...Development device 0.86.
・・・・・・Firing furnace, 87・・・Dry etcher, 88・・・Plasma asher-189・・・
...History of ion implantation equipment. Kokoko haiku yo Takuran Kenkyu (A) / Q) +234
54178, - , - N 1-Ha (in order of production) 7G pieces

Claims (2)

【特許請求の範囲】[Claims] (1)半導体装置の生産装置システムにて、ある製造工
程PNの製造装置MNと次の製造工程PN+1で使う製
造装置MN+sとの間に自動的な検査機能を持つ検査製
造CNを導入し、該検査製造CNに予め検査項目の中央
値と許容範囲を設定し、検査結果が中央値であればその
まi製品を製造工程PN+1の製造装置MN+1へ進ま
せ、検査結果が中央値から正(tllにずれていれば、
それが規格外の場合d不良品として次工程1’N+xの
製造装置MN+1へは進ませず、それが規格内の場合は
次工程PN+1の製造装@ MN + tあるいはそれ
以降の工程Pu+h<の製造装置MN+ Mに対し、正
側へのずれ分を補償する処理を指示し、又検査結果が中
央値から負側へずれていれば、それが規格外の場合は不
良品として次工程P N + 1の製造装置1yjN+
1へは進ませずそれが規格内のり゛・合は次工程PN+
 1の製造装置MN+1あるいはそれ以降の工程Ps+
uの製造装置MN・トMに対し、負側へのずれ分を補償
する処置を行うよう指示するようにし、て、製品を次工
程PN+1の製造装7z二MN+tへ進ませるよう構成
した球を特徴とする半導体装{6を自動的に一貫生産す
ることを特許とする半導体装置の生産装置システノ・。
(1) In a semiconductor device production equipment system, an inspection manufacturing CN with an automatic inspection function is introduced between the manufacturing equipment MN of a certain manufacturing process PN and the manufacturing equipment MN+s used in the next manufacturing process PN+1, and Set the median value and tolerance range of inspection items in the inspection manufacturing CN in advance, and if the inspection result is the median value, proceed to the manufacturing device MN+1 of the manufacturing process PN+1, and if the inspection result is positive (tll) from the median value. If it deviates from
If it is out of specification, it is considered a defective product and is not allowed to proceed to the next process 1'N+x manufacturing equipment MN+1, and if it is within the specifications, it is sent to the next process PN+1 manufacturing equipment @ MN + t or the subsequent process Pu+h<. The manufacturing equipment MN+M is instructed to perform processing to compensate for the deviation to the positive side, and if the inspection result deviates from the median value to the negative side, if it is out of specification, it is considered a defective product and sent to the next process P N + 1 manufacturing equipment 1yjN+
Do not proceed to step 1. If it is within the specifications, proceed to the next process PN+
1 manufacturing equipment MN+1 or subsequent process Ps+
A ball configured to instruct the manufacturing equipment MN and tM of u to take measures to compensate for the deviation to the negative side, and advance the product to the manufacturing equipment 7z2MN+t of the next process PN+1. Sisteno is a semiconductor device production system that has a patented feature of automatic integrated production of semiconductor devices.
(2)半導体装置、の生産装置システム−にて、ある、
4(′J造工程PN の製造装置MN と次の製造工程
PrJ←1の製造装置M N + 1との間に自動的な
検査機能る持つ検査装置CN を導入し、該検査装置C
rJ11こ予め検査項目の中央値と許容範9Bを設定し
、検査結果が中央値であればそのまま製品な工程PN+
 sの製造装置MN+tへ進ませ、検査:結果が中央値
から正側にずれていればその値が規格外の時は不良品と
して次工程PN+1の製造装τ。 MN+1へは進ませず、それが規格内であれば次工程P
N+1の製造装置MN+1おるいはそit以+ypの工
程PN+Mの製造装置MN+Mに対し、正側のずれ分を
補償するように指示し)又工程PNの製造装閾釈I N
に対しては中央値に近づけるような条件に変更するよう
指示を田し、一方、検査結果が中央値から負(illに
ずれでいればその値が却、格外の時は不良品として次工
程PrJ+1の製造装M、MN+1へは進ませず、そQ
値が規、(3内でちれば次工程PN+1の製造装置MN
+sあるいはそれ以降の工程P N + h+の製造装
置MN+Mに対し、負側のずれ分を補償するように指示
し、又工程PNの製造装置?・4Nに対しては中央値に
近づりるような+ 注に変更するよう指示を出して製品
を次工程、PN+1の製造装置Δ4N+1へ進ませるよ
う構成し/こことを特徴とする半導体装置を自動的に一
貫生産する該半導体装置の生産装置システム。
(2) In a production equipment system for semiconductor devices, there is
4 ('Introducing an inspection device CN with an automatic inspection function between the manufacturing device MN of the J manufacturing process PN and the manufacturing device MN + 1 of the next manufacturing process PrJ←1, and installing the inspection device C
rJ11 Set the median value and tolerance range 9B of the inspection items in advance, and if the inspection result is the median value, the process PN+ is the same as the product.
Proceed to manufacturing equipment MN+t for s, and inspect: If the result deviates from the median value to the positive side, if the value is outside the standard, it is determined to be a defective product and sent to manufacturing equipment τ for the next process PN+1. Do not proceed to MN+1, and if it is within the specifications, proceed to the next process P
Instruct the manufacturing device MN+1 of N+1 or the manufacturing device MN+M of the process PN+M of the process PN+yp to compensate for the deviation on the positive side) and the manufacturing device threshold I N of the process PN.
If the test result is negative (ill) from the median value, the value is negative, and if it is out of range, the product is considered defective and sent to the next process. PrJ+1 manufacturing equipment M, do not proceed to MN+1, and Q
The value is the standard (if it is within 3, the manufacturing equipment MN for the next process PN + 1)
+s or the subsequent process P N + h+ manufacturing equipment MN+M is instructed to compensate for the negative side deviation, and the manufacturing equipment MN+M of process PN +s or subsequent process is instructed to compensate for the deviation on the negative side.・For 4N, an instruction is issued to change to a + note that approaches the median value, and the product is configured to proceed to the next process, the manufacturing equipment Δ4N+1 for PN+1. A production equipment system for automatically integrated production of semiconductor devices.
JP57140253A 1982-06-23 1982-08-12 Production device system of semiconductor device Granted JPS5929427A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57140253A JPS5929427A (en) 1982-08-12 1982-08-12 Production device system of semiconductor device
US06/506,677 US4571685A (en) 1982-06-23 1983-06-22 Production system for manufacturing semiconductor devices
GB08317126A GB2126374B (en) 1982-06-23 1983-06-23 A production system for the manufacture of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57140253A JPS5929427A (en) 1982-08-12 1982-08-12 Production device system of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5929427A true JPS5929427A (en) 1984-02-16
JPH027178B2 JPH027178B2 (en) 1990-02-15

Family

ID=15264474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57140253A Granted JPS5929427A (en) 1982-06-23 1982-08-12 Production device system of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5929427A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122340U (en) * 1985-09-19 1987-08-03
JPS62237318A (en) * 1986-04-08 1987-10-17 Amada Co Ltd Product measuring and inspecting instrument
JP2003519920A (en) * 2000-01-04 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド On-site control of dry etcher

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107802A (en) * 1980-12-24 1982-07-05 Hashimoto Denki Co Ltd Direct welding method for hot-melt resin impregnated thread to green veneer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107802A (en) * 1980-12-24 1982-07-05 Hashimoto Denki Co Ltd Direct welding method for hot-melt resin impregnated thread to green veneer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122340U (en) * 1985-09-19 1987-08-03
JPS62237318A (en) * 1986-04-08 1987-10-17 Amada Co Ltd Product measuring and inspecting instrument
JP2003519920A (en) * 2000-01-04 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド On-site control of dry etcher

Also Published As

Publication number Publication date
JPH027178B2 (en) 1990-02-15

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