JPS5929413A - Laminated ceramic chip condenser - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer ceramic chip capacitor that can prevent bin poles in external electrodes and eliminate solder erosion.

Multilayer ceramic chip capacitors are experiencing rapid growth as electronic circuit components become smaller and larger in capacity.

FIG. 1 is an external view showing a conventional 8-layer ceramic chip capacitor, and FIG. 2 is a cross-sectional view taken along line A-A' in FIG. In the figure, (1) is a ferroelectric ceramic forming a capacitor, (2) is an external electrode made of Ag--Pd, and (3) is an internal electrode made of Pd or the like in which a large number of sheets are alternately laminated.

Note that FIGS. 3(A) to 3(E) are diagrams showing various printing patterns of internal electrodes (3) printed on ferroelectric ceramic green sheets (4), respectively.

The multilayer ceramic chip capacitor with the above configuration has a large number of internal electrodes (3) to achieve the designed capacitor capacity.
They are laminated alternately and fired after pressing.

Then, an external electrode (2) is applied and fired to complete the process.

As shown in Figures 3(A) to 3(E), the reason why there are various printed patterns on the internal electrodes (3) is that the internal electrodes of early multilayer ceramic chip capacitors Simple printing patterns as shown in Figure 3 (E) occupy most of the printing patterns, but they are hardly used at present. On the other hand, when the purpose is to further increase the capacitance of the internal electrodes and to reduce the resistance of the internal electrodes as much as possible, the internal electrodes shown in Fig. 3 0) to 3.
The printing pattern shown in Figure 1) has been developed. Figure 4 also shows the internal electrodes (3) of the printed pattern shown in Figure 3 (e).
) multiple sheets fIltw! FIG. 3 is a side view of the multilayer chip capacitor with the end surfaces of external electrodes removed. In a multilayer chip capacitor with this configuration, the part without electrodes (
5) occurs on both sides, the electrical connection between the internal ffl'[(31 and the external electrode (21) is only at one end. was coated very thickly, and even after firing it had a thickness of more than 20μ at the corners.Also, Figure 5 shows the inner electrode (3) of the printed pattern shown in Figure 3 (a) or ) is a side view of a multilayer chip capacitor 1c in which a plurality of layers are stacked, with the end surfaces of external electrodes removed.

However, in conventional multilayer ceramic chip capacitors, especially in the case of the multilayer ceramic chip capacitor shown in FIG. Ag by lowering the weight ratio (Pd view: 10vr%), etc.
+Pd countermeasures are taken, and as a result, the solder corrosion resistance is reduced. In extreme cases, many pinholes (6) are generated in the vicinity of the outer electrode (2) course portion and the inner electrode exposed portion. The cause of the pinhole (6) near the exposed part of the internal electrode is the internal electrode resistance Pd and the external electrode Hamura Ag.
This is because when Pd undergoes an alloy reaction, it grows by eating the surrounding Ag--Pd. Therefore, when placed in a solder bath, there were drawbacks such as the phenomenon that the solder was eaten away (soldering resistance of about 3 seconds at 230°C ± 5°C) on the poles, corners, and external electrodes. Therefore, an object of the present invention is to provide HtF that can improve solderability even if the coating thickness of the external electrode is reduced.
7i ceramic chip capacitor.

In order to achieve this purpose, I am launching this project I'! , fJ has only one end of the F3 part electrode exposed to the external electrode and in contact with it.
However, predetermined voids F are provided at both ends of the internal electrodes so that the external electrodes K are not exposed.This will be explained below using examples.

FIG. 6 is a cross-sectional view showing one embodiment of a multilayer ceramic chip capacitor according to the present invention, and in particular, a side view with external electrodes removed. In the same [U], (7) is an internal electrode whose detailed printed pattern (8) is shown in FIG.

Note that the printed pattern (8) of the internal electrode (7) shown in FIG.
), the gap was provided at a distance of 0.3 to 0.5 mm from both ends of the ferroelectric green sheet (4).

In the multilayer ceramic chip capacitor with this configuration, as shown in Figure 7, the internal electrodes are formed in a printed pattern (8) with a gap of 0.3 to 0.5 m from both ends of the ferroelectric green sheet (4). do. And this internal electrode (
7) is laminated, fired, and then shaped so as not to wash out both ends of the ceramic, leaving voids on both sides of the ceramic as shown in FIG. By providing a gap of 0.3 to 0.5+nm in this way, only one end was in contact with the Kube electrode material, and the firing thickness of the outer electrode corner was 5 μm, and the Pd content was Even if it is set to 10%, as shown in Figure 6, pinhole (6)
A smooth external electrode can be formed without the occurrence of blemishes. When dipped in a solder bath at 230'C'' and 75C, no solder eating phenomenon occurs until 12 seconds.

In addition, by increasing the electrode area as much as possible, it is possible to increase the circumferential capacitance and reduce the internal electrode resistance. In this way, the Pd content in the Ag-Pd of the external electrode Hamura was reduced to 10%, and the corner thickness (after firing) was reduced to 5μ.
Even if the temperature is reduced to m, iii″I is 230 as solderability.
Can be maintained at ℃±5℃ for up to 12 seconds.

As explained in detail above, according to the multilayer ceramic chip capacitor according to the present invention, a predetermined gap is provided at both ends of the internal electrode. The coating thickness can be set to a predetermined thickness at the corner, and the Pd content can be set to 1, for example.
Even at 0%, solderability can be guaranteed, and
It has the advantage of being able to be manufactured at low cost.

[Brief explanation of the drawing]

Fig. 1 is an external view showing a conventional multilayer ceramic chip capacitor, Fig. 2 is a cross-sectional view taken along line A-A', and Figs.
Fig. 3 (E) is a diagram showing various printed patterns of the internal electrodes shown in Fig. 1, and Fig. 4 is a diagram showing a laminated structure in which a plurality of internal electrodes (3) with the printed patterns shown in Fig. 3 (E) are laminated. Side view of a chip capacitor with the end surface of the external electrode removed.
Figure 5 is a side view of a multilayer chip capacitor in which a plurality of internal electrodes (3) with the printed pattern shown in Figure 3 (a) or 3) are laminated, with the outer electrode end surface removed; 7 is a cross-sectional view showing one embodiment of the multilayer ceramic chip capacitor according to the present invention, and FIG. 7 is a plan view showing the printed pattern of the internal electrodes shown in FIG. 6. (11... Ferroelectric ceramic, (2)... External electrode, (3)... Internal electrode, (4)... Ferroelectric ceramic green sheet, (5)... ... Part without electrode, (6) ... Pinhole, (71 ...
Internal electrode, (8)...Printed pattern. In addition, in the figures, the same reference numerals indicate the same or similar parts. Agent Kuzuno - Figure 1 Figure 2 Figure 3 Procedure amendment? '-F (Voluntary) Commissioner of the Japan Patent Office 1, Indication of the case 1.1 Application No. 57-14087
0 No. 2, Name of the invention Multilayer ceramic chip capacitor 3, Person making the amendment Representative Hitoshi Katayama Department 4, Agent 5, Column 6 for detailed explanation of the invention in the specification to be amended, Contents of the amendment (11 specifications) ``It occupies most of the time'' on page 2, line 15 of the book.
amend it to "accounted for the majority". (21 Ibid., page 4, line 11, “to be in good condition” is amended to “keep in good condition.”)

Claims (1)

[Claims] A multilayer ceramic chip capacitor in which only one end of an internal electrode is exposed and connected to an external electrode is characterized in that a predetermined gap is provided at both ends of the internal electrode so that the internal electrode is not exposed to the external electrode. Multilayer ceramic chip capacitor.