JPS5928206A - Magnetic disk device with fixed head - Google Patents

Abstract

PURPOSE:To prevent an interruption of operation of an information processing system, by writing the information same as that of a fixed head part into an unused track of a mobile head and then reading this information in case the information of the fixed head is destructed. CONSTITUTION:An FH address register 3 supplies an address signal 107 and the 1st and the 2nd tag signals 105 and 106 from an upper device when a writing operation is carried out while a switch device 11 has no actuation and therefore no switch signal 125 is delivered. Then the address signal of a fixed head designates the corresponding fixed head from the cylinder number CYL and head number HD within the register 3 and then delivers a selection signal 123. In this case, the signal 107 of the fixed head is also applied to an MH address register 4 at a time, and therefore the head 4 delivers a selection signal 124 after designating a corresponding one of mobile heads 6MH0-MH7 from a head number HD. In such a way, the information of the fixed head part is written with overlap also to the corresponding track of the mobile head corresponding to the fixed head.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic disk device, and more particularly to a magnetic disk device with a fixed head.

In a magnetic disk device with a fixed head (hereinafter referred to as a disk device) in which a fixed head is added to a magnetic disk device, the information written and read by the fixed head (hereinafter referred to as fixed head section information) is generally data that is updated on a daily basis. In many cases, this information is important information such as a program that is read a particularly large number of times in an operating system or an operating system.

Therefore, if the fixed head information is destroyed for some reason, it will become impossible to read important data and programs, and it will be impossible to continue the business processing of the information processing system that uses all of this disk device. Therefore, the impact is extremely large.

No conventional disk device is equipped with any special means to deal with this problem.

An object of the present invention is to propose a solution to the above problem, and in order to keep the total file capacity of a disk device constant from the perspective of a host device, movable head tracks (fixed head tracks) that are considered unused are The same number as the number of movable heads) is used to write the same information as the fixed head part information, and when the fixed head part information is destroyed, the same information written in the track of this movable head is read out. Accordingly, it is an object of the present invention to provide a highly reliable disk device in which business processing operations of an information processing system are not interrupted.

A magnetic disk device with a fixed head of the present invention receives a write clock signal, a write data signal, and a write gate signal from a host device, and performs all write operations on a designated one of a plurality of fixed heads. A fixed head write drive circuit outputs a drive signal for driving, and a fixed head write drive circuit receives all of the write clock signal, write data signal, and honor code write gate signal from the host device and outputs a drive signal for driving the fixed head. a movable head write drive circuit that outputs a drive signal for writing the one movable head; a switching device that operates in response to a command signal from the host device or manual operation to output a full switching signal; an address signal, a first tag signal, a second tag signal from the device, a ↓ switching signal from the switching device, and a selection signal that designates a predetermined one of the plurality of fixed heads by inputting all of them and a switching circuit; Fixed head address storage 5-4 outputs a read switching command signal that commands the operation of the address conversion circuit and an address conversion command signal that commands the operation of the address conversion circuit. with a movable head address storage circuit.

a fixed head read amplification circuit that receives all read gate signals from the host device, amplifies a read signal of a predetermined one of the plurality of fixed heads, and outputs a fixed head read amplification signal;

a movable head read amplification circuit that receives the read gate signal from the host device, amplifies the read signal of a predetermined one of the plurality of movable heads, and outputs the entire movable head read amplified signal; the address conversion circuit inputting all of the address signal and the first tag signal from the host device, inputting all of the address conversion command signals from the fixed head address storage circuit, and outputting the positioning command signal to the positioning control circuit; The switching unit outputs either the fixed head read amplified signal or the movable head read amplified signal by combining the fixed head read amplified signal, the movable head read amplified signal, and the continuous output switching command signal. and a circuit.

6- The present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, which shows one embodiment of the invention.

Fixed head write drive circuit* (hereinafter referred to as PH driver)
1 and a movable head write drive circuit (hereinafter referred to as MH driver) 2 both receive a write clock signal 101.1 from a host device (not shown). A write data signal 102 and a write gate signal 103Th are input to drive the fixed head 5 (indicated by FHa-FHp in FIG. 1) or the movable head 6 (indicated by iMHO to MHy in FIG. 1), respectively. Drive signal 121 or 122L-
Output.

On the other hand, an address signal 107. Fixed head address storage circuit (hereinafter referred to as FH address register) that inputs the tag signal 105 and the second tag signal gold.
3 and address signal 107 and second tag signal 106
1" input movable head address storage circuit (hereinafter referred to as MH address register) 4 selects and specifies one fixed head or movable head designated by address signal 107 from fixed head 5 or movable head 6, respectively. Selection signal 123 or 124? is output.

PH address register 3 is also. When the address signal 107 is input without the switching signal 125 being input from the switching device 11 operated by a command signal from a host device or by manual operation, the read switching command signal 112 'fr is output, and when the address signal 107 is input. Address conversion command signal Ill? Output.

The address conversion circuit 7 receives an address signal 107 from the host device.
and the first tag signal 105 are input, and furthermore, the address conversion command signal 111' from the FH address register 3 is manually converted to the cylinder number of the fixed head address of the address signal 107 to the cylinder number of the corresponding movable head address. This is output to the entire positioning control circuit 8.

Fixed head read amplifier circuit (hereinafter referred to as FH amplifier circuit)
9 and a movable head read amplification circuit (hereinafter referred to as MH amplification circuit) 10 are read signals 130 from the fixed head 5 or movable head 6 designated by the selection signal 123 or 124, respectively.
Or input 131 and read out gate signal 104 from the host device. Input all readout signals 130 or 1.
The amplified signal 127 or 128 is outputted to the switching circuit 12.

The switching circuit W & 12 is connected to the FH amplifier circuit 9 and the MH amplifier circuit l.
input to amplified signals 127 and 128 from
When the input is large, the amplified signal 127' is output to the discrimination circuit (not shown), and the read switching command signal 112'? from the FH address register 3 is output. When not input, the amplified signal 128' is output to the discrimination circuit.

Next, the operation of the disk device configured as described above will be explained.

First, a case will be described in which the entire write operation is performed in a state where the switching device 11 is not operating and therefore the switching signal 125 is not output (see FIG. 4).

FH address register 3 receives p address signal 1 from the host device
07, the first tag signal 105, and the second tag signal 106, the address signals of the fixed heads (an example of an address conversion table is shown in FIG. 3) become the address signals of the individual fixed heads a, b, . Hypothetical cylinder numbers (CYL) t, t-1-1, .・And the head number (HD) of the corresponding movable head O, 1,...
, 7, the above cylinder number (CYL) is stored in the FH address register 3.
and the corresponding fixed head from the head number (HD) (for example, if the fixed head address is cylinder number t and head number 0, the corresponding fixed head is a)? It is specified and output to the selection signal 123. At this time, the fixed head address signal 107 is simultaneously input to the MH address register 4, so the MH address register 4 receives the second tag signal 107.
6't- When manually operated, move the movable head 6 (MH) from its head number (HD).

~MH7), specify the corresponding Nll and select the selection signal 1.
Output to 24. (For example, if the fixed head is a-10-, the head number of the corresponding movable head A is 0, so a selection signal designating the movable head MHo2 is output.) On the other hand, the FH address register 3 receives the address signal 107 and Since the first tag signal 105 is input and the address conversion command signal 111k is sent to the address conversion circuit 7, the address conversion circuit 7 receives the fixed head cylinder number (t, t-1-1, . . . ) in the address signal 107. )? 110 positioning command signals converted into cylinder numbers (0, 1, . . . ) of the corresponding movable head are sent to the positioning control circuit 8. (For example, if the fixed head is a, its cylinder number t
2 Convert to the cylinder number 0 of the corresponding movable head A.

) Next, the write gate signal 103 is the write clock signal 1
When inputted to FH driver 1 and MH driver 2 together with 01 and write data signal 102, PH driver 1 and MH driver 2 send driving fN numbers 121 and 122 to fixed head 5 and movable head 6, respectively.

Since the write gate signal lO3 is also input to the positioning control circuit 8 at the same time, the positioning control circuit 8 controls the positioning device (not shown) of the designated cylinder according to the cylinder number designation of the positioning command signal 110 input earlier. When the positioning operation is completed, the fixed head and movable head previously specified by the selection signals 123 and 124 perform the entire write operation by the drive signals 121 and 122 from the FH driver 1 and the MH driver 2, and write. The write operation is ended by stopping the transmission of the gate signal 103.

In this way, the fixed head section information is stored in the corresponding track of the fixed head as well as the corresponding track of the movable head corresponding to the fixed head (when the fixed head is used, this track is used to store the entire storage capacity from the perspective of the host device). This is also a track that is normally left unused for use as a backup track.

Note that in the above operation, if the address signal 107 is an address signal for a movable head, the address input to the PH address register 3 does not have a corresponding fixed head, so the fixed head is not selected, and only the movable head is selected. Therefore, only a normal writing operation using a movable head is performed.

Next, the reading operation of the fixed head section information written as described above will be explained with reference to the timing chart of FIG.

When the switching device 11 is not operating and therefore the switching signal 125 is not output, when the FH address register 3 inputs the fixed head address signal 107 and the first and second tag signals 105 and 106', the address signal 1 is input.
Since the fixed head specified by the cylinder number and head number of 07 is specified and the corresponding selection signal 123'i is output, the read signal 130 from the specified fixed head among the fixed heads 5 (FHa-PHp) is The FH amplifier circuit 9 receives a read gate signal 104 'i gold input lever read signal 13 from the host device.
The amplified signal 12'1L-0 is output to the switching circuit 12.

On the other hand, of the same address signal 107, the head number is also input to the MH address register 4 to select the corresponding movable head, and at the same time, the cylinder number is input to the address conversion circuit 7, and the cylinder number is input to the FH address register 3.
The address conversion command signal ill inputted from the address conversion command signal ill is converted into the cylinder number of the corresponding movable head and outputted to the positioning control circuit 8 as a positioning command signal 110. As a result, the movable head 6 is positioned at a predetermined cylinder position, and the read signal 131 read from the designated movable head among the movable heads 5 (MHO to MHr) is
The MH amplifier circuit 10 outputs the amplified signal 128 from the host device to the readout gate signal 104 'i gold input lever readout signal 131 to the switching circuit 1.
Output to 2.

As an example of the switching circuit 12 is shown in FIG.
A switching device 1 that manually inputs the amplified signals 127 and 128' and outputs them according to the command of the readout switching command signal 112.
2m and a switch 12tl are provided, and the readout switching command signal 112 is input directly to the switch 12b.
The logic value is fully inverted by the inverter 12c and inputted to the switch 12a. Therefore, the switching circuit 12 normally uses the amplified signal 12
7 is suppressed and only the amplified signal 128 is output as a sound, and when the readout switching command signal 112 is input, the amplified signal 1 is output.
It operates to suppress the output of 28 and output only the amplified signal 127.

Therefore, since the switching circuit 12 to which the amplified signals 127 and 12B are inputted as described above receives the readout switching command signal 112 from the FH address register 3, only the amplified signal 127, that is, only the fixed head readout signal? The fixed head is outputted and the fixed head is successively ejected.

If the fixed head information is destroyed for some reason and cannot be read, the switching device 11Th
It operates and sends a switching signal 1215'eF'H to the address register 3.

When the PH address register 3 receives all of the switching signals 125 and also receives the address signal 107 of the fixed head, the amplified signals 127 and 128 are transferred to the switching circuit 12, similar to the read operation when the switching signal 125 is not input. However, at this time, there is no output of the readout switching command signal 112.

The output of the amplified signal 127 is suppressed and only the amplified signal 128 is output, that is, only the read signal of the movable head? The readout operation of the movable head is performed.

Therefore, by rewriting the information read from the movable head to the fixed head, the destroyed information can be repaired and the read operation from the fixed head can be performed again. When the fixed head part information receives a destructive sound that cannot be repaired, is it the corresponding movable head? By using the fixed head unit to write and read fixed head information, business processing can be continued.

As explained in detail above, by using the magnetic disk device with a fixed head of the present invention, fixed head information is destroyed! , since the same information written twice by the corresponding movable head can be read out,
This has the effect of providing a highly reliable magnetic disk device with a fixed head that does not interrupt all business processing operations of an information processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is an explanatory diagram showing an example of the address translation device used in the embodiment of FIG. 1, and FIG. 4 is a circuit diagram of an example of the switching circuit shown in FIG. FIG. 5 is a timing chart of a read operation when the switching device is in an inoperative state in the embodiment of FIG. 1. In fig. l...PH driver 2 driver, 2...MH driver, 3...F'H address register, 4...
...MH address register, 5...Fixed to ν)" (FHa-PHp). 6...Movable head (MHO to MHr)% 7.
... Address conversion circuit, 8 ... Positioning control circuit, 9 ... FH amplifier circuit, 10 ...
...MH amplifier circuit, 11...Switching device, 8YL
...Cylinder number, HD...Head number. 17- 112 Mi Figure 2 - Takun blind code (1os) Second tagi word code (+ o 6) Atrusui code number (107) CYL HD sales gate signal (1,04) Fixed Sodo helmet sales invitation However

Claims (1)

[Claims] A write clock signal, a write data zero signal, and a write gate signal are input from a host device to a plurality of fixed points.
a fixed head write drive circuit that outputs all drive signals for fully driving a designated fixed head of the nodes; a movable head write drive circuit that outputs the write clock signal and a drive signal for driving the write of the movable head described in the previous section from the host device; A switching device that operates according to a command signal from the host device or a manual operation and outputs a full switching signal. An address signal, a first tag signal, and a second tag signal are inputted from the host device, and all switching and isobiki signals are inputted from the switching device to select a predetermined one of the plurality of fixed heads.
A selection signal that specifies the fixed head, a read switching command signal that commands all operations of the switching circuit, an address conversion command signal that commands all operations of the address conversion circuit, and a fixing signal that outputs all outputs.
a movable head that inputs the address signal and the second hand tag signal from the host device and outputs all selection signals designating a predetermined one movable head meeting among the plurality of movable heads; A read gate signal is input from the address storage circuit and the host device to mark the mark. a fixed head read amplification circuit that fully amplifies a read signal of a predetermined one of the plurality of fixed heads and outputs a fixed head read amplified signal sound; a movable head read amplification circuit that inputs the read gate signal ζ~ from the host device, amplifies the read signal of a predetermined one of the plurality of movable heads, and outputs a movable head read amplified signal sound; . and the address conversion circuit receives the address signal, the first tag signal, and sound from the host device, inputs the address conversion command signal from the fixed head address storage circuit, and outputs the positioning command signal to the positioning control circuit. The fixed head successive amplified signal, the movable head read amplified signal, and the read switching command signal are all input to generate either the fixed head read amplified signal or the movable head read amplified signal? and the switching circuit that outputs the output. A magnetic disk device with a fixed head, which is characterized by the following features: