JPS5927355A - Information processing system - Google Patents

Abstract

PURPOSE:To make an operator unnecessary, also to shorten a recovery time, and to improve the rate of operation, by initializing automatically a central processing unit, at the time of a fault, and executing its recovery processing in case of a temporary fault having no reproducibility. CONSTITUTION:When a central processing unit (CPU) 1 becomes faulty and stop its processing operation, a fault signal is sent to a microprocessor 21 through a line 11. As a result, the processor 21 reads out an initializing instruction stored in a control storage 22, sends it to a decoder 24, and supplies a signal of logical ''1'' to an FF 25. The FF 25 sends an initializing signal of logical ''1'' of fixed length to the CPU 1 through a line 13. By this signal, the CPU 1 sets automatically contents of each register, the FF, etc. to an initial value determined in advance. Subsequently, the CPU 1 shifts to an operation of software, the fault recovery processing is executed, and the CPU can be reset to a state before the fault.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly to an information processing system including an automatic initialization function of a central processing unit.

A failure in the central processing unit, which is the core of an information processing system, has a fatal effect on the system, and therefore, increasing the reliability of the central processing unit and shortening the failure recovery time are becoming increasingly important issues. .

There are two types of failures: those that are fixed and reproducible, and those that are temporarily non-reproducible, and it is said that the latter are more likely to occur during actual operation than the former.

The latter failure is not reproducible, so by initializing the central processing unit again, starting the software execution, and performing failure recovery processing using the software, the information processing system will be restored to its pre-failure state and return to correct operation. There is a high possibility that it will.

In conventional information processing systems, when a failure occurs in the central processing unit, the operator recognizes the failure by displaying a lamp, etc., and operates the service processor to check various registers and flip-flops in the central processing unit in order to analyze the failure. After collecting the contents of the files, etc., press the initial setting button to supply the initial setting signal to the central processing unit, perform the initial setting of the central processing unit, and then perform the above recovery process. are dealing with. That is, the conventional method requires the intervention of an operator, and therefore has the disadvantage that it takes a long time to recover from the disturbance.

The purpose of the present invention is to provide an information processing system that eliminates the above-mentioned drawbacks of conventional systems, does not require an operator, significantly shortens the recovery time in the event of a temporary failure, and improves the operating rate. be.

The system of the present invention includes a central processing unit that generates a failure signal when a failure occurs in the central processing unit, receives an initial setting signal, performs initial settings, and performs processing from the beginning; initialization supply means for operating in response to a fault signal and providing an initialization signal to the central processing unit.

The system of the present invention also includes one or more central processing units that generate a failure signal when a central processing unit has a failure, perform initial settings in response to supply of an initial setting signal, and perform processing from the beginning; A first signal is provided corresponding to each of the processing units, operates in response to the fault signal supplied from each central processing unit, and generates a first signal, and then initializes the central processing unit in response to a signal in the memory 2. a first signal supply means for supplying a setting signal; and a first signal supply means for supplying the first signal in response to each first signal supplied from the signal supply means of each building 1; a second supplying a second signal;
and signal supply means.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first invention.

An embodiment of the first invention is comprised of a central processing unit 1 and an initialization signal generation circuit 2 that generates an initialization signal for automatically initializing the central processing unit. The initial setting signal generation circuit 2 includes a control memory 22 that stores a microprogram for generating an initial setting signal, and a microprocessor 21 that executes the microprogram read from the control memory 22.
a temporary memory 23 for temporarily storing data; a decoder 24 for decoding the signal supplied from the microprocessor 21 and generating a predetermined control signal; 7 lip-flop 25 which generates an initialization signal of ``.''.

Next, the operation of an embodiment of the first invention will be described.

When the central processing unit 1 stops processing operations due to a fault, the central processing unit 1 supplies a fault signal to the microprocessor 21 via the connection line 11. The microprocessor 21 receives the above-mentioned fault signal as an interrupt signal, and in response to the reception of this signal, reads out and executes the microprogram for generating the initial setting signal stored in the control memory 22.

That is, when it is necessary for failure analysis, the technology disclosed in Japanese Patent Application No. 179359/1983 can be applied to the microprocessor 21 in the central processing unit 1. Then microprocessor 2
1 reads the initial setting command stored in the control memory 22 and supplies it to the decoder 24, which decodes it and supplies a logic "1" signal to the flip-flop 25. logic 9
In response to the supply of the D signal, an initialization signal of a certain length of logic °°1" is supplied to the central processing unit 1 via the connection line 13. This initialization signal is used in the conventional system for initialization by the operator. The central processing unit 1 is caused to perform initial settings in the same manner as the initial settings using the initial setting signal supplied by pressing a button.In other words, the contents of each register, flip-flop, etc. are set to predetermined initial values, and the central processing unit 1 is A microprogram is loaded into the control memory in the device 1 and its execution is instructed.

By performing the above operations, the central processing unit 1 is automatically initialized. If the failure is temporary and not reproducible, the central processing unit 1 shifts to software operation and the software performs failure recovery processing to restore the information processing system to the state before the failure. The process that was being performed can be continued. In this way, in the event of a temporary, non-reproducible failure, initial settings and recovery processing are automatically performed without operator intervention, making it possible to significantly shorten the recovery time in the event of a failure.

Each device, such as the central processing unit and peripheral device control unit that makes up a large-scale information processing system, has its own built-in fault diagnosis function to improve system reliability and shorten fault recovery time. There is a service processor that oversees the maintenance functions of each device in the system.
This is how maintenance is often managed. In such an information processing system, when collecting the contents of each register, flip-flop, etc. in the device that caused the failure at the time of a failure, the information is collected using the failure diagnosis function of each device as an intermediary based on instructions from the service processor. The data is stored in the memory of the service processor.

The second invention is used in the above information processing system, and FIG. 2 is a block diagram showing one embodiment thereof.

An embodiment of the second invention comprises a central processing unit 1, an initial setting signal generation circuit 3, and an initial setting signal generation circuit control section 4.

The initial setting signal generation circuit 3 includes a control memory 32 that stores a microprogram for generating an initial setting signal, a microprocessor 31 that executes a microprogram read from the control memory 32, and signals supplied from the microprocessor 31. a decoder 34 that decodes and generates a predetermined control signal; a flip-flop 35 that receives the control signal and generates a logic II I 11 initialization signal for a predetermined time; and an initialization signal generation circuit control section 4.
An interface control circuit 36 that exchanges data with
It usually serves to collect and diagnose information necessary for analyzing failures within the central processing unit 1.

The initialization signal generation circuit control unit 4 includes a control memory 42 that stores a microprogram for controlling the initialization signal generation circuit, a microprocessor 41 that executes a microprogram read from the control memory 42, and a temporary memory that temporarily stores data. It includes a memory 43 and an interface control circuit 46 that exchanges data with the initial setting signal generating circuit 3, and normally performs the same functions as those related to the initial setting signal generating circuit 3 and other central processing units. It plays a role of instructing the circuits and peripheral control devices in the system to collect information necessary for failure analysis and to execute diagnostic operations.

Next, the operation of an embodiment of the second invention will be explained.

When the central processing unit 1 stops multi-processing operations due to a fault, the central processing unit 1 supplies a fault signal to the microprocessor 31 via the connection line 14. The microprocessor 31 receives the above-mentioned fault signal as an interrupt signal, and in response to reception of this signal reads and executes a microprogram for generating an initial setting signal stored in the control memory 32.

First, the microprocessor 31 supplies a failure notification signal to the initial setting signal generation circuit control section 4 via the interface control circuit 36 and the connection line 17. The fault notification signal is supplied to the microprocessor 41 via the interface control circuit 46 and causes the microprocessor 41 to generate an interrupt. In response to this interrupt, the microprocessor 41 reads and executes a microprogram for controlling the initial setting signal generation circuit stored in the control memory 42. That is, when necessary for failure analysis, various registers, flip-flops, etc. in the central processing unit 1 are individually specified, and the contents necessary for failure analysis at the time of the failure are collected, and the initial setting signal generation circuit control unit 4 A command is supplied to the initial setting signal generating circuit 3 via the interface control circuit 46 and the connecting line 17 so as to supply the command to the initial setting signal generating circuit 3. The microprocessor 31 receives the instruction via the interface control circuit 36, decodes it, stores it in the control memory 32, and uses the microprogram to write the register or flip-flop of the circuit designated by the instruction of the central processing unit 1. The contents of the file are read and supplied to the initial setting signal generation circuit control section 4 via the interface control circuit 36. The microprocessor 41 stores the content in the temporary memory 43, and then specifies a register or a 7-lip-flop in another circuit in the central processing unit 1 and instructs the initialization signal generation circuit 3 to collect the content. emanate.

Reversing this operation, the initial setting signal generation circuit control unit 4 controls the initial setting signal generation circuit 3 to temporarily store the contents of all necessary registers, flip-flops, etc. in the central processing unit 1 in the event of a failure. It is stored in the memory 43. When this operation is completed, the microprocessor 41 sends the initial setting command to the connection line 1 via the interface control circuit 46 according to the microprogram stored in the control memory 42.
7 to the initial setting signal generation circuit 3. Microprocessor 31 receives initialization instructions via interface control circuit 36 . Thereafter, the microprocessor 31 decodes the initialization command and controls the decoder 34 to provide a logic °°1'' signal to the flip-flop 35.
In response to the supply of the logic "1" signal from the central processing unit 1, a fixed length logic "1" initialization signal is supplied to the central processing unit 1 via the connection line 16. The subsequent operation is similar to that of the first embodiment of the invention described above, and the central processing unit 1
is automatically initialized and recovery processing is performed.

In this way, even if a large-scale information processing system has a service processor and the central processing unit has a built-in failure diagnosis function, in the event of a temporary and irreproducible failure, the central processing You can initialize the device and perform recovery processing. The embodiment of the second invention is a case in which the initial setting signal generation circuit control section controls one initial setting signal generation circuit, but the second invention is not limited to this, and the information processing system includes a plurality of central processing units. Of course, the present invention can also be applied to the case where a plurality of initial setting signal generation circuits including the above are controlled by one control section in a time-sharing manner.

As described above, in both the first invention and the second invention, the central processing unit is automatically initialized in the event of a failure, and recovery processing is performed in the case of a temporary, irreproducible failure. This has the effect of not requiring personnel, significantly shortening recovery time, and improving the operating rate of the information processing system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the first invention, and FIG. 2 is a block diagram of an embodiment of the second invention. In the figure, 1... central processing unit, 2, 3...
...Initial setting signal generation circuit, 4...Initial setting signal generation circuit control section, 21, 31.41...
Microprocessor, 22,32.42・Old・Control memory, 23°43・・Temporary memory, 24.34・・
...Decoder, 25°35...7 lip-flop, 36.46 River...Interface control circuit. Live/Kunisaki? mouth

Claims (2)

[Claims] (1) A central processing unit that generates a failure signal when the central processing unit has a failure, receives the initial setting signal, performs initial settings, and performs the process from the beginning, and the failure signal supplied from the central processing unit. An information processing system comprising: initial setting supply means that operates in response and supplies an initial setting signal to the central processing unit. (2) Generates a failure signal when the central processing unit has a failure, receives the initial setting signal, performs initial settings, and performs processing from the beginning to one or more central processing units and each of the central processing units. correspondingly provided and actuated in response to the fault signal supplied from each of the central processing units to generate a first signal and supplying an initialization signal to the central processing unit in response to the signal of the rear memory 2; a first signal supply means; and a second signal is supplied to the first signal supply means that supplied the first signal in response to each first signal supplied from the signal supply means of each of the buildings 1. and second signal supply means for supplying the information.