JPS5923624A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a high-speed, parallel-system linear or nonlinear A/D converter, by using plural C/MIS inverters which have different logical discrimination levels. CONSTITUTION:The C/MIS inverters which have mutually different logical discrimination levels consist of two complementary MIS inverters A and B. Plural composite complementary inverters 11, 12-1n having different logical discrimination levels are connected to an analog input Vi in parallel. The respective inverters discriminate the input on the basis of their logical discrimination levels to output 0 or 1. Those outputs are inputted to and coded by an encoder 3. Further, linear or nonlinear characteristics are obtained according to whether differences between the logical discrimination levels are uniform or not. Thus, the high-speed, parallel-system linear or nonlinear A/D converter is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed signal processing circuit, and particularly to a signal processing circuit suitable for being configured as an MIS integrated circuit.

In recent years, high-speed A from IMHz to 20MHz has been used for image signal processing, etc.
/D converters are increasingly required.

Moreover, since it is constructed as an integrated circuit or as a part of an integrated circuit, it must occupy a small chip area and consume low power. A successive approximation method can be considered as a high-speed A/D converter, but a clock of at least the number of bits corresponding to the precision is required to quantize one sample of an analog signal. In contrast to ξ, the direct conversion type parallel type d converter performs instantaneous conversion and is therefore the most suitable system for high-speed applications. In this system, a plurality of comparators, the number of which is determined by the required resolution, are connected in parallel to the analog input, and the reference voltage of each comparator is usually divided and supplied from a DC power supply by a resistor string. The output of the comparator is converted into a code by an encoder (encoding device) and output. The most problematic aspect of this method is the comparator. If a differential type comparator is made of an MO8 type semiconductor device, the input offset voltage will be considerably larger than that of a bipolar type, and some countermeasure will be required. Furthermore, since the structure is complicated, the frequency characteristics are inferior. Another disadvantage is that the resistor string providing the reference voltage also occupies a considerable area.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a new high-speed parallel type linear or nonlinear A/D converter.

The A/D converter of the present invention includes a plurality of C/MIS (complementary insulated gate type) inverters having asymmetric input/output characteristics with different logic discrimination levels and to which analog inputs are input in parallel; and an encoder that encodes the output of.

The present invention will be described in detail below with reference to the drawings. FIG. 1(a) shows one embodiment of an inverter used in the A/D converter of the present invention. An inverter (hereinafter referred to as MIS) consisting of complementary MisFETs with different logic identification levels.
Since it is still difficult to manufacture an inverter (called an inverter) with a single structure due to manufacturing and yield issues, two complementary types of MI
The S inverters A and B are combined, and the p-type and n-type transistors have a parallel structure of two MIS FETs. Further, depending on the case, only one of the p-type and n-type may be arranged in parallel. As for the characteristics of these composite MIS FETs, for example, by adjusting the gate threshold value or mutual conductance gm for each inverter, the logic discrimination level as a composite complementary inverter can be set to a predetermined value. Since it has a composite structure, the logical identification level can be arbitrarily selected by combining MIS FETs with different characteristics.

FIG. 1(b) shows an A/D converter that is an embodiment of the present invention. The plurality of composite complementary inverters 11, 1□, . . FIG. 2 shows the input/output characteristics of each inverter; the Vi-Vo characteristics. Here, Vi is the input voltage and Vo is the output voltage. V because each has different input and output characteristics. The operating point voltage at the intersection with the =Vi line is different. Input voltage V, , V2 in the figure
．． ... is the logical identification level. When the input exceeds this logic discrimination level, the inverter exhibits the logic level of I'Oj'. In this way, the output of each inverter becomes +101+ or 1 "1" depending on the amplitude of the analog input. If this output is encoded by the encoder 2, A/D conversion can be performed.

This logical identification level is changed by the following two means. Each MIS that is a component of the composite complementary MIS inverter 1
The two methods are to change the gate threshold voltage VT of the FET and to change the mutual conductance ratio β of the p-type and n-type MIS FETs.

The first method is to calculate the threshold value VT of the MIS FET using the following formula, where φMS ``Metal-silicon work function difference COX
: = Gate oxide film capacitance Q88 = Surface state charge density φF = Fermi level N of substrate = Impurity concentration of substrate? = electron charge amount εoX - given by the dielectric constant of the oxide film, so by changing the impurity concentration of the substrate using techniques such as ion implantation, φ2. By changing N, the gate threshold value vT of each MISFET in the integrated circuit can be arbitrarily set.

The second means is to vary the mutual conductance ratio β of the p-type and n-type FETs of this inverter. β,
Since the slope of the transition region of the input/output characteristics changes due to
By using this means in combination with the first means, it is possible to set the logic discrimination level more finely. Since the transconductance depends on the width and length of the channel, the electrode dimensions can be trimmed. Theoretically, a plurality of different gate threshold values VT can be created in stages by increasing the number of ion implantations, but the process cost is high. Also F
Even if you try to adjust the FET transconductance to a larger value just by increasing the ET channel width, the FE
This is not practical because the area of T becomes large and the gate capacitance also increases. Therefore, it is practical to combine the two means and adjust the logic identification level as an inverter by combining FETs with different gate thresholds and adjusting the mutual conductance ratio of the composite FETs.

The above means are carried out during the manufacturing process of the product circuit, but as a third means, it is possible to apply a reverse voltage VH8 (back gate voltage) between the substrate and the source by external means. If a configuration is adopted, φ in equation (1) becomes substantially (φ2+VBS), and the gate threshold voltage VT
It is also possible to change the logical identification level as an inverter.

As detailed above, the A/D converter according to the present invention separately sets the logic identification level of a plurality of complementary MIS inverters that operate at low power.2. Since it is connected in parallel to the analog input, a complicated comparator required in a conventional A/D converter is removed, and the simplest and most highly integrated circuit can be constructed. The complementary MIS inverter uses low power and has good high frequency characteristics, so it can achieve high speed A.
Suitable for integration as a /D converter.

However, the above structure can be practically easily realized with a composite structure. In this configuration, while reducing the size of the FET, complementary FET
If both the p-type and n-type are made depletion type, they can be used with high mutual conductance, so that it is possible to further reduce the size and speed of the integrated circuit. This violates the condition that both transistors have an enhancement type configuration, which was a prerequisite for C/MOS designers in the past, but it is particularly effective in expanding the input operating range and increasing high-speed response. Further, according to this configuration, it is possible to design nonlinear A/D conversion at the same time, and it is particularly effective for use in gamma correction of liquid crystal televisions and the like or characteristic correction of various sensors.

[Brief explanation of the drawing]

FIG. 1(a) shows a composite complementary form MI which is an embodiment of the present invention.
A diagram showing an S inverter, FIG. 1(b) is a configuration diagram of an A/D converter that is an embodiment of the present invention, and FIG. 2 shows input/output characteristics of a plurality of inverters with different logic discrimination levels. It is a diagram. 1.11,12. ...+11...Compound complementary MIS
Inverter, 2...encoder. Patent applicant Citizen Watch Co., Ltd.

Claims (1)

[Claims] 1. Complementary MIS in which analog inputs are input in parallel
A signal processing circuit comprising a plurality of C/MIS inverters made of FETs and having asymmetric input/output characteristics with different logic discrimination levels, and an encoder that encodes the output of the inverters. 2. The signal processing circuit according to claim 1, wherein the logic discrimination level is adjusted by adjusting the channel length and channel width of the MISFET to make them different. 3. The signal processing circuit according to claim 1, wherein the logic discrimination level is adjusted by varying the impurity concentration of the substrate of the MIS FET. 4 n-type or n in the complementary MIS FET
2. The signal processing circuit according to claim 1, wherein at least one of each of the FETs has a plurality of FETs with different gate thresholds connected in parallel. 5. The signal processing circuit according to claim 4, wherein the n-type complementary MIS FET and each of the n-type FETs have mutual conductance ratios different from each other. 6. The logic discrimination level of the inverter is adjusted by applying a back gate voltage from the outside to the substrate of the n-type or each n-type FET of the complementary MIS FET, and The signal processing circuit according to item 5.