JPS592329A - Manufacture of substrate of semiconductor integrated circuit - Google Patents
Manufacture of substrate of semiconductor integrated circuitInfo
- Publication number
- JPS592329A JPS592329A JP11059882A JP11059882A JPS592329A JP S592329 A JPS592329 A JP S592329A JP 11059882 A JP11059882 A JP 11059882A JP 11059882 A JP11059882 A JP 11059882A JP S592329 A JPS592329 A JP S592329A
- Authority
- JP
- Japan
- Prior art keywords
- film
- integrated circuit
- solder
- semiconductor integrated
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 title claims description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 239000007769 metal material Substances 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 2
- 230000007704 transition Effects 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 230000004927 fusion Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010549 co-Evaporation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体集積回路素子をフェイスダウン法によ
り回路基板に接続する方法に関し、特にはんだ接続部の
形状の制御に好適な半導体集積回路基板の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for connecting a semiconductor integrated circuit element to a circuit board by a face-down method, and more particularly to a method for manufacturing a semiconductor integrated circuit board suitable for controlling the shape of solder joints.
一般に、ＬＳＩ等の半導体集積回路を囲路基板上に高密
度に実装するための方法として、フリップチップボンデ
ィングの一種であるはんだ溶融接続法がある。以下、第
１図、第２図及び第３図によりはんだ溶融接続法と、は
んだ接続部の形状について説明する。Generally, as a method for mounting semiconductor integrated circuits such as LSIs on an enclosure board at high density, there is a solder melt connection method, which is a type of flip chip bonding. Hereinafter, the solder fusion connection method and the shape of the solder joint will be explained with reference to FIGS. 1, 2, and 3.
第１図、第２図及び第３図において、 Ｉｔま乗積回路
素子、２ははんだ接続部、３は絶縁基板、４は端子、５
はボイドである。1, 2, and 3, it is a multiplication circuit element, 2 is a solder connection, 3 is an insulating substrate, 4 is a terminal, and 5
is a void.
はんだ溶融接続法は、第１図に示すように、アルミナセ
ラミック等の材料で構成された絶縁基板３上に形成され
た端子４と集積回路素子１とをはんだ接続部２により接
続して半導体集積回路装置を構成するもので、集積回路
素子ｌの接続端子と絶縁基板３上の配線パターンの接続
端子を対向させて接続できるため半導体集積回路装置を
小型に構成することができるという利点があり、広く用
いられている。このように構成された牛導体集積回路装
置は、その使用にあたって、半導体集積回路素子１等の
発熱により、熱サイクルが加えられることになる。この
結果、牛導体＃！積回路素子１を構成するシリコンと、
絶縁基板３を構成″ｆ′るアルミナセラミックとの間の
熱膨張率のちがいにより、はんだ接続部２に歪サイクル
が加わって、はんだ接続部２は、疲労破壊を起すことに
なる。この熱サイクルに起因″ｆろ熱疲労寿命は、はん
だ接続部２の形状や、絶縁基板３−Ｅに形成された端子
４のはんだぬれ性に大きく影響される。すなわち、はん
だ接続部２は、第２図に示すようＫ、端子４の寸法によ
り種々の形状を有する岬のとなり、また、端子４のはん
だぬれ性が悪い場合、第３図に示すように、はんだ接続
部２内の端子４に接する部分にボイド５が生じ、端子４
とはんだ接続部２間の接触面積が減少し、その接着強度
が低下′Ｖ′る。As shown in FIG. 1, the solder fusion bonding method connects terminals 4 formed on an insulating substrate 3 made of a material such as alumina ceramic and an integrated circuit element 1 through solder connections 2 to form a semiconductor integrated circuit. It constitutes a circuit device, and has the advantage that the connecting terminal of the integrated circuit element l and the connecting terminal of the wiring pattern on the insulating substrate 3 can be connected facing each other, so that the semiconductor integrated circuit device can be configured in a small size. Widely used. When the conductor integrated circuit device configured in this manner is used, it is subjected to a thermal cycle due to the heat generated by the semiconductor integrated circuit element 1 and the like. As a result, cow conductor #! Silicon constituting the integrated circuit element 1;
Due to the difference in thermal expansion coefficient between the alumina ceramic and the alumina ceramic constituting the insulating substrate 3, a strain cycle is applied to the solder joint 2, causing fatigue failure of the solder joint 2.This thermal cycle The thermal fatigue life due to ``f'' is greatly influenced by the shape of the solder joint 2 and the solder wettability of the terminal 4 formed on the insulating substrate 3-E. That is, the solder connection part 2 is a cape having various shapes depending on the dimensions of the terminal 4, as shown in FIG. 2, and if the solderability of the terminal 4 is poor, as shown in FIG. A void 5 occurs in the part of the solder joint 2 that contacts the terminal 4, and the terminal 4
The contact area between the solder joint 2 and the solder joint 2 is reduced, and the adhesive strength thereof is reduced.
そして、前述の熱疲労寿命は、このような、はんだ接続
部２の最悪形状のものにおける寿命で決定され、半導体
集積回路装置の信頼性を向上ｆることか難しかった◇
前述したはんだ溶融接続法の問題点を解決するための方
法として知られている従来技術による中導体集麺回路基
板の製造方法について、以下図面により説明する。The above-mentioned thermal fatigue life is determined by the life of the worst-shaped solder joint 2, and it has been difficult to improve the reliability of semiconductor integrated circuit devices. A method for manufacturing a medium conductor integrated circuit board according to the prior art, which is known as a method for solving the above problems, will be described below with reference to the drawings.
第４図、第５図及び第６図は従来技術により構成された
半導体集積回路基板の断面図を示すものである。第４図
、第５図及び第６図ＶＣおいて ６は配線パターン、７
は付着性補助膜、８ ｔｆ、遷移層、９は第１膜、１０
及び１１は第２膜であり、第１図に対応する部分には同
一符号をつけている。FIGS. 4, 5, and 6 show cross-sectional views of semiconductor integrated circuit boards constructed according to the prior art. In Figure 4, Figure 5, and Figure 6 VC, 6 is the wiring pattern, 7
is the adhesion auxiliary film, 8 tf is the transition layer, 9 is the first film, 10
and 11 are a second film, and parts corresponding to those in FIG. 1 are given the same reference numerals.
従来技術による半導体集積回路基板の製造方法の一つは
、第４図に示すように、アルミナセラミックにより構成
される絶縁基板３上に、該絶縁基板３と第２膜９とのい
ずれにも付着性の良い導電性材料であるクローム（以下
Ｏｒと配す。）の付着性補助膜７を形成し、この補助膜
７の上ＫＭ補助膜７よりも導電性の高い材料である銅（
以下Ｃｕと記す。）を蒸着して遷移層８及び第１膜９を
形成し、この第１膜９の上にはんだにぬれにくい材料で
もあるＣｒ１７′）第２Ｎ１０を形成して、補助膜７、
遷移層ｉ１第１膜９、第２膜１０より成る合成膜を構成
し、この合成膜尻一部をフォトエツチングにより除去し
て配線パターン６を形成し、さらに、同様な方法により
配線ぷターン６上の所定部の第２層１０に除去して端子
４を形成するものである。この方法によれば、端子４あ
寸法精度を高くすることができ、また口上の周囲の第２
−１０がダムとして作用するため、菓１図〜第３図で説
明したはんだ溶融接続法により集積回路素子を端子４を
介して接続する場合、端子４と接続されるを丁んだ接続
部の形状を一定の形に保つことができ７）。しかし、第
４図に示す半導体集積回路基板は、端子４のはんだにぬ
れる第１膜９のＣｕの面ム直接表面に出ているため、端
子４のパｊｌ −ｙを形成後、集積回路素子の接続前に
図宗牛導体集積回路基板が酸化性雰囲気内で熱処理を受
ける場合、端子４の表面が着るしく酸化されてしまう。As shown in FIG. 4, one method of manufacturing a semiconductor integrated circuit board according to the prior art is to deposit a second film 9 on an insulating substrate 3 made of alumina ceramic. An adhesive auxiliary film 7 of chromium (hereinafter referred to as Or), which is a highly conductive material, is formed, and on top of this auxiliary film 7 copper (which is a material with higher conductivity than the KM auxiliary film 7) is formed.
Hereinafter, it will be referred to as Cu. ) is deposited to form a transition layer 8 and a first film 9, and on top of this first film 9, a second N10 (Cr17') which is a material that is difficult to wet with solder is formed to form an auxiliary film 7,
A synthetic film consisting of the first film 9 and the second film 10 of the transition layer i1 is formed, and a portion of the bottom of this synthetic film is removed by photoetching to form the wiring pattern 6. Furthermore, the wiring pattern 6 is formed by the same method. Terminals 4 are formed by removing a predetermined portion of the second layer 10 above. According to this method, it is possible to improve the dimensional accuracy of the terminal 4A, and the second
-10 acts as a dam, so when connecting integrated circuit elements via the terminal 4 by the solder melting method explained in Figs. The shape can be kept constant7). However, in the semiconductor integrated circuit board shown in FIG. 4, since the Cu surface of the first film 9 that is wetted by the solder of the terminal 4 is exposed directly on the surface, after the solder of the terminal 4 is formed, the integrated circuit element is If the conductor integrated circuit board is subjected to heat treatment in an oxidizing atmosphere before connection, the surfaces of the terminals 4 will be severely oxidized.
こめため、従来技−においては、その後に希塩酸処理等
により酸化物を除去しなければならず、工数の増力口や
、歩留りの低下、゛さらには製品である半導体集積回路
装置の信頼性の低下を引起すという欠点があった。Therefore, in the conventional technique, the oxide must be removed by dilute hydrochloric acid treatment, etc., which increases the number of man-hours, reduces the yield, and further reduces the reliability of the semiconductor integrated circuit device that is the product. It had the disadvantage of causing
従来技術による半導体集積回路基板の製造方法のさらに
他の−っとして、特公昭５ａ−１ｃｉ４３０号公軸に開
示されているものがある。この方法を第５図、第６図に
より説明する。第５図において、第１図”ｄ説明したと
同様に、絶縁基板３上に（ｊ ｒｒｊ、、Ｊ：る補助膜
７、遷移層８、Ｃｕ Ｋ Ｌ ルｔＸ ｌ’膳９ｖ形成
し、この第１膜９の上に金（以下Ａｕと記す。）による
第２膜１１を形成して合成膜を構成し、この合成膜の一
部をエツチングにより除去して予定の配−パターン６を
形成し、次に、水素中で加熱することにより、第６図に
示すように、第２“−１゛１を形成す４Ａｕの一部分が
表面拡散によりＣＩにょ名第１Ｍ９の縁部まで覆うよう
にする。 ゛
この方法によれば、端子となるＣｕによる第“１膜９の
面が全てＡｕによる第２膜で覆われているため、半導体
集積回路基板のその後の熱処理工程を経ても：配線パタ
ーン６の端子となる部分は、酸化することなく、良好な
はんだねれ性を得ることができ４）。しかしながら、こ
の方法は、はんだとの接続強度を得るため第１膜９の厚
みを比較的厚くする必要があり、このため、配線パター
ン６ノハターンニング時の寸法精度が比較的良（ないと
いう欠点があった。Still another method of manufacturing a semiconductor integrated circuit board according to the prior art is disclosed in Japanese Patent Publication No. 5A-1CI430. This method will be explained with reference to FIGS. 5 and 6. In FIG. 5, in the same manner as described in FIG. A second film 11 made of gold (hereinafter referred to as Au) is formed on the first film 9 to form a synthetic film, and a part of this synthetic film is removed by etching to form a planned layout pattern 6. Then, by heating in hydrogen, as shown in Fig. 6, a part of 4Au forming No. 2"-1"1 was diffused on the surface to cover the edge of CI No. 1 M9. According to this method, the entire surface of the first film 9 made of Cu, which serves as the terminal, is covered with the second film made of Au, so that even after the subsequent heat treatment process of the semiconductor integrated circuit board, the wiring pattern remains intact. 6), it is possible to obtain good solderability without oxidation 4).However, in this method, the thickness of the first film 9 is relatively small in order to obtain the connection strength with the solder. It is necessary to increase the thickness of the wiring pattern, and as a result, there is a drawback that the dimensional accuracy during turning of the wiring pattern is relatively good (or not).
本発明の目的は、前述した従来技術の欠点を除去し７、
高精度、高品質な半導体集積回路基板を提供することが
でき、接続工程での歩留りを向上して、信頼性の高い半
導体集積回路装置を得ることができろ半導体集積回路基
板の製造方法を提供するにある。The object of the present invention is to eliminate the drawbacks of the prior art mentioned above;
Provides a method for manufacturing a semiconductor integrated circuit board that can provide a high-precision, high-quality semiconductor integrated circuit board, improve the yield in the connection process, and obtain a highly reliable semiconductor integrated circuit device. There is something to do.
この目的を達成す石ため、本発明は、はんだ接続用の端
子表面を酸化防止用の金属材料、例えばＡｕ等の貴金属
や覆い、その後、ハンダ接続部におけるハンダの形状制
御のためのはんだ流れ止め、いわゆるはんだダムとなる
膜を形成するようにした点を特徴とする。To achieve this objective, the present invention covers the surface of a terminal for solder connection with a metal material for preventing oxidation, such as a noble metal such as Au, and then prevents the flow of solder to control the shape of the solder at the solder connection. , is characterized in that it forms a film that becomes a so-called solder dam.
以下、本発明の実施例を図面について説明する。Embodiments of the present invention will be described below with reference to the drawings.
第７図、第８図、第９図は本発明による半導体集積回路
基板の製造方法の一実施例の工程を説明するための半導
体集積回路基板の断面図であって、１２は第３膜であり
、第４図、第５図、第６図に対応する部分には同一符号
をつけている。7, 8, and 9 are cross-sectional views of a semiconductor integrated circuit board for explaining the steps of an embodiment of the method for manufacturing a semiconductor integrated circuit board according to the present invention, and 12 is a third film; 4, 5, and 6 are given the same reference numerals.
次に、この実施例の工程について説明する。Next, the steps of this example will be explained.
まず、第７図において、アルンナセラミックスの絶縁基
板３上に、エレクトロン争ビーム真空蒸着法を用いて、
Ｃｒ１Ｃよる厚さｘｏｏｏＡの付着性補助膜７、Ｃ【と
Ｃｕの同時蒸着により厚さ２０００Ｘの遷移層８、厚さ
１００００ＸのＣｕによる第１膜９、厚さ１５ｏｏＸの
Ａｕによる第２膜１１、厚さ１０００″ＡのＣｒｒｃよ
る第３膜１２を順次形成し、次に、第８図に示すように
、前述のようにして形成された付着性膜７、遷移層８、
第１膜９、第２膜１１、第３膜１２より成る合成膜をフ
ォトエツチングにより所定の部分を除去して配線パター
ン６を形成し、さらに、第９図に示すようπ、配線パタ
ーン６上の所定部分の第３膜・１２をフォトエツチング
ＶＣ，にり除去して端子４を形成するものである。この
ようにして得られた半導体集積回路基板は、第９図に示
すように、端子４の表面が酸化することのないＡ、 ｕ
等による第２膜１１で覆われているため、半導体集積回
路素子を接続する前に熱処理を受けても、端子４が酸化
されることがなく、また、はんだぬれ性が悪くなること
もない。なお、端子４上にはんだ接続部が設けられろと
、第２膜１１のＡｕははんだ内に溶融し、はんだ接続部
と接続端子４内の第１膜９とが強固に接続される。さら
に、半導体集積回路基板は、端子４の周囲にはんだにぬ
れにくいＣｒによる第３膜によってはんだダムが形成さ
れるため、端子４上にはんだ接続部を介して半導体集積
回路を接続する場合の、はんだ接続部の形状を一定の特
定された形状とすることが可能であり、半導体集積回路
素子を接続して得た半導体集積回路装置の信頼性を大幅
に向上させることができる。First, in FIG. 7, on the insulating substrate 3 of Aluna Ceramics, using the electron beam vacuum evaporation method,
An adhesion auxiliary film 7 made of Cr1C with a thickness of xoooA, a transition layer 8 with a thickness of 2000X formed by co-evaporation of C[ and Cu, a first film 9 made of Cu with a thickness of 10000X, a second film 11 made of Au with a thickness of 15ooX, A third film 12 of CrRC having a thickness of 1000"A is sequentially formed, and then, as shown in FIG. 8, the adhesive film 7, transition layer 8, and
A predetermined portion of the composite film consisting of the first film 9, second film 11, and third film 12 is removed by photoetching to form the wiring pattern 6, and further, as shown in FIG. The terminal 4 is formed by removing a predetermined portion of the third film 12 by photoetching (VC). As shown in FIG. 9, the thus obtained semiconductor integrated circuit board has A, u, which prevents the surface of the terminal 4 from being oxidized.
Since the terminals 4 are covered with the second film 11 made of, for example, the second film 11, the terminals 4 will not be oxidized and the solder wettability will not deteriorate even if the terminals 4 are subjected to heat treatment before connecting the semiconductor integrated circuit elements. Note that when a solder connection portion is provided on the terminal 4, the Au of the second film 11 is melted into the solder, and the solder connection portion and the first film 9 in the connection terminal 4 are firmly connected. Furthermore, in the semiconductor integrated circuit board, a solder dam is formed around the terminal 4 by the third film made of Cr, which is difficult to wet with solder. It is possible to make the shape of the solder connection part a certain specified shape, and the reliability of a semiconductor integrated circuit device obtained by connecting semiconductor integrated circuit elements can be greatly improved.
第１０図、第１１図は本発明による半導体集積回路基板
の製造方法の他の実施例の工程を説明するための半導体
集積回路基板の断面図であって、第７図、第８図、第９
図に対応する部分［は同一符号をつけている。10 and 11 are cross-sectional views of a semiconductor integrated circuit board for explaining the steps of another embodiment of the method for manufacturing a semiconductor integrated circuit board according to the present invention, and FIGS. 9
Parts corresponding to the figures are given the same reference numerals.
次に、この実施例の工程について説明する。Next, the steps of this example will be explained.
まず、第１０図において、第７図で説明したＡｕによる
第２膜１１の形成の後、所定の部分をエツチングにより
除去して配線パターン６を形成し、その後全面にわたっ
てＣｒによる第３膜１２を真空蒸着し、さらに、第１１
図に示すように、第３膜１２の配線パターン６の周囲と
配線パターン上の所定の部分を除去して端子４を形成す
るものである。この実施例により得られる半導体集積回
路基板は、前述した第７図乃至第９図により説明した本
発明の実施例による利点に加えて、ｃ「による第３膜１
２が配線パターン６の側面を経て絶縁基板３ＶＣまで達
しているので、配線パターン６がきわめて強固に絶縁基
板３に付着で剖るという特徴を有する。First, in FIG. 10, after forming the second film 11 made of Au as explained in FIG. Vacuum evaporated, and further, the 11th
As shown in the figure, the terminal 4 is formed by removing a predetermined portion of the third film 12 around the wiring pattern 6 and on the wiring pattern. In addition to the advantages of the embodiment of the present invention explained with reference to FIGS. 7 to 9, the semiconductor integrated circuit board obtained by this embodiment has a third film 1 of
2 reaches the insulating substrate 3VC through the side surface of the wiring pattern 6, the wiring pattern 6 has the characteristic of being extremely firmly attached to the insulating substrate 3.
前述した二つの実施例において、はんだダムな形成する
Ｃｒによる第３膜１２は、その材料としてｃｒを用いる
必要げなく、ガラス、有機物等であってもよく、また、
絶縁基板３の材料は、アルミナセラミックばかりでなく
、ガラス有機物行別、無機物材料であってもよい。さら
に付着性補助膜７、遷移層８、第１膜９、第２膜１１の
厚さや材料も、端子４に接続されるはんだ材料に対して
適宜変更することが可能である。In the two embodiments described above, the third film 12 made of Cr formed as a solder dam does not need to use Cr as its material, and may be made of glass, an organic material, etc.
The material of the insulating substrate 3 may be not only alumina ceramic but also a glass organic material or an inorganic material. Furthermore, the thicknesses and materials of the adhesion auxiliary film 7, the transition layer 8, the first film 9, and the second film 11 can be changed as appropriate for the solder material connected to the terminal 4.
以上説明したように、本発明によれば、半導体集積回路
基板の端子の酸化を防止−［ることかでき、また、形成
される全てのはんだ接続部の形状も等しくすることがで
きるから、半導体集積回路素子とのはんだ接続も極めて
良好となり、接続工程での歩留りが向上して信頼性の高
い半導体集積回路装置を得ることができ、上記従来技術
の欠点を除いて優れた機能の半導体集積回路基板の製造
方法を提供することができる。As explained above, according to the present invention, it is possible to prevent the oxidation of the terminals of a semiconductor integrated circuit board, and it is also possible to make the shapes of all solder joints the same, so that the semiconductor The solder connection with the integrated circuit element is also extremely good, the yield in the connection process is improved, and a highly reliable semiconductor integrated circuit device can be obtained, and the semiconductor integrated circuit has excellent functions except for the drawbacks of the above-mentioned conventional technology. A method for manufacturing a substrate can be provided.
第１図、第２図及び第３図は、はんだ溶融接続法の説明
図、第４図、第５図及び第６図は従来技術による半導体
集積回路基板の製造方法を説明するための半導体集積回
路基板の断面図、第７図。
第８図及び第９図は本発明による半導体集積回路基板の
製造方法の一実施例を説明するための半導体集積回路基
板の断面図、第１０図及び第１１図は本発明による半導
体集積回路基板の製造方法の他の実施例を説明”ｆるだ
めの半導体集積回路基板の断面図である。
１・・・・・・集積回路素子、２・・・・・・はんだ接
続部、３・・・・・・絶縁基板、４・・・・・・端子、
５・・・・・・ボイド、６・・・・・・配線パターン、
７・・・・・・付着性補助膜、８・・・・・・遷移層、
９・・・・・・第１膜、１０．１１・・・・・・第２膜
、１２・・・・・・第３膜。
７１ 国
７２昭
１４２
’Ｔ ＳＦＡ
ｆ
才 ６０1, 2, and 3 are explanatory diagrams of the solder fusion bonding method, and FIGS. 4, 5, and 6 are diagrams illustrating the method of manufacturing a semiconductor integrated circuit board according to the prior art. FIG. 7 is a cross-sectional view of the circuit board. 8 and 9 are cross-sectional views of a semiconductor integrated circuit board for explaining an embodiment of the method for manufacturing a semiconductor integrated circuit board according to the present invention, and FIGS. 10 and 11 are cross-sectional views of a semiconductor integrated circuit board according to the present invention. 1 is a sectional view of a semiconductor integrated circuit board for explaining another embodiment of the manufacturing method. 1... integrated circuit element, 2... solder connection part, 3... ...Insulating board, 4...Terminal,
5...Void, 6...Wiring pattern,
7... Adhesive auxiliary film, 8... Transition layer,
9...First film, 10.11...Second film, 12...Third film. 71 Country 72 Show 142 'T SFA f age 60
Claims (1)
る半導体集積回路基板の製造方法において、絶縁基板上
に、はんだぬれ性の良い導電性材料より成る第１膜を形
成し、該第１膜の上に酸化防止用の金属材料より成る第
２膜を形成し、該第２膜の上にはんだにぬれない材料よ
り成る第３膜を形成することにより合成膜を形成する工
程と、販合成膜を選択除去して合成膜より成る配線パタ
ーンを形成する工程と、該配線パターン上の集積回路チ
ップとのはんだ接続に供する部位の前記第３膜を除去す
ることにより接続用の端子を形成する工程とからなるこ
とを特徴とする半導体集積回路基板の製造方法。In a method for manufacturing a semiconductor integrated circuit board having a wiring pattern made of a composite film of a plurality of material films, a first film made of a conductive material with good solderability is formed on an insulating substrate, and a first film made of a conductive material with good solderability is formed on the first film. forming a synthetic film by forming a second film made of a metal material for preventing oxidation, and forming a third film made of a material that cannot be wetted by solder on the second film; a step of selectively removing the third film to form a wiring pattern made of a synthetic film; and a step of forming connection terminals by removing the third film at a portion of the wiring pattern to be used for solder connection with an integrated circuit chip. A method for manufacturing a semiconductor integrated circuit board, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11059882A JPS592329A (en) | 1982-06-29 | 1982-06-29 | Manufacture of substrate of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11059882A JPS592329A (en) | 1982-06-29 | 1982-06-29 | Manufacture of substrate of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS592329A true JPS592329A (en) | 1984-01-07 |
Family
ID=14539907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11059882A Pending JPS592329A (en) | 1982-06-29 | 1982-06-29 | Manufacture of substrate of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS592329A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6374657A (en) * | 1986-09-19 | 1988-04-05 | Hitachi Ltd | Thermal head |
| JPH05121865A (en) * | 1991-10-24 | 1993-05-18 | Sumitomo Kinzoku Ceramics:Kk | Ceramic circuit substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49125847A (en) * | 1973-04-05 | 1974-12-02 |
-
1982
- 1982-06-29 JP JP11059882A patent/JPS592329A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49125847A (en) * | 1973-04-05 | 1974-12-02 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6374657A (en) * | 1986-09-19 | 1988-04-05 | Hitachi Ltd | Thermal head |
| JPH05121865A (en) * | 1991-10-24 | 1993-05-18 | Sumitomo Kinzoku Ceramics:Kk | Ceramic circuit substrate |
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