JPS59229829A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59229829A JPS59229829A JP9121383A JP9121383A JPS59229829A JP S59229829 A JPS59229829 A JP S59229829A JP 9121383 A JP9121383 A JP 9121383A JP 9121383 A JP9121383 A JP 9121383A JP S59229829 A JPS59229829 A JP S59229829A
- Authority
- JP
- Japan
- Prior art keywords
- protection film
- wiring conductor
- aperture
- wafer
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 20
- 230000001681 protective effect Effects 0.000 claims description 17
- 230000006866 deterioration Effects 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 101150006573 PAN1 gene Proteins 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、特に半導体装
置の配線導体におけるポンディングパッド部分の保ｆ［
膜の開口方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, and more particularly, a method for manufacturing a semiconductor device.
This invention relates to a method for opening a membrane.
通常、半導体装置のポンディングパッド（ＰＡＤ）開口
工程は、半導体基板（ウェハ）の裏面をランピング処理
後に行っている。Usually, the process of opening a bonding pad (PAD) of a semiconductor device is performed after the back surface of a semiconductor substrate (wafer) is subjected to a ramping process.
しかしながら、前記パッド開口工程では半導体基板はす
でにラッピング処理を終えているため、その厚さは薄く
軽量となっており、半導体製造装置において半導体基板
をＩＩａガス等の気体を用いて搬送する場合、その搬送
がしにくいだけでなく、半導体基板が薄くなっているた
め機械的強度も弱く、搬送中に破損する等の不都合を生
じる。However, since the semiconductor substrate has already been wrapped in the pad opening process, it is thin and lightweight. Not only is it difficult to transport, but since the semiconductor substrate is thin, its mechanical strength is also weak, leading to problems such as breakage during transport.
また、パッド開口（ＰＡＤ）工程をラッピング処理の後
に行った場合、ラッピング処理で生じた切削粉がパッド
部分に付着し、ボンディングの信頼性を低下させる等の
不都合がある。Furthermore, if the pad opening (PAD) process is performed after the lapping process, there are disadvantages such as cutting dust generated in the lapping process adhering to the pad portion and reducing the reliability of bonding.
この発明は、半導体基板の搬送を容易にするとともに、
その破損等を防止し、ボンディングの信頼性の低下を防
止した半導体装置の製造方法の提供を目的とする。This invention facilitates the transportation of semiconductor substrates, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents damage to the semiconductor device and prevents deterioration in bonding reliability.
この発明は、半導体基板の表面に配線導体を配設し、こ
の配線導体の表面を被う第１及び第２の保護膜を積層し
て形成した後、第２の保護膜の表面にフォトレジスト層
を形成し、このフォトレジスト層及び前記第２の保護膜
に前記配線導体を露出させるための開口を形成し、前記
半導体基板の裏面をラッピング処理した後、第２の保護
膜をマスクにして前記開口に配線導体のボンディング部
を露出させたことを特徴とする。In this invention, a wiring conductor is provided on the surface of a semiconductor substrate, first and second protective films are laminated to cover the surface of the wiring conductor, and then a photoresist is applied to the surface of the second protective film. forming a layer, forming an opening in the photoresist layer and the second protective film to expose the wiring conductor, and lapping the back surface of the semiconductor substrate, using the second protective film as a mask. A bonding portion of a wiring conductor is exposed in the opening.
以下、この発明を図面に示した実施例を参照して詳細に
説明する。Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
図はこの発明の半導体装置の製造方法の実施例を示し、
ＡないしＥはその工程を示している。Ａに示すように、
ウェハ２の表面にはアルミニウム層等からなる配線導体
４が形成されている。この配線導体４の表面には、その
表面及びウェハ２の表面を被う窒化膜（Ｓｉ３Ｎ４）か
らなる第１の保護膜６を形成し、この保護膜６の表面に
は５ｔＯ２層からなる酸化膜で第２の保護膜８を形成す
る。The figure shows an embodiment of the method for manufacturing a semiconductor device of the present invention,
A to E indicate the steps. As shown in A,
A wiring conductor 4 made of an aluminum layer or the like is formed on the surface of the wafer 2. A first protective film 6 made of a nitride film (Si3N4) is formed on the surface of this wiring conductor 4 and covers the surface thereof and the surface of the wafer 2, and an oxide film made of a 5tO2 layer is formed on the surface of this protective film 6. A second protective film 8 is formed.
次に、Ｂに示すように、第２の保護膜８の表面にフォト
レジスト層１０を形成し、Ｃに示すように、バンド部分
にフォトレジスト層１０及び第２の保護膜８に及ぶ開口
１２を形成する。そして、Ｃに破線１４で示すように、
ウェハ２の裏面をラッピング処理をする。Next, as shown in B, a photoresist layer 10 is formed on the surface of the second protective film 8, and as shown in C, an opening 12 is formed in the band portion extending over the photoresist layer 10 and the second protective film 8. form. Then, as shown by the broken line 14 at C,
The back side of the wafer 2 is subjected to lapping processing.
次に、Ｅに示すように、第２の保護膜８をマスクにして
第１の保護膜６にエツチング処理をし、開口１２に配線
導体４を露出させる。Next, as shown in E, the first protective film 6 is etched using the second protective film 8 as a mask to expose the wiring conductor 4 in the opening 12.
このような処理工程によれば、フォトレジスト工程をラ
ンピング処理の前に行っても、パン１部分の開口処理は
ラッピング処理後に行うことができるため、ウェハ２の
破損等を防止でき、半導体基板の搬送が容易になり、し
かも配線導体２のポンディングパッド部の汚染が防止で
き、ボンディングの信頼性の低下を防止できる。According to such processing steps, even if the photoresist process is performed before the ramping process, the opening process for the pan 1 portion can be performed after the lapping process, so damage to the wafer 2 can be prevented and the semiconductor substrate It is possible to facilitate transportation, prevent contamination of the bonding pad portion of the wiring conductor 2, and prevent deterioration in bonding reliability.
以上説明したようにこの発明によれば、半導体基板の搬
送が容易になるとともに、その破損等が防止でき、ボン
ディングの信頼性を高めることができる。As described above, according to the present invention, it is possible to easily transport a semiconductor substrate, prevent damage to the semiconductor substrate, and improve the reliability of bonding.
図はこの発明の半導体装置の製造方法の実施例を示す説
明図である。
２・・・半導体基板、４・・・配線導体、６・・・第１
の保護膜、８・・・第２の保護膜、１０・・・フォトレ
ジスト層、１２・・・開口。
手続補正書動式）
１．事件の表示
昭和５８年特許願第９１２１３号
２、発明の名称
半導体装置の製造方法
３、補正をする者
事件との関係 特許出願人
住 所 京都市右京区西院溝崎町２１番地名称ローム株
式会社
代表者佐藤研一部
４、代理人〒１６７
住 所 東京都杉並区天沼三丁目２番２号荻窪勧業ビル
２階
（発送日：昭和５８年８月園日）
７、補正の内容
（１１明細書第４頁第１７行の「図」を「第１図」に補
正する。
（２） 図面の番号を朱書きした「第１図」のように
補正する。
以上The figure is an explanatory diagram showing an embodiment of the method for manufacturing a semiconductor device of the present invention. 2... Semiconductor substrate, 4... Wiring conductor, 6... First
protective film, 8... second protective film, 10... photoresist layer, 12... opening. Procedural amendment form) 1. Display of the case 1982 Patent Application No. 91213 2 Name of the invention Method for manufacturing semiconductor devices 3 Person making the amendment Relationship to the case Patent applicant Address 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto Name ROHM Co., Ltd. Representative Sato Ken Part 4, Agent 167 Address: 2nd floor, Ogikubo Kangyo Building, 3-2-2 Amanuma, Suginami-ku, Tokyo (Delivery date: August 1988) 7. Contents of amendment (11 Specification No. 4) Correct “Figure” in line 17 of the page to “Figure 1.” (2) Correct it to read “Figure 1” with the drawing number written in red.
Claims (1)
表面を被う第１及び第２の保護膜を積層して形成した後
、第２の保護膜の表面にフォトレジスト層を形成し、こ
のフォトレジスト層及び前記第２の保護膜に前記配線導
体を露出させるための開口を形成し、前記半導体基板の
裏面をラッピング処理した後、第２の保護膜をマスクに
して前記開口に配線導体のボンディング部を露出させた
ことを特徴とする半導体装置の製造方法。A wiring conductor is provided on the surface of the semiconductor substrate, first and second protective films are laminated to cover the surface of the wiring conductor, and then a photoresist layer is formed on the surface of the second protective film. After forming an opening in the photoresist layer and the second protective film to expose the wiring conductor and lapping the back surface of the semiconductor substrate, wiring is formed in the opening using the second protective film as a mask. A method for manufacturing a semiconductor device, characterized in that a bonding portion of a conductor is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9121383A JPS59229829A (en) | 1983-05-23 | 1983-05-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9121383A JPS59229829A (en) | 1983-05-23 | 1983-05-23 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59229829A true JPS59229829A (en) | 1984-12-24 |
| JPH0155579B2 JPH0155579B2 (en) | 1989-11-27 |
Family
ID=14020139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9121383A Granted JPS59229829A (en) | 1983-05-23 | 1983-05-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59229829A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228132A (en) * | 1988-03-08 | 1989-09-12 | Hitachi Ltd | Manufacture of semiconductor device |
| EP0661746A1 (en) * | 1993-07-30 | 1995-07-05 | Texas Instruments Incorporated | Microwave integrated circuit and their fabrication |
| DE102007018854A1 (en) * | 2006-09-15 | 2008-03-27 | Mitsubishi Electric Corp. | Semiconductor device manufacturing method, semiconductor wafer and semiconductor device |
-
1983
- 1983-05-23 JP JP9121383A patent/JPS59229829A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228132A (en) * | 1988-03-08 | 1989-09-12 | Hitachi Ltd | Manufacture of semiconductor device |
| EP0661746A1 (en) * | 1993-07-30 | 1995-07-05 | Texas Instruments Incorporated | Microwave integrated circuit and their fabrication |
| DE102007018854A1 (en) * | 2006-09-15 | 2008-03-27 | Mitsubishi Electric Corp. | Semiconductor device manufacturing method, semiconductor wafer and semiconductor device |
| DE102007018854B4 (en) * | 2006-09-15 | 2008-06-19 | Mitsubishi Electric Corp. | Semiconductor device manufacturing method, semiconductor wafer and semiconductor device |
| US7867829B2 (en) | 2006-09-15 | 2011-01-11 | Mitsubishi Electric Corporation | Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0155579B2 (en) | 1989-11-27 |
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