JPS59226517A - Transistor circuit - Google Patents

Abstract

PURPOSE:To constitute so that a transistor (TR) used for only the purpose of preventing an electrostatic breakdown is useful for a fact that a test is executed at a high speed, as well, by connecting in parallel a TR whose on-resistance is small to a TR whose on-resistance is large, in a buffer circuit of IC. CONSTITUTION:In a usual time (non-test time), an N channel TR (N.TR) 7 and a P channel TR (P.TR) 8 are turned on, and an N.TR 9 and a P.TR 10 are turned off, therefore, an N.TR 3 and a P.TR 2, whose on-resistance is small, used for preventing an electrostatic breakdown are turned off, and an output buffer executes a usual operation by an N.TR 1 and a P.TR 2, whose on- resistance is large. On the other hand, at the time of a test, the N.TR 9 and the P.TR 10 are turned on, and the N.TR 7 and the P.TR 8 are turned off, therefore, as for the output buffer, the N.TR 3 and the P.TR 4, whose on- resistance is small are turned on and off in accordance with a signal IN. Accordingly, a waveform of a signal OUT is varied steeply, therefore, the operation can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output buffer circuit for a semiconductor integrated circuit (hereinafter referred to as IC).

In the output buffer circuit of an IC, a transistor with a large on-resistance is often used in order to reduce power consumption, chip area, and match with external circuits. When testing such an IC, the rise and fall times of the output waveform of Ic are determined by the product (time constant) of the on-resistance of the output buffer transistor of the IC and the capacitance (time constant) that depends on the test equipment, and K.
Therefore it is decided. Therefore, if the on-resistance of the output buffer transistor is large, the output waveform will be distorted, making it impossible to increase the speed of testing. Therefore, the time occupied by the test equipment increases, which becomes a major obstacle to reducing the cost of the IC itself.

On the other hand, in order to prevent electrostatic discharge damage to the IC, it is necessary to reduce the on-resistance of the output buffer transistor so that it functions as a large protection diode. Because of that,
For an output buffer that requires a transistor with a large on-resistance as described above, a transistor with a small on-resistance that is set so that the gate signal is always off must be connected to the output. Therefore, a transistor with a low on-resistance that is always off has the disadvantage that it only serves the function of preventing electrostatic damage, although it occupies a large area within an IC.

The present invention has been made in view of the above-mentioned drawbacks, and the present invention has been made in view of the above-mentioned drawbacks.
In the 77 circuit, a transistor with an on-resistance is placed in parallel with the transistor in the on-resistance hole, and the transistor, which has an on-resistance in normal times, is turned off and used as a function to prevent electrostatic damage. By using the gate signal of the transistor in the on-resistance hole and the gate signal of the transistor in the on-resistance hole as an output buffer for the on-resistance 7), protection against electrostatic discharge damage and speeding up of testing are achieved. It is a feature.

The present invention will be described below with reference to the drawings. FIG. 1 is an example of a conventionally used output 7277 circuit. In the figure, 1 is an N-channel transistor with an on-resistance hole, 2 is a P-channel transistor with an on-resistance hole, 3 is an N-channel transistor with an on-resistance, and 4 is a P-channel transistor with an on-resistance. be. Signal IN is a gate signal for transistors 1 and 2, whose drains are commonly connected to signal OUT. The source of transistor 1 is at negative potential -■, the source of transistor 2 is at ground potential, the gate and source of transistor 4 are at ground potential, and the drain is at the signal (
Each is connected to the JUT.

The output buffer is used, for example, as a key output buffer configured at a high level.

If multiple keys are pressed at the same time, multiple of the above buffers will be short-circuited, but since the on-resistance of the pN channel is smaller than the on-resistance of the P channel, a key manual buffer (not shown) is used.
reads the unconfigured level (low level). Therefore, incorrect key input can be prevented.

However, in this circuit, the transistor 3 is always off and only serves to prevent electrostatic damage.

Therefore, since the on-resistance of the transistor 20 is large, it takes time for the output waveform to reach a high level, and the
Even if the internals can operate at high speed, the speed cannot be increased.

FIG. 2 shows an output buffer circuit according to an embodiment of the present invention, and 1 to 5 are the same as in FIG. 1.

However, in this figure, the gate of transistor 3 is connected to the drains of transistors 7 and 9, which will be described later. Furthermore, the gate of the transistor 4 is a transistor 8j?, which will be described later. and the drains of IO. TES
T is normally (at non-test) “θ” level at test “l” I
There is an I level signal, and 6 is an inverter that uses the signal TF8T12 manually.

Reference numeral 7 denotes an N-channel transistor whose gate is connected to the output signal of the inverter 6 and whose source is connected to the negative potential -2, and whose drain is connected to the gate of the transistor 3 as described above. 8 is a P-channel transistor whose gate is connected to the signal TEST, whose source is connected to the ground potential, and whose drain is connected to the gate of the transistor 4. 9 is an N-channel transistor whose gate is connected to the signal TEST and whose source is connected to the signal IN;
The drain is connected to the gate of transistor 3.

Reference numeral 10 denotes a P-channel transistor whose gate is connected to the output signal of the transistor 6, whose source is connected to the signal IN, and whose drain is connected to the gate of the transistor 4. The operation of this embodiment will be explained below.

First, under normal conditions (non-testing), N-channel transistor 7 and P-channel transistor 8 are turned on, and N-channel transistor 7 and P-channel transistor 8 are turned on.
Since channel transistor 9 and P-channel transistor 1O are turned off, N-channel transistor 3 and P-channel transistor 4, which have on-resistance, are turned off. Therefore, the output buffer is N-channel transistor 1 and P-channel transistor 2 in the on-resistance hole.
Performs normal operation.

Next, during testing, N-channel transistor 9 and P-channel transistor 10 are turned on, and N-channel transistor 7 and P-channel transistor 8 are turned off. Therefore, the output sofa turns on and off not only the N-channel transistor 1 and the P-channel transistor 2 in the on-resistance hole, but also the N-channel transistor 3 and the P-channel transistor 4 in the on-resistance according to the 1@ IN. Therefore, the waveform of the signal OUT abruptly reaches a low level and a low level.

As described above, according to the present invention, it is possible to speed up the entire transistor test, which has heretofore been used only for the purpose of preventing electrostatic discharge damage. Therefore, the cost of test equipment, which is a factor in IC cost, can be completely reduced.

Note that the inverter 6 and transistors 7, 8, 9, and 10, which are newly installed in FIG. It is possible to get away with a slight increase. Further, in the embodiment, a case has been described in which transistors with large on-resistance are used for both N-channel output buffer transistors, but the present invention is also applicable when only one of them is composed of a transistor with an on-resistance hole. Needless to say, in that case, only one of the parallel transistors with on-resistance is required.

[Brief explanation of drawings]

Figure 1 is a conventionally used output buffer circuit diagram, where 1 is a channel transistor in the on-resistance hole, and 2 is a circuit diagram of a conventional output buffer.
is a P-channel transistor with an on-resistance hole, 3 is a channel transistor with an on-resistance, and 4 is a P-channel transistor with an on-resistance.
Channel transistor 5 is an output terminal pad. FIG. 2 is an output buffer circuit diagram of an embodiment of the present invention, in which 6 is an inverter, 7 and 9 are N-channel transistors, and 8.10 is a P-channel transistor.

Claims (1)

[Claims] In a transistor circuit having a transistor with a large on-resistance, a transistor with a small on-resistance is connected in parallel to the transistor with a large on-resistance, and the transistor with a small on-resistance is normally used in the off state, and during testing, the on-resistance is A transistor circuit characterized in that a gate signal of a small transistor and a gate signal of a transistor with a large on-resistance are used in common.