JPS59225573A - Short gate field effect transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To obtain an MESFET having low source resistance and low gate resistance, and having a superior withstand voltage by a method wherein the under part of a gate electrode metal in the neighborhood of the part to come in contact with an active region is formed in narrower width in the gate length direction as compared with the top part, and moreover the under part wall faces of the gate electrode metal are protected by insulating films. CONSTITUTION:The sectional shape of a gate electrode 24 formed on an active region 22 forms a narrow width part narrowed in width in the gate length direction at the under part in the neighborhood of the part to come in contact with the active region 22, the top part is a broad width part making the edge parts to reach a pair of high electron concentration regions 23, and forms nearly a T-shape. The distance between the high electron concentration regions 23 for a source and a drain on both the sides interposing the active region 22 between them is formed sufficiently shorter than size of the top part of the gate electrode 24, and formed longer than size in the gate length direction of the gate electrode at the part of the contact face with the active region 22. Moreover the side wall faces of the under part of the gate electrode 24 are made in structure protected by third insulating films 29 consisting of an Si3N4 film having superior humidity resistance, for example, and moreover, the upper parts of the high electron concentration regions 23 adjoining to the third insulating films 29 thereof are made in structure covered with second insulating films 28 consisting of an SiO2 film.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a Schottky gate field effect transistor and a method for manufacturing the same. The present invention relates to a Schottky gate field effect transistor having a low resistance and an appropriate drain breakdown voltage, and a method for manufacturing the same.

[Technical background of the invention and its problems]

A Schottky gate field effect transistor (hereinafter referred to as ME8FET) using a compound semiconductor material is attracting attention as an ultra-high frequency device having performance that cannot be achieved with 81 materials. MP using GaAs! 8F
ET has already been put into practical use for a long time, and even now GaAsM
Various developments are being carried out to improve the performance of ESFFiT, and recently the development of ultra-high-speed digital ICs and analog ICs using GaAsME8FETs has become active in various places.

Next, the structure of a conventional GaAs M E 8 F 8 T will be explained with reference to FIG.

That is, an active region (2) is formed on a GaAs semi-insulating substrate (1).
A pair of high electron concentration regions (3) are formed, and an active region (2) is formed.
) is a Schottky barrier gate electrode metal (hereinafter referred to as gate electrode) (4), and on the high electron concentration region (3) is a source and drain ohmic electrode metal (hereinafter referred to as source and drain electrode) ( 5) Form (6).

In such a structure, it is important to form a fine gate electrode (4) in order to obtain a high-performance ME8FI (T). Gate electrodes with a length of .25 to 0.3 μm have been fabricated.However, when using the electron beam direct writing method, there are problems such as expensive manufacturing equipment and low throughput, and deep ultraviolet exposure. When using the method, the length of the gate electrode is 0.25 μm to 0.8 μm.
There was a problem in that when trying to form a film with a thickness of .mu.m, the yield rate deteriorated significantly.

Furthermore, MP! In order to improve the performance of 5PIT, it is also important to reduce the parasitic resistance.In particular, to reduce the source resistance, ・The semiconductor layer under the source electrode is formed thickly with high electron concentration, and the The distance between gate electrodes must be shortened. However, this shortening of the distance (=) is normally selected to be about 1 to 2 μm because there is a limit to mask alignment accuracy.

However, recently, various self-alignment methods have been proposed as a method for shortening the distance between the source electrode and the gate electrode to 0.5 μm or less. Figure 2 (Explain in detail.

That is, the active region 14 is first formed on the GaAs semi-insulating substrate.
After that, a gate electrode o4 is formed. Next, using this gate electrode α force as a mask, ion implantation and subsequent annealing are performed to form a high electron concentration region α, and finally, a source electrode (1) and a drazo electrode (11) are formed. According to the method, the effective distance between the source electrode a and the gate electrode I is almost zero, and a very low source resistance can be expected.However, the MESFF3T formed in this way has Since the distance between the source electrodes a9 is almost zero, the drain breakdown voltage is extremely low, making such MESFETs easy to destroy and difficult to obtain large output.Furthermore, the gate electrode α force Normally 800C to 9
It must be able to withstand an annealing temperature of 0.00C, and it is necessary to select a metal plate that has a melting point and can suppress reaction with GaAs as the metal plate for the gate electrode α force. However, metals of the types □ and ′: generally have high resistance and are difficult to microfabricate. Also, since the distance □ between the gate electrode α force and the drain electrode time is zero, the feedback capacitance is large □. 4. a,. ,yo,ga□(i
J Jj +07, ah. 4. MESFET with good microphone four-wave characteristics has not yet been obtained. Also,
In this kind of method, MESFET ””□, t□8,
Yes, □, D. 83. 1. It was difficult to manufacture MISFETs with good yields because of poor adhesion and easy peeling and the effects of high-temperature annealing, which caused variations in the electron concentration in the active region under the gate electrode.

[Purpose of the invention]

The present invention was made in view of the above-mentioned problems, and has low source resistance and gate resistance, a fine gate electrode,
Moreover, it is an object of the present invention to provide a MESFET having a breakdown voltage that causes no problems in practical use, and a method for manufacturing the same.

[Summary of the invention]

In the present invention, an active region and high electron concentration regions located on both sides of the active region J1 are formed on a compound semiconductor substrate, a gate electrode metal is placed on one active region, and a source electrode metal is placed on each high electron concentration region. In a Schottky gate field effect transistor provided with a gate electrode metal and a do/in electrode metal, the lower part near where the gate electrode metal contacts the active region is connected to the upper R11 (
': A Schottky gate field effect transistor characterized in that the gate is formed narrower in the longitudinal direction so that the cross section is shaped like a straight line, and the lower wall surface of the gate electrode metal is protected with an insulating film; This is a method of manufacturing this Schottky gate field effect transistor, particularly a method of manufacturing a gate electrode.

[Embodiments of the invention]

Next, an embodiment of the MPi8FT13T of the present invention will be explained with reference to FIG.

That is, the GaAs semi-insulating substrate υ has an active region 4 formed by ion implantation and a pair of high electron concentration regions on both sides of the active region 123, which are also formed by ion implantation. The cross-sectional shape of the gate electrode (24) formed above this active region (2) is a narrow part where the width becomes narrower in the gate length direction at the lower part near the contact with the active region (24), and at the upper part the end It has a wide portion that reaches a pair of high electron concentration regions (c) and is approximately in the shape of a single letter.

By forming the gate electrode in such a shape, the gate resistance can be lowered. In addition, the distance between the high electron concentration regions (2) for source and drain on both sides of active region 4 is sufficiently shorter than the upper dimension of gate electrode (c), and the distance between the gate electrode and active region 4 is sufficiently shorter than the upper dimension of gate electrode (c). The dimensions at the contact surface in the direction are long. For example, the distance between the source and the gate electrode and the distance between the gate electrode and the drain indicated by the symbol (d) in FIG. 8 are 0.2
The length is controlled to a desired length of about 0.5 μm. Therefore, the source resistance is sufficiently low, the drain breakdown voltage is ensured at a level that does not cause any practical problems, and the parasitic capacitance between the gate and the drain is also suppressed to be lower than in the conventional example shown in FIG. Further, the lower side wall surface of the gate electrode Qa is protected by an eighth insulating film made of, for example, an 8i, N, film having excellent moisture resistance, and the eighth insulating film (
The high electron concentration region (c) adjacent to (to) is covered with a second insulating film made of sio. According to the structure having the eighth insulating film and the second insulating film (2) in this way, the gate electrode can be easily manufactured and the gate electrode can be mechanically deformed. can be prevented.

Furthermore, the third insulating film on the active region (2) is preferably a film with excellent moisture resistance, such as an 8illN4 film, as described above, but this S-type N4 film is not compatible with the GaAs semi-insulating substrate (21). Since the stress at the interface is large, it is preferable to form the area of contact with GaAs as small as possible.

In addition, even if the high electron concentration layer (c) is affected by temperature etc. to some extent, the effect on the characteristics will be the same as #1 (GaAs semi-insulating substrate (the stress in the 2υ field is also small, so the second An S10. film is sufficient as the insulating film.

In addition, the parasitic capacitance via the insulating film (2) between the gate electrode and the source and drain should be small, and for this purpose, it is necessary to increase the thickness of the film and use a material with a small dielectric constant. is desirable. For example, the dielectric constant of 84, N4 film is about 7.8i0. The relative dielectric constant of the film is about 8 to 4, and SiN film tends to crack when it is adhered to a thickness of 810. The membrane can also be as thick as 1 μm.

Next is an example of the manufacturing method! #4 This will be explained using figure 4.

First, as shown in FIG. 4(, ), an active layer (221) is formed on a GaAs semi-insulating substrate Q by a crystal growth method or an ion implantation method.

Next, as shown in FIG. 4(b), for example, a 813N electrode with a dimension of 1 μm and a height of about 5000λ is placed at the position where the gate electrode is to be formed.
, a better first insulating film cl'? ) to form.

Next, as shown in FIG. f4S4 (c), a high electron concentration region (to) is formed by ion implantation using this first insulating film Qη as a mask. As a result, the active region 0 is formed only under the first insulating film (27).

Next, as shown in the fourth frame (d), the first insulating film (27)
A second insulating film (
to). In this case, the second insulating film (c) needs to be formed thinly on the first insulating film (2?);
This can be easily formed, for example, by spin-coding S, io dissolved in a solvent.

Next, as shown in FIG. 4(,), the first insulating film (27) is removed. This first insulation 1lK12? ) to remove
For example, reactive ion etching may be used to utilize the etching rate selectivity between the first insulating film Qη and the second insulating film (to), solution etching, or a combination of ion etching and solution etching. A combination may also be used.

Next, the electron concentration region (2) is annealed in an arsenic atmosphere to activate the ion species. This annealing in an arsenic atmosphere is performed immediately before the step shown in FIG. 4(e), immediately after the ion implantation shown in FIG. 4(c), or at the stage of forming the second insulating film (to) shown in FIG. 4(d). However, as in this example, the
It is desirable to perform annealing in step e). The reason for this is the first insulating film 0'? ) is deposited, this often causes variations in the electron concentration in the active region (2).

However, when annealing is performed in an arsenic atmosphere after removing the first insulating film 07), that is, exposing the active region 04, the electron concentration in the active region C is very stable. Furthermore, if ion etching is employed in the previous step, the GaAs surface may become defective, but this can be eliminated by the annealing process.

Next, as shown in FIG. 4(f), the surface is coated with an eighth insulating film.
Cover with This eighth insulating film (a) is preferably deposited by a plasma formation method. This 8'th insulating film (c) has approximately the same thickness on the surface and wall surface of the second insulating film Q1. In this example, the thickness of the eighth insulating film (c) is 800 mm.
It was set as OA.

Next, as shown in Figure 4(g), 94% of the insulating film (c) is removed by an anisotropic etching method such as reactive ion etching or a combination of ion etching and solution etching. 7. Insulating film of this decontamination 2 (2
) The eighth insulating film c11 on the wall surface can expose the surface of the active region (two sides) without being etched.

Next, after surface treatment of active area 4, as shown in Fig. 4 (h
), the metal film (241) for the get electrode is 1 μm thick.
A-g, AA/Ti, Au/Pi/Ti, etc. can be used as the metal for this metal film (24 m), which is coated with fish debris to a thickness of m.

Next, the upper part of the gate electrode (24) is formed to have a thickness of 8 .mu.m by a conventional mask alignment method using a resist. Next, part or all of the second insulating film (c) is removed to expose a high electron concentration region (c), and a source electrode (c) and a drain electrode (c) are formed in this high magneton concentration region (c). form.

In this case, the source electrode e! The process can be simplified by making the distance between the ends of the gate electrode 9 and the drain electrode (c) coincide with the width of the upper wide part of the gate electrode 04). Further, the eighth insulating film coated on the side surface of the lower narrow part of the gate electrode (24), which has a T-shaped cross section, may be partially or completely removed as necessary. As is clear from the above explanation, in the first step of processing the first insulating film (27), the gate length can be adjusted even if the opening size of the film is about 1 μm, which is a size that can be easily formed by photoetching. is 0.4 μm.

The distance between the end of the high electron concentration layer C23 for source and drain and the small area portion of the gate electrode (to) is 0.8 μm, which can be controlled to □0.5 μm or less.

In this case, the gate length and the distance between the source and drain and the gate electrode □ can be adjusted by changing the selection and composition of the dimensions of the first insulating film @ and the eighth insulating film 01. There is no need to use expensive equipment such as the electron beam direct writing method □.

In the above embodiment, the eighth insulating film (c) and the second insulating film) were interposed between the wide part of the gate electrode c! and the GaAa semi-insulating substrate, but for this reason, the gate electrode c! If the characteristics of the device deteriorate due to an increase in parasitic capacitance between the gate electrode and the high-electronic active region (c), the gate electrode c4
) may be partially removed by etching or the like as appropriate to the extent that the second insulating film (to) and the eighth insulating film 121 can be reinforced.

The types and thicknesses of metals and insulating films shown in the above-mentioned embodiments are for specifically showing the characteristics of the present invention.
This does not limit the invention.

That is, as a modification of the present invention, there is also a manufacturing method as shown in FIG. 5, for example. Incidentally, in FIG. 5, the same parts as those of the previously described embodiment are given the same reference numerals, and the description thereof will be omitted.

Figure 5 (,) shows that after completing the steps up to Figure 4 (,) (b) and (c), a second insulating film (to) is formed on the lower layer.
10. This is a diagram in which a fourth insulating film u1 is formed on the upper layer by spin-coding with odoresist or polyimide, and the first insulating film on an active region 12'4 (not shown) is removed.

Next, after removing the fourth insulator [(41), ion implantation
- is annealed to form an eighth insulating film (2) as shown in FIG. 5(b).

Next, by proceeding with the same steps as in the example, as shown in FIG.
As shown in c), a Schottky gate field effect transistor having a gate electrode C34) as described above is obtained.

〔Effect of the invention〕

According to the present invention, ultra-fine gate electrode caps can be achieved with low gate resistance without using electron beam direct writing methods that are expensive and have poor throughput, or deep ultraviolet exposure methods that have low yield and low precision. In addition, since the distance between the source and gate electrodes and between the gate and drain electrodes can be controlled finely and precisely, low source resistance, drain breakdown voltage that does not cause any problems in device operation, and low parasitic capacitance between the gate and drain can be achieved.

Therefore, high performance MBSFET, Ml (8FFiT
A semiconductor device including the following can be provided.

[Brief explanation of the drawing]

Figures 1 and 2 show different conventional MBSFETs.
The eighth factor is a cross-sectional view showing the structure of an embodiment of the ME8FET of the present invention, and FIG.
A cross-sectional view illustrating an example of a method for manufacturing SF IT,
FIG. 5 is a cross-sectional view illustrating a modification of the ME8FET manufacturing method of the present invention. 1, 11.21...GaAs semi-insulating substrate 2, 12.
22...Active region 8, 18.28...High electron concentration region 4, 14.24.84...Gate electrode metal 5.15.
'25...Source electrode metal 6, 16.26...Drain electrode metal 27...First insulating film 28...Second insulating film 29...Eighth insulating film 80... Fourth Insulating Film Agent Patent Attorney Inoue - Male Figure 1 Figure 2 Figure 3? What figure 4? 2 & 5 tbλ -320=

Claims (6)

[Claims] (1) Compound In a Schottky gate field effect transistor in which an active region in contact with a gate electrode metal and high electron concentration regions of the source and drain located on both sides of the active region are formed on a semiconductor substrate, the gate electrode metal The lower part near the contact part with the active region is formed narrower in the gate length direction than the upper part, and both heights are
Schottky gate field effect type, characterized in that the distance between the electron concentration regions is υ larger than the contact length in the gate length direction between the gate electrode metal and the active region, and the lower wall surface of the gate electrode metal is covered with an insulating film. transistor. (2) The Schottky gate field effect transistor according to claim 1, wherein the upper dimension of the gate electrode and the metal spacing between the source and drain electrodes are approximately equal. (3) Claim 1, characterized in that the active region and the high electron concentration region are formed by an ion implantation method.
Schottky gate field effect transistor as described in . (4) A step of forming a first insulating film in advance in a region where a gate electrode is to be formed on the compound semiconductor substrate where an active region is formed, and ion implantation into a high electron concentration region using the first insulating film as a mask. a step of forming a multilayer, and a step of forming the first
forming a second insulating film in a region where no insulating film is formed and removing the first insulating film, forming an eighth insulating film over the entire surface, and removing the second insulating film. The method further comprises at least the steps of: exposing the active region by leaving the eighth insulating film only on the wall surface of the second insulating film; and forming a gate electrode metal from the active region to a predetermined portion on the second insulating film. A method of manufacturing a Schottky gate field effect transistor characterized by: (5) A method for manufacturing a Schottky gate field effect transistor according to claim 4, characterized in that the ion implantation layer is annealed after forming the second insulating film and removing the first insulating film. . (6) A method for manufacturing a Schottky gate field effect transistor according to claim 4, characterized in that the third insulating film is removed by an anisotropic etching method.