JPS5922333A - Resin sealing method of ic - Google Patents
Resin sealing method of icInfo
- Publication number
- JPS5922333A JPS5922333A JP13184482A JP13184482A JPS5922333A JP S5922333 A JPS5922333 A JP S5922333A JP 13184482 A JP13184482 A JP 13184482A JP 13184482 A JP13184482 A JP 13184482A JP S5922333 A JPS5922333 A JP S5922333A
- Authority
- JP
- Japan
- Prior art keywords
- film carrier
- sealing
- resin
- reel
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000007789 sealing Methods 0.000 title claims abstract description 32
- 229920005989 resin Polymers 0.000 title claims abstract description 22
- 239000011347 resin Substances 0.000 title claims abstract description 22
- 230000014759 maintenance of location Effects 0.000 claims description 5
- 238000005096 rolling process Methods 0.000 abstract 1
- 238000012216 screening Methods 0.000 abstract 1
- 238000007650 screen-printing Methods 0.000 description 5
- 238000004804 winding Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 230000000452 restraining effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 キャリア実装に於けるＩＣの樹脂封止方法に関する。[Detailed description of the invention] This invention relates to a resin sealing method for IC in carrier mounting.
近年、水晶発振式電子腕時ｄ１の如く薄型化、小型化が
要求される装置の回路実装方式としてフィルムキャリア
実装方式が広く採用され始めている。In recent years, the film carrier mounting method has begun to be widely adopted as a circuit mounting method for devices that are required to be thinner and smaller, such as the crystal oscillation type electronic wristwatch d1.
このフィルムキャリア実装方式によると、実装から回路
組立に亘る全工程を長尺のテープ状で連続的に処理を行
なうことができ、生産コストの安い合理化工程を組むこ
とが可能であり、更に、ワイヤーを張ること無しに接続
を行なうことができるため、従来ワイヤーループに要し
た高さ方向及び平面方向のスペースを最小限度に押える
ことができ、薄型化、小型化を図ることがＤＪ能である
等の多くの利点を有し、薄型化、小型化かつ低コストな
るＩＣ実装を追求する水晶発振式電子腕時計の如き装置
のＩＣ実装構造として今後大いに期待されるものである
。According to this film carrier mounting method, the entire process from mounting to circuit assembly can be carried out continuously using a long tape, making it possible to create a streamlined process with low production costs. Since connections can be made without stretching wire loops, the vertical and horizontal space required for conventional wire loops can be minimized, making it possible to make the wire loop thinner and more compact. It has many advantages, and is expected to be used as an IC mounting structure for devices such as crystal oscillation type electronic wristwatches, which pursue thinner, smaller, and lower cost IC mounting structures.
以下従来の電子腕時訓等に於いて最も広く採用されてい
るフィルムキャリア実装方式に於けるｊ Ｃ実装構造を
第１図、第２図によって説明する。The JC mounting structure in the film carrier mounting method, which is most widely used in conventional electronic training, will be explained below with reference to FIGS. 1 and 2.
第１図は従来技術に於けるフィルムキャリア実装構造を
示す平面図。第２図は第１図に於けるＡ−Ａ断面図を示
す。FIG. 1 is a plan view showing a film carrier mounting structure in the prior art. FIG. 2 shows a sectional view taken along the line AA in FIG.
２はフィルムキャリアで、ポリイミド等の有機利ワより
成る厚さ約１２０μ７ｎ、幅３５７１＋ｍの長尺フレキ
シブルテープであり、該フィルムキャリア２には、前も
って後工程に於ける作業基準となるパイロット穴２ａ、
ＩＣを配置するためのデバイス穴２１〕等の必要な諸式
の加工を施した後、前記フィルムキャリア２の略中央部
に厚さ約３５μｍの長尺銅箔を接着し、しかる後、エツ
チング加工によって所定の回路パターン６を形成し、ボ
ンディング用フィンガー電４ｉｋ３ａを含む必要パター
ン部にＳｎメッキを施して成る。４ばＩＣ’で、その電
極４ａは蒸着、メッキ等の手法によって最上層にＡｕ層
を形成して成る突起電極であり前記回路パターン乙のフ
ィンガー電極６ａと熱、圧力によってＡ ｕ −Ｓ ｎ
共晶により全電極を同時にギヤングボンディングするこ
とによって、前記回路パターン６との接続を成す。Reference numeral 2 denotes a film carrier, which is a long flexible tape made of organic resin such as polyimide and has a thickness of approximately 120μ7n and a width of 3571+m.The film carrier 2 is provided with pilot holes 2a, which serve as working standards in the subsequent process, in advance.
After performing various necessary processing such as device hole 21 for arranging an IC, a long copper foil with a thickness of about 35 μm is adhered to the approximate center of the film carrier 2, and then etched. A predetermined circuit pattern 6 is formed by this method, and Sn plating is applied to the necessary pattern portions including the bonding finger electrodes 4ik3a. 4 is IC', and the electrode 4a is a protruding electrode formed by forming an Au layer on the uppermost layer by a method such as vapor deposition or plating, and is connected to the finger electrode 6a of the circuit pattern B by heat and pressure.
The connection to the circuit pattern 6 is established by simultaneously performing gigantic bonding on all the electrodes using eutectic.
しかる後、プラスチック等から形成された枠体５を前記
フィルムキャリア２のデバイス穴２ｂを囲む位置に接着
固定し、エポキシ樹脂等の熱硬化性樹脂から成るモール
ド部材乙によって封止し、ＩＣ実装を成した後、他の回
路素子を接続し、図中に示す一点鎖線位置より切り％１
して、回路基体１を成すフィルムキャリア実装方式が従
来より採用されていた。Thereafter, a frame body 5 made of plastic or the like is adhesively fixed to a position surrounding the device hole 2b of the film carrier 2, and is sealed with a mold member B made of a thermosetting resin such as epoxy resin, thereby mounting the IC. After that, connect other circuit elements and cut from the dot-dash line position shown in the figure.
Conventionally, a film carrier mounting method for forming the circuit board 1 has been adopted.
この様な従来技術に於けるフィルムキャリア実装方式に
よる。と、長尺のテープにて全工程を容易に連続処理す
る工程を組むことができ、工数の削減に寄与し、形状的
にもワイー）・−実装方式と比べ、薄型、小型化に寄与
し、かつ実装品の品質に於いては時計品質を充分に満足
するものである等の多くの利点を有するものである。This is based on the film carrier mounting method in the prior art. It is possible to easily set up a continuous process for all processes using a long tape, which contributes to a reduction in man-hours and is also good in terms of shape) - Contributes to thinner and smaller size compared to the mounting method. , and has many advantages, such as the quality of the mounted product fully satisfying the quality of a watch.
しかし、上記フィルムキャリア実装方式に於いても封止
に際し、枠体５を接着固定しモールド部＃６にて封止を
行なうため、実装厚が枠体５の形成上の制約を受け、又
枠体５を必要とするため部品点数が増加し、さらに枠体
５とフィルムギヤリア２の接着及びポツテング樹脂の仮
ギユア−のため工程増となる。さらには、枠体５とフィ
ルムキャリア２との接着が充分でない場合モールド部拐
６が接着境界部より流出し、安定した刺止が得ら、）ｔ
ないばかりか、周囲の半田側は部等の接着部へ悪影響を
与える等、超薄型化、超小型化及び低コス］・を追求す
る電子特訓の回路実装に於いてはまだ多くの問題点を有
している。However, even in the film carrier mounting method described above, since the frame 5 is adhesively fixed and sealed at the mold part #6, the mounting thickness is limited by the formation of the frame 5. Since the body 5 is required, the number of parts increases, and furthermore, the number of steps is increased due to adhesion of the frame body 5 and the film gear rear 2 and provision of a temporary gear of potting resin. Furthermore, if the adhesion between the frame body 5 and the film carrier 2 is not sufficient, the mold parts 6 will flow out from the adhesion boundary, resulting in stable stabbing.
Not only that, but the surrounding solder side has a negative effect on the bonding parts of parts, etc., and there are still many problems in circuit implementation for electronic training that pursues ultra-thinness, ultra-miniaturization, and low cost. have.
又フィルムキャリア実装方式に於ける封止方法の他の従
来例としては、単にポツテングする方法やトランスファ
ー成形する方法が）、るか、前者の方法はＩＣのみ樹脂
封止され、フィンガ一部は封止されずに露出されるため
機械的強度が弱く、電子腕時計のごとき携帯装置には採
用出来ず、又後者の方法は、特性的には満足出来るが、
設備や工数の点に於いてコスト高となり、いずれも前述
の枠を用いた封止方法に比べて欠点があった。Other conventional sealing methods in the film carrier mounting method include a simple potting method and a transfer molding method. Since it is exposed without being stopped, its mechanical strength is weak, and it cannot be used in portable devices such as electronic wristwatches.Although the latter method is satisfactory in terms of characteristics,
Both methods are disadvantageous compared to the above-mentioned sealing method using a frame, as they are expensive in terms of equipment and man-hours.
本発明の目的は、上記する様な従来技術に於ける諸問題
点を解決し、薄型、小型かつ低コストなるフィルムキャ
リア実装を実現することであり、上記目的を達成するた
めの本発明に於ける要旨は、フィルムキャリアを使用し
、該フィル１、キャリアに連続的に設けられたデバイス
穴内に形成されたフィンガー電極を用し・てギヤングボ
ンディングされたＩＣの樹脂封止方法に於いて、前１１
己フイルムキヤリアをリールに巻取りながら、ＩＣ面上
に形状保持性の大きい封止樹脂をスクリーン印刷し、リ
ールに巻取られたフィルノ、キャリアを炉に入れて直接
本キュアーすることにより前記ＩＣ面上に印刷された封
止樹脂を硬化させることを特徴としている。The purpose of the present invention is to solve the problems in the prior art as described above and to realize a thin, small, and low-cost film carrier mounting. The gist of this is that in a method for resin-sealing an IC that uses a film carrier and is subjected to gigantic bonding using the film 1 and finger electrodes formed in device holes continuously provided in the carrier, Previous 11
While winding the self-film carrier onto a reel, a sealing resin with high shape retention is screen-printed on the IC surface, and the film carrier wound onto the reel is placed in a furnace and directly cured to cure the IC surface. It is characterized by curing the sealing resin printed on it.
以下本発明によるフィルムキートリア実装方式に於ける
ＩＣの封止方法を第３図、第４図、第５図、第６図によ
って説明する。尚、図中、第１図、第２図と共通する番
号は第１図、第２図と同一部材を示す。The method of sealing an IC in the film key ria mounting method according to the present invention will be explained below with reference to FIGS. 3, 4, 5, and 6. In the drawings, the same numbers as in FIGS. 1 and 2 indicate the same members as in FIGS. 1 and 2.
第３図乃至第６図は本発明に於けるＩＣの封止方法を示
す回路基体に於けるＩＣ実装部の断面図であり、第３図
及び第４図ば１． Ｃの上面側の封止工程を示し、第５
図はＩＣの下面側の封止工程、第６図は封止完成状態を
示す。3 to 6 are cross-sectional views of the IC mounting portion in the circuit board showing the IC sealing method according to the present invention. This shows the sealing process on the upper surface side of C.
The figure shows the sealing process on the bottom side of the IC, and FIG. 6 shows the completed sealing state.
第３図に於いて１０は裏打治具板、１１はスクリーンマ
スクであり、第２図と同様にデバイス穴２１〕内に形成
されたフィンガー電極６ａにギャングボンブイングされ
たＩＣ４を備えたフィルムキャリア２を裏打冶具板１０
に対し、前記パイロット穴２ａを位置基準としてＩＣ４
がＩＣ収納部１０ａに収態されるごとく載置し、さらに
フィルムキャリア２の上面側よりＩＣ４の部分に開口部
１１ａを合わせてスクリーンマスク１１を被せ、封止樹
脂１２をスクリーン印刷することにより第４図に示ずご
と＜ｉｃ４の上面側を制止することが出来る。In FIG. 3, 10 is a backing jig plate, 11 is a screen mask, and as in FIG. 2. Backing jig plate 10
On the other hand, IC4 is set using the pilot hole 2a as a position reference.
is placed in the IC storage part 10a, and then a screen mask 11 is placed on the film carrier 2 with the opening 11a aligned with the IC 4 part from the top side of the film carrier 2, and the sealing resin 12 is screen printed. As shown in Figure 4, the upper surface of IC4 can be stopped.
次に第５図に示すごとくＩＣ収納部１３ａを有する裏打
治具板１６にフィルムキャリア２を反転させて載置し、
開口部１４ａを有するスクリーンマスク１４を用いてフ
ィルムキャリア２の下面側に制止樹脂１２をスクリーン
印刷することにより第６図に示すごと＜ｉｃ４の表裏面
及びリード電極６ａを最小限のスペースにて完全に封止
することが出来る。Next, as shown in FIG. 5, the film carrier 2 is inverted and placed on the backing jig plate 16 having the IC storage section 13a.
By screen printing the restraining resin 12 on the lower surface side of the film carrier 2 using a screen mask 14 having an opening 14a, as shown in FIG. It can be sealed.
尚前記封止樹脂１２には最近開発された粘度９Ｘ］０５
ＣＰＳのエポキシ系高粘度樹脂を使用し、その形状保持
性が大きいため、スクリーン印刷によって形成さ、ｈた
制止樹脂は加熱しない状態でリール巻取りを行なっても
十分形状を保持することが出来る。The sealing resin 12 has a recently developed viscosity of 9X]05.
CPS's high viscosity epoxy resin is used and its shape retention is high, so the restraining resin formed by screen printing can sufficiently retain its shape even if it is wound up on a reel without heating.
したがって製造工程としては、従来行なわれているよう
なフィルムキャリアに連続的にボンディングされたＩＣ
をリールに巻取りながら連続的にＩＣ面上にポツテング
した封止樹脂をラインの中間に設けた仮キーアー炉を通
して半硬化させ、この状態にしてリールに巻取ったフィ
ルムキャリアをリールごと炉に入れて本キュアーする方
式に対し、本願の工程は、フィルムキャリアをリールに
巻取りながら連続的にＩＣの上面側に形状保持性の大き
い封止樹脂をスクリーンマスク
ーすることなく巻取ったり〒ルを反転させて逆巻取りを
しながら連続的に下面側のスクリーン印刷を行なうこと
によって第６図に示す刊市完成状態のＩＣを実装したフ
ィルムキャリアをリールに巻取り、これをリールごと炉
に入れて直接本キュアーさせることにより完成する。Therefore, as a manufacturing process, ICs are continuously bonded to a film carrier as conventionally done.
The encapsulating resin is continuously potted onto the IC surface while being wound onto a reel, and is semi-cured through a temporary Kier furnace installed in the middle of the line.In this state, the film carrier wound onto a reel is placed into the furnace together with the reel. In contrast to the method in which the film carrier is wound onto a reel, the sealing resin with high shape retention is continuously applied to the top surface of the IC without using a screen mask. By inverting and winding the film in the reverse direction, screen printing is continuously performed on the lower side, and the film carrier with the completed IC mounted thereon as shown in Figure 6 is wound onto a reel, and the entire reel is placed in a furnace. It is completed by directly curing it.
上記のごとく本発明によれば、ＩＣを実装したフィルム
キャリアをリールに巻取りながら前記ＩＣ面上に形状保
持性の大きい封止樹脂をスクリーン印刷法により塗布し
、これを樹脂の形状保持性の大きいことを利用して、そ
のままリールに巻取ってしまい、このリールを一括して
炉に入れ、直接本キュアーすることによりリール１本分
のテープに実装されたＩＣの樹脂封止を同時に行なうこ
とが出来るため、テープライン中間での仮キュアー炉を
必要とぜず、さらに、スクリーン印刷という簡単な設備
と作業によって行なうことが出来るため設備費及び工数
の削減により低価格となり、電子腕時計等の小型電子装
置に適したＩＣの封止方法、すなわち封止形状が小さく
、かつ廉価なＩＣの封止方法を提供することが可能とな
った。As described above, according to the present invention, while winding a film carrier on which an IC is mounted onto a reel, a sealing resin having a high shape retention property is applied onto the IC surface by a screen printing method. Taking advantage of its large size, the tape is simply wound onto a reel, and the reel is then placed in a furnace and directly cured, thereby simultaneously resin-sealing the ICs mounted on one reel of tape. This eliminates the need for a temporary curing furnace in the middle of the tape line, and it can be performed using simple equipment and operations such as screen printing, which reduces equipment costs and man-hours, resulting in lower costs, and is suitable for small products such as electronic wristwatches. It has become possible to provide an IC sealing method suitable for electronic devices, that is, an IC sealing method that has a small sealing shape and is inexpensive.
第１図は従来技術に於けるフィルムキャリア実装構造を
示す平面図。第２図は第１図に於けるＡ−Ａ断面図、第
３図乃至第６図は本発明に於けるＩＣの封止方法を示す
回路基体に於けるＩＣ実装部の断面図であり、第３図及
び第４図はＩＣの」二面側の封止工程を示し、第５図は
Ｉ Ｃの下面側の制止工程、第６図は封止完成状態を小
ず。
１・・・・・・回路基体、
２・・・・・・フィルムキャリア、
２ａ −−パイ日ソ１゛穴、
２ｂ・・・・・デバイス穴、
６・・・・・・回路パターン、
６ａ・・・・・フィンガー電極、
１０．１６・・・・・裏打治具板、
１１．１４・・・・・スクリーンマスク、１２・パ・・
・制止樹脂。
第１図
３
第２図
第３図
第４図
第５図FIG. 1 is a plan view showing a film carrier mounting structure in the prior art. FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1, and FIGS. 3 to 6 are cross-sectional views of an IC mounting part in a circuit board showing the IC sealing method according to the present invention. Figures 3 and 4 show the sealing process on the two sides of the IC, Figure 5 shows the sealing process on the bottom side of the IC, and Figure 6 shows the completed sealing process. DESCRIPTION OF SYMBOLS 1...Circuit substrate, 2...Film carrier, 2a--PiNISO1 hole, 2b...Device hole, 6...Circuit pattern, 6a ...Finger electrode, 10.16...Backing jig plate, 11.14...Screen mask, 12.Pa...
・Suppression resin. Figure 1 Figure 3 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
的に設けられたデバイス穴内に形成されたフィンガー電
極を用いてギヤングボンディングされたＩＣの樹脂封止
方法に於いて、前記フィルムキャリアをリールに巻取り
ながら、ＩＣ面上に形状保持性の大きい封ｄ−，樹脂を
スクリーン印刷し、リールに巻取られたフィルムキャリ
アを炉に入れて直接本キ１．アーすることにより前記Ｉ
Ｃ面上に印刷された封止樹脂を硬化させることを特徴と
するｆＣの樹脂封止方法。In a resin sealing method for an IC that uses a film carrier and is subjected to gang bonding using finger electrodes formed in device holes continuously provided in the film carrier, the film carrier is wound onto a reel. 1. A sealing resin with high shape retention is screen printed on the IC surface, and the film carrier wound on a reel is placed in a furnace and directly heated. By arching the above I
A resin sealing method for fC characterized by curing a sealing resin printed on the C side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13184482A JPS5922333A (en) | 1982-07-28 | 1982-07-28 | Resin sealing method of ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13184482A JPS5922333A (en) | 1982-07-28 | 1982-07-28 | Resin sealing method of ic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5922333A true JPS5922333A (en) | 1984-02-04 |
| JPH0313750B2 JPH0313750B2 (en) | 1991-02-25 |
Family
ID=15067418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13184482A Granted JPS5922333A (en) | 1982-07-28 | 1982-07-28 | Resin sealing method of ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922333A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2774810A1 (en) * | 1998-02-10 | 1999-08-13 | St Microelectronics Sa | Screened integrated circuit packaging and method for the fabrication |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365052A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | High speed logic circuit |
| JPS5365062A (en) * | 1976-11-24 | 1978-06-10 | Hitachi Ltd | Production of semiconductor and apparatus for the same |
-
1982
- 1982-07-28 JP JP13184482A patent/JPS5922333A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365052A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | High speed logic circuit |
| JPS5365062A (en) * | 1976-11-24 | 1978-06-10 | Hitachi Ltd | Production of semiconductor and apparatus for the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2774810A1 (en) * | 1998-02-10 | 1999-08-13 | St Microelectronics Sa | Screened integrated circuit packaging and method for the fabrication |
| US6312975B1 (en) | 1998-02-10 | 2001-11-06 | Stmicroelectronics S.A. | Semiconductor package and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0313750B2 (en) | 1991-02-25 |
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