JPS59220574A - Cpu speeding preventing system in electronic lock system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a CPU runaway prevention method in an electric lock system that uses a CPU to perform unlocking code verification processing.

[Background technology]

FIG. 1 is a block diagram of a conventional electric lock system. In the same figure, (1) is a collation processing means, and CP
It is composed of a micron fuser containing U f2+. (3) is the operation panel, where you enter the unlock code (4), and various display lamps (5)
etc. When the unlock code is input from the operation panel (3), the state ashing detection means (6) detects this and
Power from the stain source supply means (8) is supplied to the CPU (2) by the PU power-on means (7). CPU (2
The verification processing means +1+ compares and verifies the code input from the operation panel (3) with a pre-stored registration code, and outputs a match detection signal when they match.

The unlocking means (9) opens the electric lock (10) when the coincidence detection signal is input. When the CPU (2) completes the verification processing operation, it sends the PU electric power supply 1st year number (,: PU electric power supply 1st year number) and stops the power supply from the power supply means (8) to the CPU (2).

By the way, in such an electric lock system, the CPU (2
) goes out of control due to fluctuations in the power supply voltage, etc., it may malfunction or become inoperable in response to input, resulting in inconveniences such as the inconvenience that it cannot accept any further human effort.

[Purpose of the invention]

The present invention has been made in view of the above points,
Provides a CPU runaway prevention method for electric lock systems that automatically returns the CPU to a normal state in the event that the CPU used to perform the verification process goes out of control.
The purpose is to

[Disclosure of the invention]

The configuration of the present invention will be described below with reference to the illustrated embodiments. As shown in FIGS. ), an unlocking means (9) performs an unlocking operation of the electric lock (10) in response to a coincidence detection signal, and a CPU power-on means (7) turns on the CPU power at the start of inputting an unlocking operation. When the CPU power is turned on, the CPU power is turned off after the verification process of the unlock code is completed, and when the CPU power is turned on, the clocking operation is started, and the CPU (processing of 21) required by the electric lock system is A clocking means Q'4 outputs a clocking end signal after a time longer than the time has elapsed, and a CPU power control means a field for forcibly turning off the CPU power at the clocking end signal of the clocking means θ group. c P U in electric lock system
The actual working time of +2+ is at most 10 seconds, and CPU+2+ will not continue working for any longer. Therefore, if power is supplied to the CPU (21) for more than this time, it can be determined that the CPU (2) is in a runaway state. The time required to complete is approximately 1
Set it to about 5 seconds. However, in the embodiment shown in FIG. 2, when the unlock code is input on the operation panel (3), the clocking means (121) is detected by the output of the state change detecting means (6).
starts the timing operation. ``Then, in the event that the CPU (21) in the verification processing means (1) goes out of control, the CPU power source 1
At the time of crotch, CPU (2
However, the power supply to CPU (2
), when the elapsed time after the start of operation exceeds about 15 seconds, the timer (a) outputs a timer end signal, and this timer end signal causes the CPU power control means @ to operate, and the power supply means (8) The power supply to the CPU +2+ is forcibly stopped. CPU (21) is designed so that when the power supply is cut off, all internal registers and counters are reset.
(By turning off the power at step 21, the electric lock system automatically returns to its normal state.

FIG. 8 is a block circuit diagram of a main part in a more specific embodiment of the present invention. In the figure, (12A) is a timer IC consisting of a recoupled one-shot multivibrator used as the timekeeping means (6), and (12A)
18A) is a switching means used as the CPU power supply control means lJi. Furthermore, (8A) is the power supply section (8A).
) is a constant voltage power supply unit used as a power supply.

In the embodiment of FIG. 8, only the construction of the main parts around the CPU (2) is shown, but the general structure other than the main parts is the same as that of FIG. 2. 114 (a) to (d) show the respective operating voltage waveforms of sections a to d in the circuit of FIG. First, FIG. 4(a) shows a state change input (starting pulse). This status change input is sent to the status change detection means (6) when the operation panel (3) is operated.
The pulse width is, for example, approximately 5 m5 ec. The timer I C (12A) is set by this state change input (starting pulse) and starts timing operation. During the timer operation of the timer IC (12A), a control signal as shown in FIG. 4(C) is supplied to the switch means (13A). During the period when this ]] human zero signal is at H level, the switching means (13A) is turned on and the constant voltage power supply section (8
The output voltage of A) indicates the switch means (13A) and is supplied to the power input terminal of CPU (21).
U f2) is busy signal (B
US Y ) is output. This busy signal is the timer IC
(12A) is connected to the reset input. Here, the set input of timer I C (12A) is a rising trigger, but the reset input is a falling trigger. Therefore, the timer IC (12A) is reset at the timing of the fall of the busy signal (BUSY), that is, at the timing when the CPU f21 ends its operation. When timer IC (12A) is reset, the control signal goes low as shown in Figure 4 (C).
level, which causes the switching means (18A
) is turned off, and the CPU (
The power supply to 21 is stopped. As is clear from the above explanation of the operation, the timer IC (1
2A) is a one-pronged CPU power supply in the embodiment shown in FIG. In the embodiment of FIG. 8, when CPU (2) falls into a runaway state due to fluctuations in power supply voltage, etc.
(2) The digital lock signal (BLISY) remains at H level, and the timer IC (12A) is not reset from the outside even after the processing time (approximately 10 seconds) of the electric lock system has elapsed. The timer IC (12A) has a time constant circuit consisting of a resistor R and a capacitor C, and as time passes, the charging voltage of the capacitor C gradually increases as shown in FIG. 4(d). When this charging voltage reaches a predetermined level, the timer IC (12A) is turned on and the control signal i goes low as shown in the 41st package).
level. As a result, the switch means (iaA
) is turned off and the CPU is disconnected from the constant voltage power supply (8A).
The power supply to (2) is stopped. Therefore C
Even if P U (1) goes into a runaway state due to fluctuations in the power supply voltage, the timer I C (12A) is reset at time-up as described above, and the power to CPU (21) is automatically turned off. te CPU (2
+ can be returned to its normal state.

Generally speaking, fluctuations in the power supply voltage of the CPU (CPU 12) are detected to prevent the CPU from running out of control.
When the operating voltage of 21 is out of range, CPU (21
Resetting the runaway CPU (2) to return it to the state of 9 has been done for some time, but the present invention is completely different from the general CPU runaway prevention method. be. The present invention, as shown in FIG.
・So-called power-save type electricity that has a power-on means (7) and a CPU power-off means (9), etc., and supplies power to the CPU i21 only when the electric lock system requires processing. C used in locking systems
P U (2j runaway prevention method, C P U
This invention utilizes the property that f21 is not supplied with power for a certain processing time or longer. An electric lock system using such a power saving method is particularly useful in applications where it is necessary to save power consumption, such as when using a battery as a power source.

〔Effect of the invention〕

The present invention is configured as described above, and includes a verification processing means that performs an unlocking code verification process using a CPU, an unlocking means that performs an unlocking operation of an electric lock based on a coincidence detection signal from the verification processing means, A means to turn on the CPU power at the start of unlocking operation input, and a means to turn on the CPU power after inputting the unlocking code is completed.
In an electric lock system comprising a PU'F [means for turning off the power source, the timing operation starts when the CPU power is turned on, and after a time longer than the processing time of the CPU required by the electric lock system has elapsed. It consists of a timer that outputs a timer end signal, and a CPIJ% source control device that forcibly turns off the CPU power in response to the timer's end signal. Even if the CPU goes into a runaway state, if a time period longer than the CPU processing time required by the electric lock system has elapsed and the clock end signal is output from the clock means, the power supply to the CPU will be forcibly cut off. The CPU is shut down and the system is automatically restored to its normal state.
This can prevent inconveniences such as the CPU running out of control and exhibiting abnormal operation, or becoming inoperable in response to input and unable to handle subsequent human effort.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram of an embodiment of the present invention, Figure 3 is a block circuit diagram of a main part of another embodiment of the above, and Figure 4 (company). This figure is an explanatory diagram of the same operation as above. (1) C comparison processing means, (2) CPU 171
[Power on means, (9) is unlocking means, (1o) is electric lock,
θυ is the CPU power off means, θ is the clock means, and a is C.
This is a PU power control means. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] +11 A verification processing means that performs a verification process for unlocking by the CPU, an unlocking means that performs an unlocking operation of the electric lock based on a coincidence detection signal from the verification processing means, and a CPU In an electric lock system comprising a means for turning on the power and a means for turning off the CPU power after verification processing of the input unlock code is completed, a timing operation is started when the CPU power is turned on, and the electric A timer that outputs a timer end signal after a time longer than the CPU processing time required by the lock system, and a CPU power control device that forcibly turns off the CPU power in response to the timer's end signal. A CPU runaway prevention method in an electric lock system characterized by comprising: