JPS59219032A - voltage generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to voltage generation circuits. The present invention relates to circuits, or in other words, techniques effective for voltage sources that cancel out echo components.

[Background technology]

In digital telephones, voice signals are converted into pulse signals and transmitted. In this case, the transmitted signal will contain echo components in addition to the main pulse obtained by converting the audio signal. An equalizer is used to remove this echo component. The equalizer forms a signal corresponding to the echo component and subtracts it from the transmitted pulse signal, thereby forming an equalized signal with the echo component reduced from the pulse signal.

Such an equalizer requires a voltage generation circuit to form a signal corresponding to the echo component.

In order to perform highly accurate equalization, in other words, to reduce echo components from the transmitted pulse signal as much as possible, it is necessary for the equalizer to form signals corresponding to echo components of multiple orders. The equalizer has no power supply voltage dependence.

This requires a voltage generation circuit that generates a highly precisely controlled minute voltage.

[Purpose of the invention]

An object of the present invention is to provide a voltage generation circuit that can generate a highly precisely controlled minute voltage.

Another object of the present invention is to provide a voltage generation circuit capable of forming a voltage signal corresponding to an echo component capable of highly accurate equalization of the main pulse.

The objects and novel features of this invention and its ponds are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by forming a signal with a pulse width inversely proportional to the changing component of the reference current and charging the capacitor with the current formed based on the reference current only during this pulse width, the fluctuation of the reference current is influenced. The voltage that is not applied is generated based on the voltage held in the capacitor.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, each circuit shown in the figure is constituted by MO8F, ET (insulated gate field effect transistor).

It is formed on a single semiconductor substrate such as silicon by known semiconductor integrated circuit technology.

In the same figure, MOS shown with circuit symbols such as Ql etc.
The FET is a p-channel MOSFET, and the Q
The MOS FETs indicated by circuit symbols such as 4 are n-channel MO8FETs, so the circuit of this embodiment is constituted by a CMO8 (complementary MO8) circuit.

The n-channel MO8FETQ4, which has a predetermined reference voltage Vref applied to its gate, has a reference current I. form. This current I. is supplied to a p-channel MO8FETQI whose gate and drain are shared. By providing p-channel MO3FETs Q2 and Q3 configured in a current mirror configuration with the p-channel MO8FET QI, a current flow according to the reference current I0 from the input of these MO8FETs Q2 and Q3.・And current α engineering. are formed respectively.

Above 'current α'. The above-mentioned standard Kairyu Techniques. It is used to form a pulse width signal that is inversely proportional to the variation of . That is, the source and power supply voltage VD of the above MO8FETQ3
A switch MO8FETQII composed of a p-channel MO8FET is provided between the MO8FET and D. This MO8
A clock signal CLK is applied to the gate of FETQ11. When this clock signal CLK is at low level, MO8FETQI1 is turned on, and MO8FETQI1 is turned on.
Power supply voltage VDD is supplied to FETQ3. This causes the above current α to flow from the drain of MO8FETQ3.

is output. This current αIo is used as a charging current for the capacitor C1. Further, between the capacitor C1 and the ground potential of the circuit, the clock No. 215 CLK is connected.
An n-channel MO8FET QI 2 is provided to receive the signal. MO8FETQI 2 is.

It is turned on when the clock signal CLK is at a high level. As a result, the charge stored in the capacitor C1 is discharged through the MO8FETQI2. The holding voltage Vl of the capacitor C1 is applied to the non-inverting input terminal (+) of the voltage comparison circuit VC. The inverting input terminal (-) of this voltage comparator circuit VC is applied with the reference voltage vref, which is not particularly limited. signal CLK
and is input to the NOR gate circuit G1. As a result, as will be described in detail later, the NOR gate circuit GH forms a NOR signal ψ having a NOR pulse inversely proportional to the fluctuation component of the reference current. Although not particularly limited, the generated voltage In order to be able to adjust the value of out, a logic circuit LOG is provided which receives the pulse signal φ and the control signals Up and Down and forms a pulse signal U and a pulse signal R.

Although not particularly limited, in this embodiment, the logic circuit OG is constituted by a three-man powered NAND circuit G2, a three-man powered AND circuit G3, and a two-man powered NOR circuit G4. By configuring the logic circuit LOG as shown in the figure, for example, the limit signal Up can be set to
- When the signal is turned on (binary signal "1"), the gate circuit G2 is opened and a pulse signal U according to the signal φ is output.In contrast, the control signal ]) When the current level (“1”) is set, the gate circuit G3 is opened and a pulse signal according to the current signal φ is output. When the control signals Up and ])own are both low level (“0”).

Regardless of the pulse number Φ, a pulse signal U of low level (1'') and a pulse signal U of low level (0') are output.

In order to form a voltage controlled with high precision, the MO8F
Current ■ formed in ETQ2. ' is p-channel MO
It is supplied to n-channel MO8FETQ8 via 8FETQ7. This MO8FETQ8 and the n-channel MO8FETQ15, which is in a current mirror configuration, allow a sinking current of β.

is formed. Further, a push current β0 is formed by the MO8FBTQI and the p-channel MO8FETQ14 in a current mirror configuration.

Although not particularly limited, in this embodiment, a p-channel MO8FETQ9 whose gate is constantly supplied with the circuit ground potential is provided between the source of the MO8FET Q2 and the power supply voltage VDD, and the MO8FET
There is a voltage at the gate between the source of Q8 and the circuit ground potential.
n-channel MO8F with constant voltage DD
ETQIO is provided.

Although not particularly limited, the above current I. To ensure that ′ is a value that accurately follows the standard electric construction ◎.

Between the drain of MO8FETQ5 receiving the reference voltage Vref and the power supply voltage VDD, there is
FETQ6 is provided, and its gate is connected to the above MO8FET.
By connecting the gate of the MO8FET Q7 to the drain of the MOSFET G6, a bias voltage is applied to each of them.

MO8 forming the above extrusion charge 1IL) current βI0
The source of FETQ14 is connected to a switch MO made up of a p-channel MO8FET that receives the above pulse (d number U).
Power supply voltage V is supplied via 8FETQI3. In addition, MO8FETQI which forms the above-mentioned suction (discharge) 'lII flow β■o
5 is a switch MO8FETQI, which is composed of an n-channel MO8FET that receives the above pulse signal.
6, the ground potential of the circuit is supplied.

Then, MO8FETQI that forms each of the above currents βIo
A capacitor C2 is provided between the connection point of 4 and Ql 5 and the ground potential of the circuit, and an output voltage is formed by charging and discharging the capacitor C2. Although not particularly limited, in this embodiment, the formed capacitor C2
The holding voltage (Vout) is sent out through a voltage follower circuit composed of an operational amplifier circuit OP.

Next, the operation of this embodiment circuit will be explained according to the timing diagram of FIG.

When the clock signal CLK is changed from high level (logic ``1'') to low level (logic ``0''), MO8FE
TQI 2 is turned off and MO8FETQll is turned on. From this K, the capacitor CI is MO8FE
It is charged by the current ffIo generated by TQ3. This charging operation increases the charging voltage (holding voltage) Vl of the capacitor C1. When the value of this charging voltage V1 becomes larger than the reference voltage Vref, the output signal 2 of the voltage comparison circuit VC changes from low level to high level.

The pulse signal φ formed by the NOR gate circuit G1 receiving the clock signal CLK and the output signal V2 is a signal with a pulse width proportional to the time until the charging voltage 1 of the capacitor C1 reaches the reference voltage Vref. . The charging time of the capacitor C1 is the current α. As the current α increases, the current becomes shorter, and as the current α decreases, the current becomes longer. Therefore, the current α k. and the pulse width of the pulse signal ψ are inversely proportional to each other.

@In the logic circuit LOG, the above pulse signal φ is the control im
@No. U p, ]) Pulse signals U, D according to owr+
is converted to For example, when the secondary fH signal Up is set to high level (1"), MOS FETQ13 is turned on for the pulse width (high level period) of pulse signal φ. MO8FETQ13 is turned on. By doing so, capacitor C2 becomes .

Current β■ formed in MO8FETQI 4 above.

is charged by Therefore, when the control signal Up is set to no-repel, the capacitor C2 is connected to the pulse signal φ
The current β rises each time the pulse width reaches a high level (pulse width). is charged by

On the other hand, the control wJ signal 1) own is at a high level (1
”), the pulse width of the pulse signal φ (
MO8FETQ16 is turned on only during the high level period). By turning on the MO8FETQ16, the capacitor C2 is connected to the MO8FETQI
5. The current β is formed by 5. is discharged by. Therefore,
When the control H No. Down is set to high level, the capacitor C2 has a pulse signal Φ of high level (pulse width).
Each time the current β1. is discharged by.

The output voltage Vout is substantially equal to the holding voltage of the capacitor C2. Amplitude of output voltage vout (change amount by 1!)
is determined by the amount of charge Q obtained in time t corresponding to the number of pulses of the current βIOy pulse signals U and D and the pulse width thereof, and the capacitance value C of the capacitor C2 (Vout
=Q/C). For example, if the number of pulses of the pulse signal U supplied to 9M08FETQ13 when the control signal Up is at a high level is 10, this number of pulses,
The output voltage ■out increases by a voltage value according to the amount of charge determined by the time and current βIo corresponding to the pulse width and the capacitance value of the capacitor C2. Conversely, when the control signal]) own is set to high level.

If the number of pulses of the pulse signal @D supplied to MO8FETQ16 is 5, the voltage value is according to the number of pulses, the time corresponding to the pulse width, the amount of charge determined by the current βIo, and the capacitance value of the capacitor C2. Output voltage ■ou
t decreases.

Note that when the pulse signal @U is at high level (l'') and the pulse signal is at low level (“0”), MO8FETQ
Since I3 and Ql6 are both turned off, capacitor C2 maintains its holding voltage. Therefore, when the control fg (UT) and Down are both set to low level, the output voltage voutO value hardly changes.

In this embodiment, a potential change in the output voltage V Out (voltage value of minute voltage ΔV) with respect to one pulse of the pulse signal φ, in other words, a potential change in the output voltage ■out with respect to one pulse of the pulse signal U or D. (minor voltage Δ
The amount of charge ΔQ that determines the voltage value of V is the relationship between time t corresponding to the width of the pulse and current βIo (t x βIO)
become. As mentioned above, the time (pulse width) t is the current αI.

It is inversely proportional to (t(x:1/α1.). Therefore.

The relationship ΔQ=K (constant)×β/α holds true. α.

By appropriately selecting β (size ratio of current mirror MO8FET), the current ■. It is possible to form a desired value of @small voltage Δ■ that is not affected by fluctuations in .

That is, the ratio Wl/Ll of the channel length Ll of MO8FETQI and its channel width W1.

α is mainly determined by the ratio W3/L3 between the channel length L3 of MO8FETQ3 and its channel width W3, and Wl/Ll is the ratio between the channel length L1 of MO8FETQI and its channel width W1.

By appropriately selecting β, which is mainly determined by the ratio W14/L14 between the channel length L14 of MO8FETQ14 and its channel width W14, the value of the minute voltage Δ■ can be set to a desired value.

Moreover, the reference current may vary due to variations in manufacturing conditions, fluctuations in voltage, etc. Even if the value of changes, the above formula (ΔQ =
K Xβ/α) with electric current. Since there is no term, the value of the generated minute voltage ΔV (ΔV=CXΔQ) hardly changes. Furthermore, by setting the value of β/α in the above equation to an appropriately small value, it is possible to form a voltage of approximately several mV with high precision.

Note that the mirror-shaped MOSFET is operated in a saturation region.

Further, in order to form a minute voltage Δ■ having a desired value, the capacitance value of the capacitor C1, the valley value of the capacitor C2, or both capacitance values may be appropriately set.

As mentioned above, control 1al (, No. 3 Up and ]) own
Accordingly, the number of pulses of the pulse signal U supplied to the MO8FETQ13 and the number of pulses of the pulse signal U supplied to the MO8FETQ16 can be adjusted. Thereby, the voltage value of the output voltage Vout can be controlled in units of the scanning voltage ΔV. Moreover, since the minute voltage Δ■ is almost unaffected by fluctuations in the power supply voltage, the value of the output voltage Vout hardly changes due to fluctuations in the power supply voltage.

When a MOSFET is used as the switching means controlled by the pulse signals U and D, when the MOSFET changes from the on state to the off state, the charges forming the channel flow into the capacitor C2. Further, due to capacitive coupling between the gate electrode and the source region and capacitive coupling between the gate electrode and the drain region, changes in the potential of the gate electrode are transmitted to the source region and the drain region. For this reason, in the MOS and FET which receive the pulse signal U at their gate electrode, the voltage of the electrode υ decreases when the power supply voltage is supplied, and the MOSFE which receives the pulse signal @D at its gate it pole
At T, the potential of the electrode of one circuit to which the ground potential is not supplied changes. This change in potential causes the capacitor C to
2' charge amount changes. Together, these are called clock feedthroughs, and may cause errors in the minute voltage values. In this example, since the p-channel MO8FETQ13 is used as the MOSFET responsible for the switching operation of the above-mentioned charging current, its field through greatly increases the output voltage vOut (
Charging current) acts in the direction of f. On the other hand, the above suction (
Since the n-channel 7-channel MOSFET Q16 is used as the MOSFET responsible for the switching operation of the discharging current, its field through acts in the direction of reducing the output voltage Vout (discharging current). Therefore, MO8F
By making the respective dimensions (sizes) of ETQI 3 and Q16 the same and making the field-through values generated in each of them about the same, the minute amount when the output voltage vout increases due to the control [1 Absolute value of voltage ΔV and control signal]) Output voltage vout by wn
The absolute value of the minute voltage ΔV when the voltage decreases can be made almost equal to the absolute value of the minute voltage ΔV. As a result, when the output voltage Vout is formed by photoelectric discharge/discharge of the capacitor C2, the field through is biased in one direction.
There is no possibility that the holding voltage of the capacitor c2 gradually becomes thicker or gradually becomes smaller.

For example, the above MO8FETQI 3 is an N-channel type M
When configured with an O8FET, the feedthrough acts in the direction of reducing the output voltage Vout. Therefore,
The feedthroughs of the MQSFETs QI 3 and Ql 6 act in the direction of reducing the output voltage (output). That is, the output voltage V is changed by the control signal Up.
The absolute value of the minute voltage Δ■ when the output voltage Vout decreases due to the control signal Down becomes larger than the absolute value of the minute voltage Δ■ when the output voltage Vout increases. Therefore, if, for example, the pulse signal U and the pulse signal R are alternately applied to the MO8F'ETQ13 and Ql6, the voltage held in the capacitor C2 will gradually become smaller.

In other words, the value of the output voltage Vout gradually decreases to L7 and does not reach the desired value. On the other hand, if feedthrough acts in both directions as described above, the value of the output voltage An output voltage Vout of a desired value can be formed.

In addition, in Example 2 described next, the above MO8FE
No TQI, Ql2. capacitor ci.

The circuit constituted by the voltage comparison circuit VC and the NOR circuit G1 is called a current-pulse width conversion circuit IC, and the above MO
The circuit constituted by the 8FETs Q13 to Ql6, the capacitor C2, and the operational amplifier circuit OP is referred to as a pulse width-voltage conversion circuit CV.

Umbrella [Embodiment 2] FIG. 3 is a block diagram of an embodiment in which the present invention is applied to a decision feedback automatic equalizer, which is a type of line equalizer for digital telephones.

The audio signal is converted into a pulse signal having both positive and negative polarities, that is, a bipolar pulse signal, and then transmitted. For example, by connecting a branch line to a transmission line for transmitting this pulse signal, the transmitted pulse signal contains an echo component. A decision feedback automatic equalizer as described below is used to remove echo components from the transmitted pulse signal.

That is, the input signal BTIN containing the echo component is applied to the 10,000 input terminal (+) of the addition/subtraction circuit 1. The output of the adder/subtracter circuit 1 is supplied to a three-valued bell determination circuit M provided for identifying an audio signal converted into a bipolar pulse signal.

In addition, in the input signal BTIN, the peak voltage of the bipolar pulse signal converted from the audio signal is ±1. Ov
It is being done.

The above three-valued bell judgment circuit M includes a voltage comparator 2゜3, AN
D circuit 4. exclusive OR circuits 5 and N;

It is constituted by an R circuit 6. A reference voltage of 0.5V is applied to the inverting input terminal (-) of the voltage comparator 2, and a reference voltage of K-0.5V is applied to the inverting input terminal (-) of the voltage comparator 30. As a result, if the potential of the output signal of the power-low subtraction circuit 1 exceeds 0.5V, the AND circuit 4
The output signal X becomes high level (binary signal "1"),
If the output signal of the addition/subtraction circuit 1 has a value lower than 10.5V, the output signal Y of the NOR circuit 6 becomes high level (binary signal "'1"), and the potential of the output signal of the addition/subtraction circuit 1 becomes If the value is within the range of the reference voltage 0.5 V and 10.5 V, the output signal 2 of the exclusive OR circuit 5 becomes high level /I/ (binary signal "1").

For example, if the level of the pulse signal converted from the audio signal is 1
(2) If this is supplied to the ternary signal and bell judgment circuit M without any echo component, the output signal 0''').Furthermore, if the level of the pulse signal converted from the audio signal is -1V, for example, and this is supplied to the ternary bell judgment circuit M without an echo component, the output signal Y is high level (“1”)
The remaining output signals X and Z are both low level /l/
(“0”). Furthermore, when a pulse signal converted from an audio signal, for example OV, is supplied to the ternary bell determination circuit M without an echo component, the output signal Z becomes a high level ("1"). , the remaining output signals X and Y both become low level (0'').

In order to convert the transmitted bipolar pulse signal into a uni-polar pulse signal, the output signals X and Y are
The signal is supplied to a two-person exclusive OR circuit 7. That is,
By supplying the output signals X and Y to the exclusive OR circuit 7, the output signal X or Y forms a high level (1") output signal out.
When the output signals X and Y are both at low level A/(0"), an output signal out of low level ("0") is formed. Thereby, the exclusive OR circuit 7 outputs the pulse signal converted from the audio signal. When the level is 0.5V or more (for example +IV) or -0,5V"' (for example -IV), a high level ("1") output signal out is formed, and the pulse signal converted from the audio signal is level is 0
．． When within the range of 5V and -0,5■ (for example, OV),
An output signal out of low level (0") is formed.

In the same figure, N is an equalization error detection circuit, which is an N-channel encoder MO8FET8, which is switch-controlled by the output signals X, Z, and YK, respectively.
9.10, and a comparison circuit TVO that compares the voltage supplied via the MOS FETs 8 and 9.10 with the voltage of the output signal of the addition/subtraction circuit 1. The comparison circuit TVO has (-) on its (+) input terminal.
When a voltage higher than the input terminal is applied, for example +1
．． Outputs an equalization error signal A of V (+1), and when the same voltage is applied to its (+) input terminal and (-) input terminal, outputs an equalization error signal A of 0V (0). And that(-
) When a voltage with a higher value than the (+) input terminal is applied to the input terminal, an equalization error signal A of -1V[-1] is output.

In the figure, reference numeral 0 is a current-pulse width conversion circuit, and although the detailed circuit is not shown, as described in the first embodiment, MO8FETQI to G12. Capacitor 01. It is composed of a voltage comparator circuit (2)0 and a NOR circuit G1. That is, it has the same configuration as the IC shown in FIG.

The current wires 11゜12 of the current-pulse width conversion circuit 0 are connected to three pulse width-voltage conversion circuits cv-1゜0V-2,
Coupled to 0V-3. Each pulse width-voltage conversion circuit has substantially the same configuration as each other. In the same figure,
Only one of them is shown in detail. As can be seen from the figure, each pulse width-voltage conversion circuit has almost the same configuration as the pulse width-voltage conversion circuit Ov in FIG. 1. However, in order to be able to generate a negative voltage, the source of MO8FET QI 6 is coupled to a negative voltage source Vss, unlike in FIG. As will be described later, each of the pulse width-voltage conversion circuits eV-1, eV-2, and eV-3 outputs a voltage (tap voltage) for canceling the echo component.

The output signals X and Z of the ternary bell determination circuit M are supplied to a delay circuit 11-1. The output signal of this delay circuit 11-1 is supplied to the next delay circuit 11-2, and the output signal of this delay circuit 11-2 is further supplied to a delay circuit 11-3. A shift register 11 is constituted by these delay circuits 11-1 to 11-3.

Further, each of the delay circuits 11-1. 11-2゜11-3
The output signals of the corresponding multiplication circuits 12-1, 12-2, .
12-3 10,000 input terminals and corresponding multiplication circuit 14-
1.14-2.10,000 input terminals of 14-3.

Each of the above multiplication circuits 12-1. 12-2. The equalization error signal A is supplied to the other input terminal of each of the circuits 12-3. Each multiplication circuit 12-1.12-2.12-3 receives an equalization error signal A and a corresponding delay circuit 11-
1.11-2. ．． 1. Multiply the output signal of 11-3 and send the result to the corresponding logic circuit 13og 1. I.J.
Output to Og 2+ log 3.

The above logic circuit log -1+ log -2+ IJ
Og3 is the corresponding multiplication circuit 12-1.12-2.
12-3 output signal and the above current-pulse width conversion circuit 1
0 to form pulse signals U and D, respectively, and output them to the corresponding pulse width-voltage conversion circuits 0V-1, 0V-2, and 0V-3. This logic circuit flag-L Aog -2, log-3
Although not particularly limited, they have the same configuration.

The logic circuit 11og outputs a signal obtained by inverting the phase of the pulse signal φ as the pulse signal U when the output signal from the multiplication circuit is a positive voltage.

It also outputs this low level pulse signal. When the output signal from the multiplication circuit is a negative voltage, when the pulse signal φ is output as a pulse signal, the MOIC outputs a high level pulse signal U.

Also, when the output signal from the multiplication circuit is approximately O■,
It outputs a high-level pulse signal U and a low-level pulse signal U.

The other input terminal of the multiplication circuit 14-1. 14
-3 is the corresponding delay circuit 11-I, 11-2.11-
When the output signal of 3 is high level ("1"), the corresponding pulse width-voltage conversion circuit 0V-1, CV-2, 0
The output voltage from V-3 is supplied to the adder circuit 13.

The addition circuit 13 includes the respective multiplication circuits 14-1, 14-2, .
14-3 and supplies it to the input terminal (-) of the power subtraction circuit 10.

Next, the operation of this decision feedback type automatic equalizer will be explained.

The operations include training operations and actual equalization operations.

Although the training operation is not particularly limited, it is performed before performing the actual equalization operation. In the training operation, the above three-valued bell judgment circuit M and the shift register 11
A predetermined pulse signal for training is applied to the shift register 1 and the transmission end of the transmission line. As a result, each logic circuit log −1 to lo
g-3 is each pulse width-voltage conversion circuit 0V-1 to eV-
3 cancels each echo component E1 to E3 ■2
The pulse signal U or D is output so as to form □ to Vg3. When each pulse width-to-voltage conversion circuit 0V-1>CV-3 is able to generate a voltage that can cancel out the echo components, the training operation ends and the actual equalization operation begins.

The following description will be made assuming that an input signal BTIN containing echo components E1 to E3 (symbol interference) as shown in FIG. 4 is supplied to the adder/subtractor circuit 1.

That is, the input signal BTIN consists of a signal converted from an audio signal, that is, a signal consisting of a positive main pulse MP and a subsequent ov signal as shown by the broken line in the figure, and echo components E1 to E3. It is made up of.

Also, by the training operation described above, the pulse width-voltage conversion circuit O■-1 generates a voltage ■2□ that eliminates the echo component E1, and the pulse width-voltage conversion circuit cv-2 generates a voltage ■2□ that eliminates the echo component E1.
It is assumed that the pulse width-voltage conversion circuit 0V-3 forms a voltage vg3 that cancels out the echo component E2, and a voltage 183 that cancels out the echo component E3.

Now, as shown in FIG. 4, when the main pulse MP is ternary and is supplied to the bell judgment circuit M, the voltage of this main pulse MP is higher than the reference voltage of 0.5■, so
The value level constant circuit M forms the output signal X of ノ・IREHE/I/(1'').
At the same time, the output signal OUT of 71 becomes high level C1''), and the output signal X of 71 high level C1'') is input to the delay circuit 11-1.

After a certain period of time, the output signal of the delay circuit 11-1 becomes a zero level (1"). As a result, the output voltage vg0 formed in the pulse width-voltage conversion circuit 0V-1 is The echo component E1 is supplied to the input terminal (-) of the addition/subtraction circuit 1. At this time, the echo component E1 is supplied to the input terminal (+) of the addition/subtraction circuit 1. The voltage value of the echo component E1 and the output voltage v81 are almost the same value, so
The voltage of the output signal of the addition/subtraction circuit 1 is a reference voltage of 0.5
The value will be between v and -0.5V. As a result, the output signal 2 of the ternary bell determination circuit M becomes high level ("1"). As a result, the output signal out is at a low level of 0.
''). Since the output signal X is low level (0'') and the output signal Z is high level (``1''), the delay circuit 11-1' receives a low level (``0'') signal. is applied.

Delay circuit] After a certain period of time after the output signal of delay circuit 11-1 becomes high level, the output signal of delay circuit 11-2 becomes high level ("1"). As a result, the output voltage ■8° formed by the pulse width-voltage conversion circuit 0V-2 is transferred to the Calo subtraction circuit 1 through the multiplication circuit 14-2 and the 710 multiplication circuit 13.
0 input terminal (-). At this time, the echo component E2 is supplied to the input terminal (10) of the addition/subtraction circuit.

Since the voltage value of the echo component E2 and the output voltage vg□ are almost the same value, the voltage of the output signal of the 7JD subtraction circuit 1 has a value between the reference voltage 0.5V and 10.5V. .

As a result, the three-valued bell judgment circuit M is
'') output signal 2 and low level ("O") output signals X and Y. Therefore, the output signal out becomes low level (0"). Furthermore, due to the low level (0'') of the output signal X, a low level (0'') signal is imprinted on the delay circuit 11-1.

The output signal of the delay circuit 11-2 is at the same level as )
), the output signal of the delay circuit 1]-3 becomes high level ("1"), and the output voltage formed by the pulse width-voltage conversion circuit 0-3 changes to 3. The multiplication circuit 4-3 and the addition circuit 13 are supplied to the input terminal (-) of the subtraction circuit 1. At this time, the echo component E3 is supplied to the input terminal (+) of the addition/subtraction circuit 10. Since the voltage value of the echo component E3 and the above-mentioned output voltage Vg3 are almost the same value, the three-valued bell determination circuit M distinguishes between the output signal Z at a low level (0") and the output signal Z at a low level (0").
' output signals X and Y are formed. As a result, the output signal out becomes the high level (0'').

As described above, the echo component is removed from the input signal BTIN, and a signal corresponding to the signal converted from the audio signal is obtained as the output signal out.

In the above explanation, the signal converted from the audio signal first becomes 1" and then becomes continuous ("F). For this reason, the adder circuit 13M operates so as to be supplied with only the output voltage formed by one pulse width-to-voltage conversion circuit and to transmit it to the addition/subtraction circuit 1.

Next, describe the function of the equalization error detection circuit N.

For example, when subtracting the echo component E1 and the output voltage vg1, if the voltage of the echo component E1 is higher than the output voltage v8, the input terminal (+) of the comparison circuit TVO
A voltage of the level No. 1 is applied to. Also at this time,
MO by the output signal
Since the 8FETQ9 is in the on state, 0 is applied to the input terminal (@) of the comparison circuit TVO. As a result, the comparison circuit TVC outputs a positive voltage equalization error signal A.
Output. By this equalization error signal A and the output signal of -I level of the delay circuit 11-1, the multiplication circuit 12-1
outputs a high V output signal to the logic circuit log -1. As a result, the logic circuit log-1 outputs the pulse signal U, which is the phase-inverted pulse signal φ, for a certain period of time as described in the first embodiment. As a result, the output voltage V8□ of the pulse width-voltage conversion circuit 0V-1 increases, and the difference between it and the voltage value of the echo component E1 is reduced.

On the other hand, if the output voltage ■2□ is higher than the voltage value of the echo component E1, the input terminal (, -
) The voltage applied to K is higher than the voltage applied to the input terminal (+). Therefore, the equalization error signal A is
The voltage becomes negative, and a negative output signal is applied to the logic circuit 1Joz-1. As a result, the logic circuit log-1 supplies a pulse signal corresponding to the pulse signal φ to the pulse width-voltage conversion circuit CV-t for a certain period of time. As a result,
As described in Example 1 above, the pulse width-voltage conversion circuit e
The voltage value of the output voltage vg□ of V-1 decreases, and the difference between it and the echo component E1 is reduced.

Furthermore, when the echo component E1 and the output voltage ■2□ have the same value, the equalization error signal A becomes almost 0■, so the logic circuit 7og-1 outputs the high-level pulse signal U and the low-level pulse signal output. This allows MO8FET
QI 3. Ql 6 turns off, and the output voltage ■8□
The value of does not change.

Other output voltages vg□, ■g3 and echo components E2゜E3V
Even if c, the equalization error detection circuit N operates in the same way as described above, and the difference between the echo component and the corresponding output voltage is reduced.

Note that although FIG. 3 shows a circuit that excludes echo components only for the positive signal (main pulse MP),
Even for negative signals, echo components can be removed by providing a circuit similar to that described above. That is, the shift register receiving the output signal Y, the multiplication circuit 1
2-1 to 12-3. Multiplication circuits corresponding to 14-1 to 14-3, logic circuits corresponding to the logic circuits log-1 to log-3, and pulse width-voltage conversion circuits 0V-1 to 0.
A pulse width-voltage conversion circuit corresponding to V-3 and a force n calculating circuit corresponding to the adding circuit 13 are provided, and the output voltage of this adding circuit is converted to the output voltage of the adding circuit 1. What is necessary is to supply it to the input terminal (+).

The third-order echo component, that is, the echo component E3, is
That level is as small as several tens of mV. The voltage generation circuit shown in Figure 1 (a voltage generation circuit composed of a current-pulse width conversion circuit 0 and a pulse width-voltage conversion circuit C) is used as a voltage source to cancel the echo component. By using this, it is possible to form a voltage that is highly accurately approximated to the echo component whose level is small, so that a highly accurate equalization operation can be performed. That is, it is possible to form a very small voltage that is not affected by fluctuations in the power supply, so that highly accurate equalization operation can be performed.

In this embodiment, one current-pulse width conversion circuit is provided in common for three pulse width-voltage conversion circuits. This attempts to reduce the number of elements.

[Embodiment 3] FIG. 5 shows a circuit diagram of an embodiment in which the present invention is applied to an offset canceling circuit of a Miller integrating circuit.

In this embodiment, an operational amplifier circuit OF, a capacitor C provided between its inverting input (-) and the output terminal OUT, and a capacitor C provided between the inverting input (-) and the input terminal IN. The resistor R constitutes a Miller integration circuit. In order to remove the offset of the operational amplifier circuit OP, the voltage vg generated by the voltage generating circuit VG similar to the embodiment shown in FIG.
). Normally, the operational amplifier circuit OF generates an output signal even if its pair of input levels are equal to each other. That is, the operational amplifier circuit has a so-called office. This occurs because, for example, the operational amplifier circuit includes a differential amplifier circuit, and the characteristics of bare elements, such as a pair of MOSFETs, forming the differential amplifier circuit do not match each other due to variations in manufacturing conditions. Therefore, due to the offset of the operational amplifier circuit, the integrator circuit
It has the disadvantage that the input signal cannot be integrated to a high N degree. To remove such offsets, the voltage generating circuit VG as described above is used.

That is, since the above-mentioned offset is usually a very small voltage of several tens of mV, a very small voltage vg corresponding to this offset voltage is formed using the control signals Up and Down and is supplied to the non-inverting input (+) side. By doing so, the offset can be achieved.

Note that in order to reduce power consumption, the voltage generating circuit VG may be operated only when an input signal to be integrated is supplied. The polarity of the minute voltage vg is set according to the polarity of the offset of the operational amplifier circuit.

〔effect〕

(1+) The capacitor is charged or discharged by a current proportional to the reference current for a time inversely proportional to the reference current, and the output voltage is formed based on the voltage held in the capacitor. Even if the current changes, the time for charging or discharging the capacitor changes in inverse proportion to the change in the reference current, and the current for charging or discharging the capacitor changes in proportion to the change in the reference current. The voltage held in the capacitor during charging or discharging is almost unaffected by changes in the reference current.Therefore, a precisely controlled output that is unaffected by fluctuations in the reference current. The effect is that a voltage can be generated.

(2) By performing the charging and discharging operations on the capacitor for a time inversely proportional to the reference current and with a current proportional to the reference current, the amount of charge charged to the capacitor and the amount of charge discharged are Since the current held in the capacitor is virtually unaffected by fluctuations in
By forming the output voltage based on the voltage, it is possible to form a highly precisely controlled pulsed output voltage that is not affected by fluctuations in the reference current.

(3) By using a P-channel type MO8F'ET and an N-channel type MO8F'ET as a switch means for switching between charging and discharging the capacitor, which forms an output voltage based on the holding voltage. , the change in the holding voltage of the capacitor caused by the feedthrough of the P-channel MO8FET, and the change in the holding voltage of the capacitor caused by the feedthrough of the P-channel MO8FET, and the
Since the change in the holding voltage of the capacitor caused by the feedthrough of the FET can be made to change in different directions, for example, when forming an output voltage that should be constant, the level can be gradually changed to positive or negative. If you can reduce the problem of storing things away, you will get a ℃/cold effect.

(4) A P-channel type MO with approximately the same dimensions as a switching means for switching between charging and discharging a capacitor, which forms an output voltage based on its holding voltage.
By using 8FET and N-channel type MO8, F''ET, P-channel type MOSFET
The change in the holding voltage of the capacitor caused by the feedthrough of the T and the change in the holding voltage of the capacitor caused by the feedthrough of the N-channel MO8FET can be made to change by approximately the same value in different directions, for example. When forming the desired output voltage, it is possible to prevent the problem of the level gradually changing to positive or negative.

(5) Since a voltage generation circuit that can form an output voltage that is not affected by fluctuations in the reference current can be obtained, by applying this to a voltage generation circuit for canceling the echo component of a line equalizer for a digital telephone, transmission The effect is that it is possible to obtain an equalizer that can reliably reduce echo components from the pulse signal that is generated.

(6), depending on the ratio of the proportionality constant α between the first current and the second current to the proportionality constant β between the first current and the third current, and the capacitance value of the capacitor. Since the value of the output voltage can be adjusted in determined microvoltage units, by appropriately setting the ratio of the above constants, the capacitance value of the capacitor, or both, it is possible to form a small microvoltage and also finely adjust the value of the output voltage. You can get the effect that you can.

(7), the first current and the second current formed based on this
in minute voltage units determined by the ratio of the proportionality constant α between the current and the proportionality constant β between the first current and the third current formed based on this, and the capacitance value of the capacitor. Since the value of the output voltage can be adjusted, by appropriately setting the ratio of the above-mentioned constants, the capacitance value of the capacitor, or both, a small microvoltage can be generated and the value of the output voltage can be finely adjusted. In addition, the voltage that is formed is not determined by the value of the current, but by the proportionality constant α and βθ ratio.
Since it is determined by the capacitance value of the capacitor, it is possible to form a voltage that is almost unaffected by current fluctuations.

(8) Since the voltage generation circuit can be configured with MOSFETs,
The advantage is that it can be used with a voltage generating circuit that is suitable for a semiconductor integrated circuit device.

(9) Since it is possible to form a minute voltage with high precision to remove the offset of the operational amplifier circuit that constitutes the integrating circuit, it is possible to provide a Miller integrating circuit that can perform highly accurate integrating operation. It will be done.

(10), the first capacitor is used to form a signal with a pulse width inversely proportional to the fluctuation of the base current, and the second gear capacitor is charged or discharged during the pulse width. If they are formed at the same time, the capacitance ratio between the first capacitor and the second capacitor will hardly change even if there are variations in manufacturing conditions. Therefore, if the capacitance value of the second capacitor changes due to variations in manufacturing conditions, and the pulse width changes as a result, the time for charging or discharging the second capacitor will change; Since the value changes in the same way as the capacitance value of the first capacitor, the holding voltage of the second capacitor determined by charging or discharging hardly changes due to variations in manufacturing conditions. Therefore, by setting the voltage based on the holding voltage of the second capacitor as its output voltage, it is possible to obtain a voltage generating circuit with a high manufacturing yield.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the circuit shown in FIG. 1 above, simply resetting the discharge circuit of capacitor C2,
The MO8FET for the node may be used, and only the charging voltage to the capacitor C2 may be used as the output voltage. In this case, a sample and hold circuit may be provided as an output circuit to receive this voltage and convert it into a static voltage signal. Furthermore, the specific circuits constituting each of the current sources described above can take various embodiments. Further, the reference voltage Vref may be a voltage whose value changes according to fluctuations in the voltage.

[Application field]

The present invention is not limited to the above-mentioned embodiments, but can be widely used as a voltage generating circuit that generates a highly precisely controlled voltage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. FIG. 4 is a block diagram showing an embodiment of the invention when applied to an automatic equalizer, FIG. 4 is a waveform diagram for explaining its operation, and FIG. 5 is an embodiment of the invention when it is applied to a Miller integration circuit. FIG. 2 is a circuit diagram showing an example. Vo, 2. 3...Voltage comparison circuit, OP...Operation amplifier circuit, LOG...Combined logic circuit, M...Three value and bell judgment circuit, 11...Shifton register, ■G...
・Voltage generation circuit, 10... current-pulse width conversion circuit,
Cv...Pulse width-voltage conversion circuit, N...Equalization error detection circuit. Figure 1 Figure 2 Melo W Le

Claims (1)

[Claims] 1. A reference current generation circuit, a first current source that generates a current according to the reference current, and a first current source that receives a clock signal and supplies the current of the current source to the capacitor C1. A switch MO8FET, a logic gate circuit that forms a signal with a pulse width commensurate with the phase difference with this capacitor signal, a second current source that forms a current according to the reference current, and an output of the logic gate circuit. a second switch MO that receives the signal and supplies the current of the second current source to the capacitor C2;
8FET and a discharge circuit that discharges the voltages held in the capacitors CI and C2 at predetermined timings, the voltage generation circuit is characterized in that the voltage held in the capacitor C2 can be output. 2. The discharge circuit of the capacitor C2 is composed of a third current source that flows a discharge current set to the same value as the current value of the second current source, and a third switch MO8FET,
The second switch MO8FET and the third switch MO
2. The voltage generating circuit according to claim 1, wherein each of the 8FETs is controlled by a two-phase pulse signal formed by the output signal of the logic gate circuit. 3. The first to third current sources are current mirror MOs.
3. The voltage generating circuit according to claim 1, wherein the voltage generating circuit is constituted by 8F'ET. 4. The second switch MO8FET is a MOS whose field through occurs in the direction of increasing the output voltage.
The third switch MO8FET is a MOSFET whose field through occurs in the direction of decreasing the output voltage. Voltage generation circuit. 5. The above output voltage is the control voltage source of the decision feedback type automatic equalizer in the line equalizer for the gauge Talto telephone and 1. Claim 2 is characterized in that it is used for
, the voltage generating circuit according to item 3 or 4. 6. The second switch MO8FET and the third switch MO8FET are of different conductivity types,
6. The voltage generating circuit according to claim 4, wherein the voltage generating circuit has substantially the same dimensions.