JPS59213283A - Drive circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit that uses field effect transistors for high-speed switching of an inverter, and an object thereof is to provide a drive circuit that does not malfunction.

FIG. 1 shows the configuration of a conventional inverter switching circuit.

This inverter is driven by a direct current 'Ichihara E4, and is connected in series with n-channel type Ml and M2k using field effect transistors (hereinafter referred to as i7MO8FETs and denoted by the symbol M in the explanation). Connection point a
A load is connected between this and ground.

In FIG. 1, only the driving times of M1 of the positive arm are shown, and the configuration and operation thereof will be explained.

The oscillator of the signal v1 that drives M+'c is the pulse transformer T.
A rectifying and smoothing circuit consisting of a diode D1 and a capacitor CI% is connected to the output side j of the pulse transformer, and the output end of the smoothing circuit is an NPN
It is connected between the base and emitter of transistor Q. The collector terminal of the transistor Q+ is a MOSFE
The north terminal of T Ml is connected to a positive DC voltage E+ which brings it to the gold reference level ili, and the emitter terminal is connected to the gate terminal of Ml.

The emitter connected to the gate terminal of Ml is connected on the one hand via point b to a negative DC voltage E2, which makes the north terminal of Ml a reference voltage, via a resistor 2.

The general operation of this drive circuit is as follows.

, when the drive signal Vl is zero, the disk Q1 is in a non-conducting state, and the voltage between the sources is v, and the voltage between the sources is v, and the negative voltage is M is in a non-conductive state.

Kaku81. IIl information■When 1 is a high frequency/cross signal,
・An output appears on the lance T1, is passed through the die D1, and is smoothed by the condenser C2.
1. ) N1・7:/When the voltage between the base and emitter of 7Q+ is about 0.7V, the transistor Q
1 is conductive 7, this nK, 1 is the heavy pressure between the gate and source of M, that is, the '71 pressure V between b and 3, - becomes a positive voltage E1, and Ml becomes conductive.

As shown in Figure 1, the M
If I and Ml of the negative arm are both conductive at the same time, it will cause a short circuit in the power supply, so it is unavoidable.

In the conventional drive circuit shown in Fig. 1, (rL
, often MI ,! :The occurrence of this malfunction is explained by referring to Figure 2 +:11.

I will clarify.

α position V1 of point a, that is, MI, source A14 of Ml
Child 1-it position is load L (7) K position 1) J a VC
If maintained: l'L-c, both Ml and Ml are in a non-conducting state.

The resistor Q1 is also in a non-conducting state, and the heavy pressure \' ba is equal to the negative voltage I.-2.

At this time, when Ml changes to a conductive state, the potential V at point a drops to zero, as shown in (1) in Fig. 2, and the heavy pressure Vb-,
) until O fixed at le 2, position f'tt of point b is a
It changes according to the change in the point's value.

Since the switching speed of Ml is extremely fast, the potential change dv, /di is extremely large.On the other hand, there is an f1 drift shown by C3 in the drive circuit of Fig. 1, so ( 2), C3・(jV, /
If cN=il, the current flows into the pace of transistor Q, and Ql
becomes conductive, and as shown in (3) in Fig. 2, while Narita Vb-a maintains the positive voltage EI, albeit for a short time, Ml becomes conductive, resulting in the worst lifting platform error. A short circuit will occur, which will damage elements such as MO8Fj.

,I'! FIG. 3 is a modification of the conventional example shown in FIG. 1st
It is different from the figure, in figure 1 it is NPN) transistor Q,
is inserted into the circuit of positive voltage El, whereas
In the figure, only the PNP l-transistor (U2) is inserted into the circuit of negative 'it pressure I'62.

The effect is therefore that when transistor Q2 becomes conductive, a negative voltage E2 is applied to the gate of MI.

This one deception, 1V11. Both Mz and I are in a non-conducting state, and point a, V, maintains the bottom position of the load, and p
:NPl-ra/register Q is conductive, and the MI gate is in a conductive state.
1... A negative voltage E2 is applied to the source voltage V, .

When Ml changes to a conductive state, Q2 changes to a non-conductive state (~, Vb-1 becomes a positive upper pressure E).

Vb- is the zero point 4 E, M + Surenon Yuhold l
; After reaching this point for a while, Ml begins to shift to the conductive state 1,
As shown in Fig. 4, the 1st and 1st f1γ of a1 and 1) move upward from 1u of L to 1μ current W and HiI ball to: 4 and start. Due to the large change in the potential V at point a and the presence of stray capacitance C4 in the drive circuit, the emitter of the PNP transistor (, l!2)
Voltage Lf-change dv between the base and the series connection of stray capacitance 04
, /dl acts. Therefore, (to the emitter of 2).

dV, 7dI flows into 4 currents iz corresponding to 1 (, 1). Therefore, Q2 transitions to a conductive state, and the heavy pressure V b - becomes Q,
? Ti LIE, E 2 adds υ9, result of 7,
Ml becomes non-conductive (transfers to a phantom level, and Shigenobu aton returns to the potential of P'' and the load. At this point, Shigenobu's change at point a is dV, /d
t becomes Q, j(), current 1z becomes zero, transistor Q2 moves to the non-four-in state, and Vb-a begins to rise to the positive rhi pressure E1 by one ear.

This leads to a Mild conductive state, and as shown in FIG. 4, F11 repeats a conductive state and a non-conductive state, resulting in a so-called small generation state.

In this way, the drive circuit shown in FIG.
FJ! : Produces a 'J' motion.

This invention L- prevents malfunctions caused by stray capacitance existing in the drive circuit by connecting the PH2 transistor in full series to the NPN transistor used in the drive circuit for driving the MO8FET. be.

Next, the structure and operation of the present invention using the embodiments shown in the drawings,
Explain the effect.

FIG. 5 shows an example in which the present invention is fully implemented in the conventional drive circuit shown in FIG.

The difference in Fig. 5 from Fig. 1 is that the PNPI-transistor Q3
and its emitter 'kNPN+- transistor Q
1 emitter, collector to MO8FETM+ gate terminal, base? 'M-column connection of the NPN transistor Q+ and PNP transistor Q3 is configured in the drive circuit by connecting them to the output terminals of the transformer Tl, respectively.

Next, the entire operation of the inventive circuit will be explained.

When MI, M, and 2 are all in a non-conducting state, point Ii at point a; V1 maintains the full potential of the load, the output of the pulse transformer T+ is zero and Q,+ is in a non-conducting state, and 81. game
]...North, substitute, i.e. 1)-al;;1rb.

The voltage V b -s is a negative voltage ■.]2.

Next, when M2 transitions to a conductive state, ILl at point a
t7: V falls to zero, and this rapid potential change dV,/d
i and the floating 'f existing in the drive circuit; jtjC3
The current +1 that is about to be generated due to
Since CIu is stopped and the synchronizers Q+ and Q3 are not conductive, no malfunction of M1 occurs.

FIG. 6 shows a conventional circuit similar to that shown in FIG. 3 when the present invention is implemented.

・Different from Figure 3 is PNI,) l-transistor 0.
Add an NPN transistor Q4'r to 2 and connect its emitter k to the emitter of 2, the collector to the gate terminal of Ml, and the base to the diode f) +
respectively to the output terminals of pulse transformer T1 through
This is a consistent point.

Next, the operation of this circuit will be briefly explained.

When MI transitions from a non-conducting state to a conducting state, the potential change dv,/dt of a4 and the stray capacitance C of the drive circuit
The generation of current 12 caused by
will not malfunction.

FIG. 7 shows another embodiment of the drive circuit of the present invention, in which a driver consisting of one stage of NPN transistor Q5 and PNP transistor Q6 is provided between the gate of MI and the drive circuit. be.

FIG. 8 shows a diode Dz k provided between the emitters of an NPN transistor Q1 and a PNP transistor Q3.

FIG. 5 shows the effects of the two embodiments described in -1-.

Embodiment shown in FIG. 6 and prevention of malfunction of synchronizer 11-
It is similar in that respect.

According to the present invention, P
N I) These two transistors are conductive only when current flows through the bases of the transistors, otherwise they are not conductive, but the MO8F'ET isolating if
, the wakefulness caused by the potential change of the so-suf 1.1 element and the f-7 free capacitance of the drive circuit that occurs during a powerful performance.
JIO8P+ without UL being applied to the transistor
・：Oscillation due to T malfunction and short circuit of the rh source are prevented, which produces a great effect.

[Brief explanation of the drawing]

,,'4Y1 is a small diagram of an example of a conventional drive circuit,
Figure 2 is a week chart showing the change in the main flow, "I", that occurs on path 111 in Figure 1, and Figure 3 is another example of the conventional drive circuit.
91J, Figure 4 shows the potential generated in the circuit of Figure 3,
'(Diagram showing changes in LθIU, Figures 5 to 8 are drive circuit diagrams showing non-inventive embodiments. J...] DC Ij2 source, L... Load, M... ... Mosfe, Nodo, Q+, Q6...NPN transistor, (Table 2 + Q3 +yii + Q5...PN
P t-lanogister, 'I゛1...Pulse 7g Spear 3 Rohm S Figure 3 Figure 9 Figure 8

Claims (1)

[Claims] 16 In an inverter incorporating two field effect transistors connected in series as switches, an N
A PN transistor and a PNP) transistor have their respective emitters connected in series, one collector connected to the gel terminal of the field effect transistor, the other collector connected to the source terminal, and a drive signal output circuit connected between the pace terminals. A drive circuit characterized by being connected.