JPS5921168B2 - Manufacturing method for semiconductor integrated circuits - Google Patents
Manufacturing method for semiconductor integrated circuitsInfo
- Publication number
- JPS5921168B2 JPS5921168B2 JP56152089A JP15208981A JPS5921168B2 JP S5921168 B2 JPS5921168 B2 JP S5921168B2 JP 56152089 A JP56152089 A JP 56152089A JP 15208981 A JP15208981 A JP 15208981A JP S5921168 B2 JPS5921168 B2 JP S5921168B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- bonding
- wire
- chip
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/49173—Radial fan-out arrangements
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/491—Disposition
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/01014—Silicon [Si]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、半導体集積回路の製法に関し、特に、超音波
ボンディング法によつて半導体チップとワイヤとを接続
するための半導体集積回路の製法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a semiconductor integrated circuit for connecting a semiconductor chip and a wire by an ultrasonic bonding method.
半導体集積回路では、シリコン・チップと外部リードと
を接続するためのボンディング・パッドが必要である。Semiconductor integrated circuits require bonding pads to connect silicon chips and external leads.
このパッド１は、通常第１図Ａに示すように、チップ２
の周辺部すなわち回路素子領域３の外側に形成されてお
り、その形状は正方形である。そしてパッド１とリード
との接続は、Ａｕ、Ａｌ等の細線（ワイヤ）を用い、そ
の結線には熱圧着法あるいは超音波ボンディング法が利
用される。ここで、特に超音波ボンディングの場合、振
動子からホーンを介して伝達される超音波エネルギーは
、その振動方向をワイヤの長さ方向に設定される。This pad 1 is usually connected to the chip 2 as shown in FIG. 1A.
It is formed on the periphery of the circuit element region 3, that is, on the outside of the circuit element region 3, and has a square shape. The pad 1 and the lead are connected using a thin wire made of Au, Al, etc., and a thermocompression method or an ultrasonic bonding method is used for the connection. Here, particularly in the case of ultrasonic bonding, the vibration direction of the ultrasonic energy transmitted from the vibrator via the horn is set in the length direction of the wire.
このため、ボンディング個所４ａにおけるワイヤ４の形
状は、第１図Ｂに拡大して示すように、ワイヤ４の直径
方向の長さがワイヤ直径ｄの２倍程度になるに対し、そ
の長さ方向では５〜７倍程度となる。従つて、上記ボン
ディング部４ａのワイヤ４の一部がパッド１外に達する
ことがあり、その場合ワイヤ４とパッド１との接着面積
が小さくなりその接着強度が低下してしまう。なお、こ
の接着強度低下の問題点を考慮して、従来一般にはパッ
ド１の面積を大きくすることが行なわれている。しかし
、その形状自体は正方形であるためパッド１が必要以上
に大きくなり、チップ２の集積密度を低下している。従
つて、本発明の目的は、超音波ボンディングにおいて、
デバイスの集積密度を低下することなく、リード細線と
パッドとの接着強度を増すことにある。For this reason, the shape of the wire 4 at the bonding point 4a is such that, as shown in an enlarged view in FIG. It will be about 5 to 7 times larger. Therefore, a part of the wire 4 of the bonding portion 4a may reach outside the pad 1, and in that case, the bonding area between the wire 4 and the pad 1 becomes small and the bonding strength thereof decreases. Note that, in consideration of this problem of a decrease in adhesive strength, conventionally, the area of the pad 1 has generally been increased. However, since the shape itself is square, the pad 1 becomes larger than necessary, reducing the integration density of the chip 2. Therefore, an object of the present invention is to provide ultrasonic bonding with
The object is to increase the adhesive strength between the lead wire and the pad without reducing the integration density of the device.
このため本発明によれば、四角形の半導体チップの周辺
部に複数のボンデイングパツドを設け、該複数のボンデ
イングパツドのそれぞれに超音波ボンデイング法によつ
てワイヤを接続する半導体集積回路の製法において、前
記各ボンデイングパツドを、その相対抗する二辺が互い
に平行となり、その二辺の長さがそれら二辺と直角な方
向の幅よりも大きくなるように形成し、前記複数のボン
デイングパツドのうち、前記半導体チツプのコーナー部
に近接するものを、そのパツドの長さ方向が前記半導体
チツプの一辺を直角でない角度で横切るとともに、前記
半導体チツプのほぼ中央部に向う方向に延在するように
配置し、前記超音波ボンデイング法による接続時に、前
記ワイヤの長さ方向と前記パツドの長さ方向とを一致さ
せ、かつ、超音波の振動方向が前記パツドの長さ方向に
一致するように超音波を前記パツド上のワイヤに印加す
ることを特徴とする。Therefore, according to the present invention, in a method for manufacturing a semiconductor integrated circuit, a plurality of bonding pads are provided around the periphery of a rectangular semiconductor chip, and a wire is connected to each of the plurality of bonding pads by an ultrasonic bonding method. , each of the bonding pads is formed so that two opposing sides thereof are parallel to each other, and the length of the two sides is greater than the width in a direction perpendicular to the two sides, and the plurality of bonding pads are Among the pads, those near the corner portions of the semiconductor chip are arranged such that the length direction of the pads crosses one side of the semiconductor chip at an angle other than a right angle, and extends in a direction toward approximately the center of the semiconductor chip. and so that when connecting by the ultrasonic bonding method, the length direction of the wire matches the length direction of the pad, and the vibration direction of the ultrasonic wave matches the length direction of the pad. The method is characterized in that ultrasonic waves are applied to the wire on the pad.
以下、本発明の超音波ボンデイング用パツドの１実施例
を第２図Ａ，Ｂと共に説明する。Hereinafter, one embodiment of the ultrasonic bonding pad of the present invention will be described with reference to FIGS. 2A and 2B.
第２図ＡおよびＢはそれぞれ本発明のパツドを備えたチ
ツプの上面図およびそのボンデイング部の拡大図である
。FIGS. 2A and 2B are a top view and an enlarged view of a bonding portion of a chip with a pad of the present invention, respectively.
第２図Ａ，Ｂに示す本発明の実施例では、シリコン・チ
ツプ２上、回路素子領域３の外周辺部に長方形状のアル
ミニウム・パツド１１，１２，・・・１（ｎ−１），１
ｎを形成している。In the embodiment of the present invention shown in FIGS. 2A and 2B, rectangular aluminum pads 11, 12, . . . 1 (n-1), 1
forming n.
各パツド１１，１２，・・・１（ｎ−１），１ｎのたて
、よこの長さＰ，ｑは、前記したボンデイング部の形状
を考えて例えばワイヤ４の直径ｄの３倍および８倍程度
にそれぞれ設定される。しかも長い方のよこ方向はすべ
てチツプ２の中心０に向かつている。さて、パツケージ
に取り付けたチツプ２のアルミニウム・パツド１１〜１
ｎとパツケージの外部リード線とをワイヤ・ボンデイン
グする場合、先ず超音波印加用チツプの先端と各パツド
１１〜１ｎとの位置合わせ（アライメント）を行なう。The vertical and horizontal lengths P and q of each pad 11, 12, . . . 1(n-1), 1n are, for example, three times the diameter d of the wire 4 and Each is set to about double the amount. Moreover, all the long sides in the horizontal direction are directed toward the center 0 of the chip 2. Now, aluminum pads 11-1 of chip 2 attached to the package cage.
When performing wire bonding between the pads 11 to 1n and the external lead wires of the package, first, the tip of the ultrasonic wave applying chip and each of the pads 11 to 1n are aligned.
この際、超音波印加用チツプは固定されており、従つて
シリコン・チツプ２上のパツド１１〜１ｎをＸ，ｙ，θ
方向に移動してアライメントが行なわれる。こうして、
例えばパツド１（ｎ−１）のアライメントが終了した段
階で、そのパツド１（ｎ−１）上のワイヤ４に超音波が
加えられ、ワイヤ４とパツド１（ｎ−】）との接続が行
なわれる。この場合、パツド１（ｎ−１）は、第２図Ｂ
に示すように、長い方のよこ方向が、印加される超音波
の振動方向と一致しているため、ボンデイング部４ａは
パツド１（ｎ−１）からはみ出ることがない。次に、パ
ツド１（ｎ−１）の隣りのパツド１ｎの接続を行なうに
際し、そのアライメントを行なう。その場合、パツド１
ｎの長手方向がシリコン・チツプ２の中心０に向いてい
るため、チツプ２を角度θｎだけ回転移動した後でＸ，
ｙ方向の位置修正をずれば良い。従つてそのアライメン
ト自体は非常に簡単であり、しかもアライメントが終了
した状態ではパツド１ｎの長い方のよこ方向が、印加す
る超音波の振動方向と一致しているため、パツド１（ｎ
−１）の場合と同様ボンデイング部がパツド１ｎ外には
み出ることがない。このように、上記実施例では、アラ
イメントをしやすくするため、各パツド１１〜１ｎの長
い方のよこ方向をチツプ２の中心に向かうようにしてい
る。At this time, the ultrasonic wave application chip is fixed, so the pads 11 to 1n on the silicon chip 2 are
Alignment is performed by moving in the direction. thus,
For example, when alignment of pad 1 (n-1) is completed, ultrasonic waves are applied to wire 4 on pad 1 (n-1) to connect wire 4 and pad 1 (n-]). It will be done. In this case, pad 1 (n-1) is
As shown in FIG. 2, since the longer horizontal direction coincides with the vibration direction of the applied ultrasonic waves, the bonding portion 4a does not protrude from the pad 1(n-1). Next, when connecting pad 1n adjacent to pad 1(n-1), alignment is performed. In that case, pad 1
Since the longitudinal direction of n is directed toward the center 0 of the silicon chip 2, after rotating the chip 2 by an angle θn,
It is sufficient to shift the position correction in the y direction. Therefore, the alignment itself is very simple, and when the alignment is completed, the longer horizontal direction of the pad 1n matches the vibration direction of the applied ultrasonic wave, so the pad 1(n
As in the case of -1), the bonding portion does not protrude outside the pad 1n. As described above, in the above embodiment, the longer side of each pad 11 to 1n is directed toward the center of the chip 2 in order to facilitate alignment.
これによつて、超音波ボンデイング時のアライメントを
しやすくする。特に、アライメントをよりしやすくする
には、上記第２図Ａに示す各パツドｔ１〜１ｎの位置を
、チツプ２の中心０から一定の距離だけ離れるように設
定すれば良い。さらに、本発明によれば、半導体ペレツ
トの中心部に対して放射状に延在する方向と同一方向に
ボンデイングパツドの両端部が延在することになるので
、半導体ペレツトの周辺部にパツドを密集して形成せし
め、これらに対して多くのワイヤを接続させることを可
能にする。これは、特に、半導体ペレツトのコーナ部に
おいてパツドを密集させて、かつ、そのコーナ部の外周
辺に沿つて外部引出しリードを位置させることができる
ので、特に、大規模の半導体集積回路において、多くの
接続ワイヤを設ける場合に有利である。上述のように、
本発明の超音波ボンデイング用パツドによれば、パツド
自体の面積を必要以上には大きくする必要がなく、デバ
イスの集積密度を向上する上で効果があり、しかもボン
デイング部がパツド外にはみ出ることが防止できるため
、相対的にその密着強度を増すことができる。This facilitates alignment during ultrasonic bonding. In particular, in order to facilitate alignment, the positions of the pads t1 to 1n shown in FIG. 2A may be set apart from the center 0 of the chip 2 by a certain distance. Furthermore, according to the present invention, since both ends of the bonding pad extend in the same direction as the direction in which it extends radially with respect to the center of the semiconductor pellet, the pads can be densely arranged around the periphery of the semiconductor pellet. This allows many wires to be connected to them. This is particularly useful in large-scale semiconductor integrated circuits because pads can be densely packed in the corners of semiconductor pellets and external leads can be positioned along the outer periphery of the corners. This is advantageous when connecting wires are provided. As mentioned above,
According to the ultrasonic bonding pad of the present invention, there is no need to increase the area of the pad itself more than necessary, and it is effective in improving the integration density of devices, and furthermore, the bonding part does not protrude outside the pad. Since this can be prevented, the adhesion strength can be relatively increased.
第１図Ａ，Ｂはそれぞれ従来のパツドおよびそのボンデ
イング部を示す図、第２図Ａ，Ｂはそれぞれ本発明の超
音波ボンデイング用パツドを備えたチツプの上面図およ
びそのボンデイング部の拡大図である。
１，１１〜１ｎ・・・・・・アルミニウム・パツド、２
・・・・・・シリコン・チツプ、３・・・・・・回路素
子領域、・・・・・・ワイヤ、４ａ・・・・・・ボンデ
イング部。FIGS. 1A and 1B are views showing a conventional pad and its bonding part, respectively, and FIGS. 2A and 2B are a top view and an enlarged view of the bonding part of a chip equipped with the ultrasonic bonding pad of the present invention, respectively. be. 1,11~1n・・・Aluminum pad, 2
... Silicon chip, 3 ... Circuit element area, ... Wire, 4a ... Bonding part.
Claims (1)
グパッドを設け、該複数のボンディングパッドのそれぞ
れに超音波ボンディング法によつてワイヤを接続する半
導体集積回路の製法において、前記各ボンディングパッ
ドを、その相対抗する二辺が互いに平行となり、その二
辺の長さがそれら二辺と直角な方向の幅よりも大きくな
るように形成し、前記複数のボンディングパッドのうち
、前記半導体チップのコーナー部に近接するものを、そ
のパッドの長さ方向が前記半導体チップの一辺を直角で
ない角度で横切るとともに、前記半導体チップのほぼ中
央部に向う方向に延在するように配置し、前記超音波ボ
ンディング法による接続時に、前記ワイヤの長さ方向と
前記パッドの長さ方向とを一致させ、かつ、超音波の振
動方向が前記パッドの長さ方向に一致するように超音波
を前記パッド上のワイヤに印加することを特徴とする半
導体集積回路の製法。1. In a method for manufacturing a semiconductor integrated circuit in which a plurality of bonding pads are provided on the periphery of a rectangular semiconductor chip and a wire is connected to each of the plurality of bonding pads by an ultrasonic bonding method, each of the bonding pads is connected to its phase. The bonding pads are formed so that two opposing sides are parallel to each other, the length of the two sides is greater than the width in the direction perpendicular to the two sides, and one of the plurality of bonding pads is close to a corner of the semiconductor chip. The pad is arranged so that the length direction of the pad crosses one side of the semiconductor chip at a non-right angle, and extends in a direction substantially toward the center of the semiconductor chip, and the connection is performed by the ultrasonic bonding method. At times, ultrasound is applied to the wire on the pad so that the length direction of the wire matches the length direction of the pad, and the vibration direction of the ultrasound waves matches the length direction of the pad. A method for manufacturing a semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56152089A JPS5921168B2 (en) | 1981-09-28 | 1981-09-28 | Manufacturing method for semiconductor integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56152089A JPS5921168B2 (en) | 1981-09-28 | 1981-09-28 | Manufacturing method for semiconductor integrated circuits |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49124394A Division JPS5150661A (en) | 1974-10-30 | 1974-10-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5795642A JPS5795642A (en) | 1982-06-14 |
| JPS5921168B2 true JPS5921168B2 (en) | 1984-05-18 |
Family
ID=15532801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56152089A Expired JPS5921168B2 (en) | 1981-09-28 | 1981-09-28 | Manufacturing method for semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5921168B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5404047A (en) * | 1992-07-17 | 1995-04-04 | Lsi Logic Corporation | Semiconductor die having a high density array of composite bond pads |
| JP2002324798A (en) * | 2001-04-25 | 2002-11-08 | Nissan Motor Co Ltd | Electrode structure |
| JP5634033B2 (en) | 2008-08-29 | 2014-12-03 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Resin-sealed semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5113009Y2 (en) * | 1971-02-05 | 1976-04-07 |
-
1981
- 1981-09-28 JP JP56152089A patent/JPS5921168B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5795642A (en) | 1982-06-14 |
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