JPS59210671A - silicon thin film field effect transistor - Google Patents

Abstract

PURPOSE:To obtain low threshold voltage and high mutual conductance by constituting a gate insulating film by laminates of a SiO2 thin-film and a Ta2O5 thin-film formed on the SiO2 thin-film through a sputtering method. CONSTITUTION:A Si thin-film 2 is deposited and formed on an amorphous insulating substrate 1. N type source region 3 and drain region 4 are formed to the thin-film 2. A gate electrode 7 is shaped on a region 5 between these regions 3 and 4 through gate insulating films 6. A source electrode 8 and a drain electrode 9 are formed on the substrate 1. In said constitution, the films 6 are constituted by a SiO2 thin-film 10 shaped brought into contact with the region 5 and a Ta2O5 thin-film 11 shaped on the thin-film 10 through a sputtering method. Consequently, the interface between the region 5 and the films 6 has only small charge density because positive charges in the thin-film 10 and negative charges in the thin-film 11 cancells each other out, accordingly, threshold voltage is extremely low. A FET displays high mutual conductance because the films 6 have the thin-film 11 and its permittivity is high.

Description

[Detailed description of the invention]

In the present invention, a silicon thin film is formed on an amorphous insulating substrate.
A source region and a drain region are formed in the silicon thin film, and a gate insulating film is formed on the region between the source region and the train region of the silicon thin film.
Regarding the improvement of silicon thin film field effect transistors having a structure in which a gate voltage is arranged in a horizontal direction (regarding the improvement of transistors). It is being proposed. Series 1 Thin B9, which is different from the conventional configuration as described above.
Field effect 1 ~ The transistor has a gate insulating film formed by a thermal oxidation method, an anodic oxidation method, or a CVD method.
It was usually made of a single layer of film or Ta+CLia film. However, in the case of conventional silicon thin film field effect transistors that have such a configuration, the gate insulating film is formed by thermal oxidation or

[,1 is formed by anodic oxidation method or CVD method and is a single layer of ksi02 thin film or Al+O+ thin film or 1'a y (')5 thin film, so it has a low threshold (ffj voltage) and a high transconductance. Although it is desired that C1's motion be stable, these desired conditions have not been fully satisfied. '7I, - In a conventional silicon thin film field effect lR1 transistor having the configuration described above, its gate insulation 111. If j is a single layer of 3iCh thin film, then because the insulating film is a 3iCh thin film, at the interface between the region between the source region and the drain region of the silicon thin film 9 film and the gate insulating film, Goo 1 ~ Insulating film is AltOh
Since the charge density is lower than in the case of a single layer of thin film or 1a) Oi thin film, the threshold voltage is
-The insulating film has a characteristic that the resistance is lower than that of a single layer of ΔL20+ thin film or Ta+Oi thin film. The reason why the insulating film is SiO + thin is that the insulating film is Aj! , the +OI thin film layer is formed to have a lower electron trapping level than a single layer of Ta205 thin film, and the gate insulation II! a, the gate insulating film is AL+ Oi
The RGI film also has a lower electron trapping effect in the region between the source and drain regions of the silicon 1-in-W film than in the case of a single layer of thin film. Therefore, the threshold voltage of the gate insulating film is AjL+
Or u film J, lJ is 1°” r Oi RII film 1
It has the characteristic that it fluctuates less than when it is made of 11 layers. However, S10. The thin film has a dielectric value j↑ζ of 3.
4, since the Ta+Q+ thin film and the A fLrO+ thin film Oi have a small dielectric constant and C, there is an electric charge between the source region and the train region of the silicon thin film. n is the same gate insulation I
The thickness of Q, one gate/insulator) is l”il 70
I thin film or △, 203 thin II is smaller than △, compared to the case where it is a single layer of 1. , the thickness of the insulation film is 100
If it is thinned to a thickness such as 8 or less, electrons will pass through the insulation 11, and this /=me, 1 thin JIS for shi 1! Electricity 5ν effect Song 1 Heran Sister operation becomes unstable,
It had a lack of IAi. Furthermore, if the thickness of the insulating film is increased, the gate voltage will be reduced, and a high electric field of 10 V/cm or more will be applied to the film. A large number of electrons are generated at the interface between the region between the source region and the drain region of the thin film and the gate insulating film, and as a result, the region between the source region and the drain region of the silicon thin film, This has the drawback that a new I/II interface level is generated at the interface with the gate insulating film, resulting in a high threshold voltage. Just like that, if you change the thickness of the insulating film from Goo 1 to Goo 1,
~ Zetsumura, the membrane is generated as described above, many hot spots ~
The drawback is that the threshold voltage fluctuates due to the trapping of the 1-heron, which makes the operation as a silicon thin film field effect transistor unstable. In addition, in the conventional silicon thin film field effect transistor having the configuration described above, the gate insulating film is △J
, +0+ If the first layer of the thin film is A), then ΔL203 thin 1j has a dielectric E which is higher than the dielectric E of 8'(・A-)(, 3i0+), so ΔL203 thin 1j is The region between the source region and the train region of the silicon thin film and the goo 1
To save on static electricity between the electrode and the electrode, if the thickness of the insulating film is the same, there will be no problem! Compared to the case where it is made of a single layer of 5102 thin film, there is
! One way to avoid the above-mentioned drawbacks when using the first layer of +i
] The characteristic of being able to do things. However, at the interface between the region between the source and drain regions of e1 silicon thin film and the Goo 1-insulating film, 1Q
IT C111-1 and above, 1 to 1, 11) are S! 10 Ofi when consisting of a single layer of O+ thin film
In order to reduce the charge density of more than 1, the gate insulating film is higher than that of a single layer of 5ICh thin film (11). Since the insulating film is Aj,, Oi thin film, △Ly of A is
Due to the difficulty of forming the O+ thin film using the CV l) method, the gate insulating film has more electron trapping levels than when the insulating film is made of a single layer of S:O+ thin film of 1Q II Cl11-1 or higher. The gate insulating film or the insulating film is S! 1. With a single layer of O+ thin film. The effect of capturing electrons in the region between the source region and the drain region of the silicon thin film is higher than that in the case where the silicon thin film is separated from the source region and the drain region. For this reason, compared to the case where the gate insulating film is a single layer of 3iQ thin film, the threshold voltage changes more easily and the operation of silicon thin film field effect transistors is unstable. had. Furthermore, in a conventional silicon thin film field effect transistor having the 41+1 structure mentioned above, if the gate insulating film is a single layer of Ta205 thin film, ]-a, ○, the thin film has a dielectric constant of 25. Since it has a higher dielectric constant than the SiO7R film and the Al+Ch thin film, the region between the source region and the drain region of the silicon thin film,
The capacitance between the gate electrode and the gate electrode is the same)
, II! l! With the thickness of , the insulating film to goo 1 is 3iCh
11) Manoko is Δ (Lr O + thin 1 layer) compared to the case where the gate insulating film is made of a single layer of S i O + f + 9 films. , the goo 1 ~ insulating film is A
jl, q: 1 characteristic @ 4r tI that can be avoided and covered more than in the case of 111 single layer of +O + thin film
Ru. However, the goo [・insulation 11shi) is l-d+ Oh
Because it is an it+ film, a layer of goo (~5 x 10"cm-' or more) is formed at the interface between the region between the source and drain regions of the silicon thin film and the gate insulator 11.
When the insulating film is a ql layer C of 5102 thin films, 11-
Since it has a significantly higher charge density, it has a drawback that the threshold voltage is higher than that of the 171 type in which the gate insulating film is a SiO+'A') film. . Also, if the goo 1~insulating film is 1'a+Oin if;i 11
;l Chsu, and that "1alo+ thin film is formed by the anodic oxidation method Jl: /, :IJCV l) method. However, the effect of trapping electrons in the region between the source region and the drain region of the silicon 19 film is i'. (T's) 1. Silicon 1, 1, 1, 1, 1, !Effect 1 - The operation of a transistor ('I had a disadvantage of being unstable (~).) - (, The present invention is TZ of the above-mentioned drawbacks, new μm
Na Siri:, jn i'+4' II! i! Field effect 1 - Proposal of transistor I! /υ What will happen (゛) It will become clear from the following detailed description accompanied by drawings. Figure 1 shows an example of silicon thin film field effect 1 to transistor according to the present invention. For example, a P-type amorphous to polycrystalline film 2 is formed on an amorphous insulating substrate 1 by a method known per se. Desirably, that silicon R9Its! 2, all those J9
Throughout, an N-type source region 3 and a drain region 4 are formed in a manner known per se. In addition, in the region 1)-1 between the source region 13 and the train region 4 of the silicon thin film 2, goo 1 to insulation 11S! 6, the electrodes 1 to 7 are connected to the source (1118 and the train electrode 9) to the amorphous insulating substrate 1 formed by a known method. It is connected to the source region 3 and the drain region 11, and is formed by a method known per se. 1.
1. Further detailed explanation will be omitted. Sirinin1-AI7+1 according to the invention! l! Effect of giving electricity 5
An example of 121 to non-sister is d5 (
, - Which gate insulating film 6 is formed by, for example, thermal oxidation, in contact with the region 5 between the source region 11.'(3 and the drain region 4) of silicon φV II
A11・film 10, the S:O+thin film 10.1 was formed by the subaturing method °r'il)○, AλI
; 1111! The configuration consisting of a laminate with 11 is shown on the right. In practice, with such a laminate, 4f goo 1 ~ insulation JIT
,! G is 1 for thermal oxidation method and 5ICh thin film 10 is S! Form an O+ thin film and then 5iOtit'
A Ta)O7 thin film, which becomes the thin film 11, is formed on the I pattern by sputtering to obtain a laminate of a Sin thin film and a Ta+Oi thin film, and then the laminate is placed in a hydrogen atmosphere. The heat treatment () in i1. (for example, 450° C. for 30 minutes), and then patterning is performed on the heat-treated surrounding body. The above is an example of the structure of a silicon thin film field effect transistor according to the present invention. According to an exemplary configuration of a silicon thin film field effect transistor according to the present invention having this J, U configuration, the gate insulating film 6 is a silicon thin film 111i! S10. Since it is a laminate of a thin film 10 and a 1a) Oh thin film 11 formed on the 3i0+ thin film 10 by sputtering, S! OF thin film 10 (positive charge and Ta7
Since the negative charge C applied to the 0s thin film 11 cancels out to H↑], at the interface between the region 5 between the source region 3 and 1-1 twin region 4 of the silicon thin film 2 and the gate insulating film 6, Goo 1~The silicon thin film 1'7 mentioned at the beginning where the insulating film is a single layer of l' a HOh thin 1jψ! 'j! ':
! Of course, in the case of a /7 effect transistor, there is a
, the membrane is S! Compared to the conventional silicon thin film field effect transistor mentioned at the outset, which consists of a single layer of O+ thin film, a significantly lower electrical density is required. This means silicon thin 11! ,! 2 source area 3
The applied electric current jIV (pol 1 to
) and the capacitance C (standard vessel), we found that the applied voltage V was as shown in curve 1 in Figure 3.
FLAT] Band 'YE 'ff Vt (=-0,95
capacitance C in the area on the corner side where the bolt) is
On the other hand, in the invention shown in FIG. 1-Silicon thin film field effect according to the present invention according to FIG. When we measured the relationship between the capacitance C and the voltage V, we found that the applied voltage V
However, it is clear from the above that a result is obtained when the capacitance 11C takes the median value in the positive region with respect to the flat voltage Vf. For this reason, in the case of the silicon thin film capacitor transistor shown in FIG.
~5ICh%, 91f constituting the insulating film 6! +!
10 and -[11) rZ(
lor5 and S! O+ J5 is on the side of the thin film 10, and the positive and negative voltages are Ei, but the energy band is 1f! Region 5 between the source and drain regions of J2
There is only a small bend on the gate insulating film 6 side. By the way, 'l-a 20 is the thin film 11 (7) 71 is 8
If you want to enter 50, S! 0+ Note+1ru) 10 j'I
1 (8), the region F between the source region 1 and the O/drain region 4 of the silicon thin film 2] and the insulation Its! At the interface between the two, there is a charge density [) (
10"cnr') is shown in FIG.
When the thickness of 1 is E'3 and 0 people, by setting 19 of 5hot thin film 10 to :(00~/100 people), the electric current ('I Xfl W l) is 0.5X10
Below ``Cl1l-''(+(<'=I can be -(mono C). Therefore, the tuff, threshold 1 electrician 1] is,
Goo 1 ~ Insulating film or SiOtii9 film or Δη, 203
Thin+1u or l-a, ○, the first layer of the thin film -CI; it is much lower than when it is thin)! l: Curse the + sign to the right. In addition, as shown in FIG. 1 and according to the present invention, the gate insulating film 6 is 17) S!02R'p!1210 :
2 (, since it is in contact with the region 5 between the source region 3 and the drain region 4 of the silicon thin film 2, the gate isolation RIl
'A 1fiS10. As in the case of the conventional silicon thin film field effect transistors described at the beginning, which are made of a single layer of thin film, the gate insulation 1! ! h
< AL201 'i,'i membrane or l-a + Oh
The first layer of the S'TJJ film (-1-1) is compared to the case of a conventional silicon thin film field effect transistor, the source region 3 and the drain region/l of the silicon thin film 2. The electron in region 1 or 5 of IiJ is l+Ii 8'h-
46 Low action. In addition, in the present invention described above in FIG. 1, J: silicon thin film field effect transistor (,
', 04 It has the characteristic that it is difficult to move compared to the case of a single-layer thin film field effect transistor (a). . Furthermore, according to the present invention described above in FIG.
The dielectric constant is 25 and is much higher ( Since A, the electrostatic capacitance (
d is 1" of the same goo 1 to insulation 11), J is the thickness of the gate insulating film, and the gate insulating film is the middle layer C' of the oh thin film. /A) Similar to the lift stage of the Song Tung transistor, there is a person (・There is. Therefore, in the case of the silicon thin film field effect transistor shown in Fig. In addition, the silicon thin film field effect transistor according to the invention shown in FIG.
If J 6 does Tar Oi 1WI3311, -;
: ljte, that-“a +, Oi R9!I!,!1
1 is formed as J on the sputter link (,
-l-a,, Q, the thin film 11 is the silicon thin film 2
fij- between the source region 3 and the drain region til1
The effect of 511, ·) on the electrons of 1i15 is low, and therefore the electron capture unit in -1'if)O,1j9If11'l can be reduced to 10 v'am-'. , For this reason, the threshold voltage is 0 (1151 j city)'i! Effect 1 - compared to the case of a non-transistor, the field effect of the silicon thin film field effect transistor is changed by 1 [0, 1], and in the case of the silicon thin film field effect transistor of the present invention shown in FIG. 1-Operation as a transistor is possible if the gate insulating film is △L
The rO+ thin film Oh is characterized by being much more stable than the conventional silicon thin film field effect transistor described above.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an example of a silicon thin film field effect transistor according to the present invention. Fig. 12 is a silicon Jv which is not shown in Fig. 1 and is included in the present invention.
The film field effect (- is an energy band diagram showing the charge density distribution in the region between the silicon thin film source and drain regions of the transistor and the interface between the goo 1 and the insulating film. Figure 1 shows the silicon thin film field effect 1 to the silicon tti' IIG shown in Figure 1.
In order to explain the charge density at the interface between the source region 1 and the drain region 1 of I, such as the region 1a'1 between the region 1 and the insulating film,
, the electrostatic charge f9 '+' C (normalized Fig. 4 shows the relationship between the silicon thin film field effect 1 and transistor according to the present invention shown in Fig. 1. 11,1 of the constituting Ta, 04RQ film 't:ε3!')
(',) When set to 8, gate insulation Ilr, H)
I'm so happy! The charge at the interface between the region between the source and drain regions of the film and the insulator 11), relative to the thickness of the O+ thin film;
There is a small diagram of the relationship between 1) and 1). 1・・・・・・・・・・・・・・・・・・Amorphous rIij
16 ties! it1 to 2・・・・・・・・・・・・・・・
...Sirini Jii,'/I11/! 3...
・・・・・・・・・・・・Source area 4・・・・・・・・・
......Drain region 6...
・・・・・・・・・・・・Gate/Insulation: Film 7・・・・・・
・・・・・・・・・・・・Gu 1～゛Ichigoku 8・・・
・・・・・・・・・・・・・・・ Source voltage (i(9...
・・・・・・・・・・・・Drain region 10...
・・・・・・・・・・・・・・・3iCh Thin B9
11・・・・・・・・・・・・・・・l-a+o
i Thin film applicant 1-1 Thu. City Telephone and Telephone Corporation Figure 1 Figure 2 Figure 6 Figure 3

Claims (1)

[Claims] A thin silicon film is deposited on an insulating substrate,
A source region and a drain region are formed in the silicon thin film, and a goo 1 to - region is formed on the region between the source region and the train region of the silicon thin film through an insulating film.
In a silicon thin film field effect transistor having a structure in which a gate electrode is arranged, C1, the gate insulating film is in contact with a region between the source region and the drain region of the silicon thin film, S! O+ thin film and the S! A silicon thin film field effect transistor comprising a stack of Ta205 thin films formed by sputtering on Or FJ['A.