JPS59210595A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a semiconductor memory device.

[Background of the invention]

Among non-volatile semiconductor memory devices in which elements with an information storage function are arranged in a matrix on a semiconductor substrate so that information can be read out non-destructively, a non-volatile semiconductor memory device is one in which stored information can be rewritten by an electrical signal applied from the outside. Those with this structure are EEP 几OM (Ble~critically
Asable Programmable Read
Only Memory) or E P ROM (
Erasable eProgrammable head
0nly Memory) is known.

For example, as described in Japanese Patent Publication No. 51-42901, an EEP OM is an MNOS (Metal-Nitride-Ox
IDE-8 semiconductor) type transistors are used. In the above MNO8) transistor, when an electric field of more than a critical value is applied to the insulating film (in the direction perpendicular to the gate voltage and the substrate voltage), the charges in the substrate pass through the silicon dioxide layer due to the tunnel effect and the silicon nitride layer is formed. This charge is retained within the silicon nitride layer even after the above electric field is removed, but when an electric field of a predetermined value or more is applied in the opposite direction to the above, it returns to the inside of the semiconductor substrate. The charge attracts positive charges to the semiconductor substrate surface,
Because it affects the conduction threshold voltage ■TH of the transistor.

In an MNOS transistor, the VTH of the transistor is determined by the amount of charge remaining in the silicon nitride layer under the gate electrode.
can be changed, and information can be stored by making the state of vTH correspond to binary information "■" and "0". The stored information can be determined by whether or not the transistor becomes conductive when a predetermined gate voltage is applied.

In EFROM, instead of the above MNOS transistor,
FAM OS (Floating Avara)
ncheMO8) It uses a transistor,
Erases stored information by irradiating it with ultraviolet light.

By the way, ROMs in which these information can be rewritten have lower manufacturing yields than masks R and OM i that store fixed information, and are inferior to mask ROMs in terms of information retention period, etc. In addition, these R and OM require the user to write information such as programs to each storage device, but depending on the use of the ROM, both user-specific programs and general-purpose programs independent of the user can be written. If you apply an expensive ROM that can rewrite information to such uses, it will simply be a ROM
In addition to the problem of unit cost, the time loss required for writing the general-purpose program portion, which could originally be done in a mask ROM, cannot be ignored. In addition, the above general-purpose program part is stored in a mask ROM.
However, the input/output circuits are duplicated and the number of chips increases, which becomes uneconomical.

[Purpose of the invention]

The present invention has been made in response to the above reasons.

[Summary of the invention]

In the present invention, a ROM in which information can be rewritten is formed in a first region on one semiconductor substrate, and masks R and OM are formed in a second region ζ, so that the stored information of two ROMs with different properties can be stored. It is characterized in that it can be read out via a common output circuit on the semiconductor substrate.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, JOO is the first
A region 200 is a 24th:A region forming a mask ROM, and in each region memory cells each consisting of a storage element and a switch element connected in series are arranged in a matrix. In each memory cell 10 in the first region, the memory elements M, , M1□-Mn, .

consists of MNO8I-transistor, switch element S,
,S,・S nm is Enhancement Men! □WM OS
Consists of transistors. On the other hand, in the memory cell 20 in the second region, the memory elements Mp□, Mp2...M9-1
The switching elements Sp, S, 2, .

Above 1st. Throughout the second region, memory cells belonging to the same column share a common first. The first signal line (LL) on the switch element side is connected in parallel between the second signal lines.

L2...Lm) are resistance elements R1, R2...
Voltage terminal ■ through Rm. 0, and the second signal line (Ll'L, 2'...Lm') on the storage element side is connected to the ground potential. On the other hand, in each of the above regions, memory cells belonging to the same row have their gates connected to the first control line (Wl, W2...W,).
, second control lines (H,, H2...H4) are commonly connected, and each first signal is output according to the state of the gate threshold voltage of each storage element in one row selected by the second control line Line (L, ~L
, n), the stored information can be read out from the output terminals 1.2...+11. The voltages at these terminals are determined as 1'' or 0'' by a sense amplifier (not shown).

The storage element date voltage applied to the first control line during a read operation is not necessarily the same in the first region and the second region, but is based on the gate threshold of the storage element in the second region and the MNO8I-RANGE voltage applied to the first control line. By appropriately selecting the gate threshold value, it is possible to read the stored information by applying the same gate voltage.

For example, in the mask ROM 4, the memory element for information '1' is configured by EMO8, the memory element for '0'' is configured by DMO8,
E used in memory peripheral circuits as these elements
When using the same elements as MO8 and DMO8, EMO8
The threshold voltage is +〇, 5 V.

If the threshold voltage of DMO8 is 13■, in the second region, by applying zero V to the first control line W-W, EMO8
can be made non-conductive and DMO8 conductive. in this case,
The gate threshold value of each memory element in the first region is the first control line W0
~ When Wn is zero ■, which is the same as in the second region, set a value such that the storage element for information "■" is non-conductive and the storage element for "0" is conductive, for example, one is set to +4V and the other to -6V. Just leave it there. In this way, the bias circuit for the two storage areas can be shared, and an output corresponding to the state of the storage element of the memory cell addressed by the second control line can be obtained at the terminal 1-m. Voltage terminal ■. 0 to 5■, second signal line L1
If zero ■ is given to '~L,,,', an output voltage of approximately 0■ is obtained if the memory element is conductive, and approximately 5■ if it is non-conductive, and the output circuit is also connected to the above two storage areas. can be shared.

One embodiment of the present invention has been described above, but the MN in the first region
The memory element may be configured with FAMO8 instead of O8j. Furthermore, the output circuit may be of a different type from that of the embodiment. Furthermore, in the above embodiment, D is used as a memory element in the second area.
Although MO8 and EMO8 are used, it is also possible to replace the DMO8 applicable portion with a simple conductor, or make the EMO8 applicable portion nonconductive or disconnected.

〔Effect of the invention〕

According to the present invention, a mask ROM area and a ROM area in which information can be rewritten are configured on one semiconductor substrate, and the peripheral circuits are shared between the two ROMs. Therefore, a general-purpose program that does not depend on the user can be written from the beginning. This provides a convenient R, O'M that can be used to prepare and additionally store user-specific programs. In this case, since the manufacturing yield of the mask R,OM is higher than that of the information-rewritable R,OM, the memory of the present invention, which is partially composed of a mask ROM, can provide a relatively large memory capacity at a low cost. . Therefore, the device of the present invention is extremely effective for applications such as a ROM for a microcomputer that stores a general test program and a user-specific depacking program.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention, in which 100 indicates a first memory formation area where information can be rewritten, and 200 indicates a second memory formation area in which fixed information is stored. . In the figure, 100 is a first area, and 200ii is a second area. 497

Claims (1)

[Claims] A read-only memory with rewritable information is formed in a first area on one semiconductor substrate, a read-only memory in which information is fixed is formed in a second area, and the information stored in both memories is shared by a common memory. A semiconductor memory device that can be read to an output circuit via a signal line.