JPS59208744A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and specifically relates to a novel separation method (14
The present invention relates to a semiconductor device with a new structure.

[Background of the invention]

The conventional element isolation method in semiconductor integrated circuits (ICs) is the so-called LOCO3(f,ocal Qxidati
□n□f 5i1icon Niji-T-, Air Berzula, Phillips Research Report Vol. 25, p. 118.

1970; J. A. Appels et al.
, Ph1lips Resept 25,
II8 Dc+7o)L! : A method of forming an oxide film using a nitride/rifon film as an oxidation-resistant mask has been commonly used. However, the following two major problems with this method have become apparent as the device dimensions are reduced.

(1) So-called bird beak
Reduction of device area due to intrusion of the oxide film for device isolation into the region where the device is to be formed, called eak). Usually, the width is about 1/2 of the thickness of the oxide film for isolation between elements. For example, when the oxide film thickness is 1 μm, it is about 0.5 μm.

(2) Impurities doped under the oxide film, such as boron in the case of a P-type substrate, are used to grow the oxide film to prevent the formation of channels between devices and for complete electrical isolation. In the thermal oxidation process, it diffuses laterally to form a highly enriched boron diffusion layer, resulting in a reduction in the effective device area. This is called a narrow channel effect in the case of MO8 type ICs.

Because of these two problems, it is impractical to perform device isolation using the LOCO8 method, especially in ICs consisting of fine patterns with device dimensions of 1 μm or less.

For example, making an IC with a device isolation region of 1.0 μm will result in a bird peak of 0.15 μm and a narrow channel effect of approximately 1.0 μm.
Since it is μm, it is impossible. On the contrary, first 1
A region with a width of .mu.m ultimately becomes an element isolation region with a width of 2.5 .mu.m.

In order to solve these problems of the ocos method,
A coated glass method can be used. This is shown in Figure 1 (a
), P type (100) plane, 10Ω・+17
A groove is formed on the Si substrate 1 of No. 11 by a reactive sputter etching method, and a coated glass such as 0CD59 is further formed.
310 (product name; manufactured by Tokyo Ohka) with a rotation speed of 5000 rpm
When spin coating is carried out at m, the groove is covered with a thick coated glass film 2,
The still flat portions are each covered with a thin coated glass film 3. In order to actually form an element, a thin coated glass film 3
It is necessary to remove the Si substrate 1 and expose the 81 substrate 1, but at this time, the thick coated glass film is also etched, and as shown in FIG. 1(b), it is lower than the Si substrate 1 by the amount of overetching. I'm spoiled. Furthermore, each time the silicon oxide film is etched in the subsequent process, the thick coated glass film 3 is etched, resulting in a step difference of 0.2 μm or more. As described above, it is necessary to prevent the height of the element isolation region from becoming lower than that of the substrate, since this will have a negative effect on the element characteristics. Such level differences cannot be avoided by simply applying coated glass.

[Purpose of the invention]

The present invention has been made to solve these problems of the prior art, and it is possible to improve the precision of the element isolation structure by creating a structure in which the element isolation oxide film protrudes from the 81 substrate. This makes it possible to

[Summary of the invention]

The present invention is illustrated in the conceptual diagram shown in FIG.
1. First, the case where it is applied to C will be explained. P type (1
00) A groove with a depth of 1 μm is formed in a Si substrate 4 with a surface of 10 Ω·m, and coated glass is applied by rotation to form a thick coated glass layer 5.
A gate 6, a gate oxide film 7, and an arsenic diffusion layer 8 are formed to protrude from the Si substrate, and a gold layer 8 is formed. By adopting such a structure, both the element isolation width and the channel width can be made equal to the designed value. If the thick coated glass layer 5' were to be lower than the 81 substrate 4 as in the conventional case, the side surface 9 of the Si substrate 4 would become a channel area, as shown in the cross-sectional view in the channel width direction in FIG. 2(b). Therefore, secondary problems arise, such as difficulty in controlling the threshold voltage (VTR). The reason for this is (1) V T
The ion implantation method used to control R has two problems: (2) it is impossible to implant black ions into the side surface 9; and (2) the ascending level density Qss differs depending on the Si0 surface.

[Embodiments of the invention]

The present invention will be described in detail below based on examples.

Example 1 Figure 3 (→ indicates P-type (100) surface 10Ω・ffi Si
The board 11 is 1000 tl? Oxidation is carried out in dry oxygen to grow a thermal oxide film 12 with a thickness of 5 Qnm, and then low pressure chemical vapor deposition (:chemical
Vapor Deposition method; hereinafter LPCVD
A silicon nitride (hereinafter referred to as 813N4) layer 13 with a thickness of 200 nm was deposited by a method (abbreviated as 813N4), and AZ1350J (trade name; manufactured by Shipley Co., Ltd.) was spin coated as a resist to a thickness of 1 μm. A pattern 14 is shown formed in a region where an element is to be formed according to the process.

FIG. 3(b) shows the SI3N in the area other than the pattern 14.
The fourth layer 13 and the thermal oxide film 12 are etched by reactive sputter etching using a mixed gas of CF490 and H210, and the Si substrate 11 is further etched by reactive sputter etching using SFg gas to a depth. This shows a state in which a groove of 1.5 μm was formed and further etched for 30 seconds with an etchant containing a mixture of hydrofluoric acid and nitric acid at a volume ratio of 1:50. This etching using a mixed solution of hydrofluoric acid and nitric acid is performed to remove damage caused by reactive sputter etching.

FIG. 3(C) shows a state in which the coated glass 15 is applied and the grooves formed in the substrate 81 are filled. The coating conditions for the coated glass were a rotational speed of 500 rpm and annealing at 200 C for 20 minutes. By applying multiple times, the thickness becomes 1 μm.
It is possible to completely fill the coated JJ glass with the top edge 1 of the resist layer.

FIG. 3(d) shows that the resist layer 14 is removed and the groove is
1 shows a state filled with coated glass 15 protruding from the surface of one substrate.

As shown in this example, in order to form a coated glass layer that protrudes from the surface of the semiconductor substrate, a material such as a resist is deposited thickly in an area other than the area where the tray glass layer is to be formed, and then All you have to do is apply coated glass to make it flat.

Example 2 Figure 4(a) shows P-type (100) surface 10Ω cm L7)
After oxidizing the 81 substrate 21 in 10001 dry oxygen and growing an oxide film 22 with a thickness of 2Q nm, L P
Thickness 120 nm (7) 81s N4 by CVD method
A film 23 and an 8102 film 24 with a thickness of 400 nm are deposited by the CVD method, and a pattern 25 is formed using AZ1350J as a photoresist.
2 film 24, S r 3N 4 film 23, thermal oxide film 22,
It shows the state where each was etched by reactive sputter etching using CI-i Fa gas.

FIG. 4(b) shows that after removing the resist pattern, CF 4
The 3i substrate 2 is etched by reactive sputter etching using gas.
A purple groove with a depth of 1 μm was formed in 1, and hydrofluoric acid was added.

The 8j02 film 24 was immersed in a solution mixed at a volume ratio of nitric acid =■:50 for 30 seconds to etch 0.05 μm on the 81 side.The 8j02 film 24 was further immersed in hydrofluoric acid to be removed, and then immersed in dry oxygen at 1000C for 20 minutes. Oxidized thermal oxide film 26 with a thickness of 2011 m
Shows the grown state.

Figure 4 (C) shows boron as the coated glass.
Rotation speed 300 Orp containing OCD 59310 containing 1 mol%
This figure shows the state in which the sample was coated on a rotating wall at m to form a coating lath (27), and then heated in a 900C wet atmosphere for 30 minutes.

FIG. 4(d) shows the coated glass r on the 5j3N4 film 23.
e 27 was etched with a buffer etchant containing a mixture of hydrofluoric acid and ammonium fluoride at a volume ratio of 20, and then the Si
The 3N4 layer 23 was removed using fully heated phosphoric acid, and the 8102 layer 22 was removed using a buffer etchant. With this structure, it is possible to realize a structure in which the coated glass layer 27 protrudes from the Si substrate by about 0.1 μm.

FIG. 4(e) shows the gate oxide film 28 and the gate conductor 29.
, form the source/drain region 30, and MO8L”E
This shows the completed state of T. At this time, the coated glass layer 27
Since boron is diffused into the 81 substrate 21 to form a channel stopper, there is no fear of leakage current or the like. A schematic cross-sectional view of the completed device in the gate width direction is shown in Figure 4.Compared to the conventional technology shown in Figure 2(b), perfect 1''ET operation is expected because no channel is formed on the sidewalls. Also, the step difference in the element isolation region is 7il-01μm.
Since it is possible to do the following, it is possible to completely avoid the occurrence of wiring defects at the stepped portion.

Example 3 FIG. 5(a) shows 'z(7) on the Pa(100) plane 10.
After thermally oxidizing the Si substrate 31 in a 100OC dry oxygen atmosphere and growing an oxide film 32 with a thickness of 5 Qnm, polycrystalline silicon (hereinafter abbreviated as polysi) was deposited to a thickness of 0 using the LPCVD method.
．． The pOA is deposited to a thickness of 5 μm, and the pOA is deposited on the area where the device is to be formed using a conventional photolithography method.
The ysi layer is etched by reactive sputter etching using -CF4 gas to leave a pattern 33, and the Si substrate is further excavated to a depth of 0.7 μm to form a groove, the resist is removed, and then etched again. Dry oxidize at 1000C to form oxide film 3
4 has grown.

Figure 5(b) shows boron as the coated glass.
A coated glass layer 35 is formed by spin coating 0CD59510 containing 1 mol of 0CD59510, and after annealing in nitrogen for 30 minutes, the coated glass layer on the pOtyS1 layer 33 is removed, and a reactive layer 35 is formed using CF4 gas. The potySi layer 33 is shown removed by sputter etching. After removing the thermal oxide film 32, a device is created on the substrate 81.

〔Effect of the invention〕

As shown in the examples above, by forming a coated glass layer that protrudes from the 81 substrate and using it for isolation between elements, it is possible to improve the conventional L
By eliminating the drawbacks of the OCO8 method and the problems of the conventional coated glass method, a device with excellent device characteristics can be realized.

That is, (1) LOC such as hard peaks and narrow channel effects;
It is possible to prevent the active region from decreasing due to the O8 method, and it is possible to realize a device with the same design dimensions.

(2) The level difference in the element isolation region can be reduced, and sidewall channels and wiring defects can be eliminated.

Therefore, according to the present invention, it is possible to realize an element isolation technique with a width of 1 μm or less, thereby making it possible to further increase the density of elements. In addition, when applying this technique to C-MOS, it is sufficient to form a groove having a depth equal to or greater than the depth of the well, and fill this groove with coated glass.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the prior art, and FIGS. 2 to 5 are process diagrams for explaining different embodiments of the present invention. 1.4, 11, 21.31...81 board, 2,3゜5
．． 5', 15, 27.35... Coated glass layer, 6°29... Gate, 8.30... Source/drain region, 7.28... Gate oxide film, 9... Side wall, 12
,22゜26.32.34...thermal oxide film, 13.23
...Silicon nitride, 14...Resist,
33... Multiple buds 1 Figure ((1) % 1 Figure (b) Figure 2 (Good) Figure 2 (b) Figure 3 (C) Open 3 Figure (d) Figure 4 ((1)

Claims (1)

[Claims] The semiconductor substrate has a groove provided therein, and the groove is filled with a cured product of T cloth glass, and the upper surface of the cured coated glass is above the edge surface of the semiconductor substrate. Semiconductor equipment.