JPS59206808A - Focus detector - Google Patents

Abstract

PURPOSE:To increase the response speed at a low luminance and to decrease the influence of a camera shake by adjusting the level of a circuit for generating a luminance modulating level to maintain the specified integrating time and output from a photodetector array when the output from a clocking circuit exceeds the range of a normal time. CONSTITUTION:When brightness decreases, the integrating time increases gradually within an optional preset luminance modulating level and if the integrating time takes a specified value or above, the output from a reference time generating circuit 800 goes to a controller 1100 then the luminance modulating level is brought down by one step by the control of said controller 1100 and the integrating time is made shorter with respect to the same brightness. When the brightness increases, the integrating time decreases successively within the optional luminance modulating level and the output from the circuit 1000 goes to the controller 1100 then the luminance modulating level is brought up by one step by the control of the controller 1100 so that the integrating time is made longer with respect to the same brightness. The always specified integrated output voltage is thus obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus that uses an array of integral light receiving elements to extract a constant level of contrast output even when subject brightness changes, and automatically performs focus detection.

Conventional contrast method using an MO8 type photodetector array or an integral type photodetector array such as a CCD.

Many applications have been filed for and commercialized devices that perform focus detection using triangulation and the like. By the way, if the output of the integral type photodetector is ■, then C is a constant determined by the shape and sensitivity,
It is given by the formula V=CX L XT where L is the average illuminance of the light being irradiated and T is the time during which the light with the illuminance L is being irradiated. In the conventional method of obtaining a constant optical integral voltage (2), a constant output voltage was obtained by changing the integral time T in response to changes in the brightness of the subject. By the way, in this method, when the subject brightness decreases to 1/2, the integration time inevitably doubles, and especially in the case of low brightness, this integration time becomes extremely long, making it difficult for the device to The response speed of the camera and the effects of camera shake caused inconvenience in use. Furthermore, if the integration time is limited to a certain period of time, the optical integration voltage decreases and focus detection becomes impossible.

The present invention is intended to overcome the above-mentioned disadvantages,
The purpose is to provide focus detection that has a fast response speed even in low brightness and is less affected by camera shake, and to improve focus detection ability in low brightness.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Focus detection of the present invention will be explained in detail below according to embodiments shown in the accompanying drawings.

First, the basic configuration of focus detection according to the present invention will be explained with reference to FIG. FIG. 1 shows the basic configuration of focus detection according to the present invention as a circuit block diagram. The drive circuit 100 is connected to the integrating type light receiving element array 200, outputs an integration start pulse and a drive pulse, and also outputs a monitor diode 500. Reference time generation circuit 800. It is also connected to a clock circuit and outputs an integration start pulse. The integrating type light receiving element array 200 is connected to an integration end control circuit 900 and an amplifier 300, inputs an integration end signal, ends the integration, and outputs the output to the amplifier 300. The amplifier 300 performs amplification using an externally settable amplification factor and outputs a constant level optical integrated voltage to the focus detection circuit 400. The focus detection circuit 400 performs focus detection processing using the input voltage from the amplifier 300. The monitor diode 500 is a comparison circuit 600
is connected to outputs an optically integrated voltage for monitoring. On the other hand, the brightness modulation level generation circuit 700 is also connected to the comparison circuit 600 and outputs a brightness modulation level set from the outside.

The comparison circuit 600 includes an integration end control circuit 900 and a timing circuit 1.
000 and the output of the monitor diode 500;
The outputs of the brightness modulation level generation circuit 700 are compared and outputted. The reference time generation circuit 800 is the integration end control circuit 9
00 and outputs a signal when the integration time reaches a certain set time. The integration end control circuit 900 is the comparison circuit 6
When either the output of 00 or the reference 3-time generating circuit 800 is output, an integration end signal is output to the integrating type light receiving element array 900.

The clock circuit 1000 measures the time from the integration start pulse of the drive circuit 100 until the integration end signal of the comparator circuit 600 is output. A controller 1100 is connected to each part and performs integration time adjustment, amplification factor adjustment, brightness modulation level adjustment, and timing management.

Next, the functions of the basic structure of the present invention constructed as described above will be explained with reference to FIG. FIG. 2 shows the integration time of the monitor diode 500 on the χ axis and the output of the monitor diode 500 or the brightness modulation level generation circuit 70 on the y axis.
The brightness modulation level is 0. The larger the slope of the straight line is, the brighter it is, and the smaller the slope is, it is darker. The monitor diode 500 performs integration with the slope corresponding to the brightness, and ends the integration when the set brightness modulation level is reached.

Thick solid line part in the figure 1~3.4~7,8~11°12~1
5.16-19.20-23. . . . is a series of possible integration end points of the monitor diode 500 when the focus detection of the present invention is operated, and is a collection of straight line portions corresponding to 4-brightness modulation levels. Furthermore, the dotted line portion in the figure shows the transition of the integration end point when the brightness modulation level changes by one step for the same brightness integration. Further, brightness modulation levels 1, 1/2. i/'I
Amplification factor 1 to obtain a constant output for ,...
, 2, 4. ...and the constant output at that time 1, 1,
1. ... is shown on the right side of the graph in a form corresponding to the brightness modulation level. In Fig. 2, to simplify the explanation, the brightness modulation level is initial value 1 and changes by 172 times per step.
The output l is obtained by setting the amplification factor to an initial value of 1 and changing it by a factor of 2 per step, but more generally, the brightness modulation level is changed by a factor of 1/n per step at an initial value of m, and the amplification factor changes by a factor of 2 per step at an initial value of m. By doubling this, it is possible to obtain a constant output mk. First, when the brightness decreases, the integration time becomes longer within the arbitrarily set brightness modulation level → T1 → T2 → T3 → T4
The integration end point moves in the direction of .

If the integration time is T4 or longer than T4, the output of the reference time generation circuit 800 is
00, the brightness modulation level is lowered by one level under the control of the controller 1100, and the integration time is shortened from T4 to T2 for the same brightness.

At this time, the output of the controller 1-roller 1100 is sent to the amplifier 300, and the amplification factor is increased by one step, so the output does not change. If it gets even darker, do the same T2→1゛3→
After a change in T4, when the integration time becomes longer than T4 or T4, the brightness modulation level is lowered by one step, and for the same brightness, the integration time becomes shorter from T4 to T2. Therefore, when the brightness decreases from a very bright state to a dark state, the integration end point is 1 → 2 → 3 → 5 → 6 → 7 → 9 → 1o →
11 → 13 → 14 → 15 → 17 → 18 → 19 → 21 → 2
Move according to 2 → 23. Next, a case where the brightness increases will be explained. When the light becomes brighter, the integration time becomes shorter within an arbitrary brightness modulation level, and the integration end point moves in the direction of →T4 →T3 →T2 →T1. Then, when the integration time becomes T1 or shorter than T1, the output of the clock circuit 1000 goes to the controller 1100,
With the control of 0, the brightness modulation level is increased by one level, and for the same brightness, the integration time becomes longer from T1 to T3.

At this time, the output of the controller 1100 is output to the amplifier 300.
Since the amplification factor is lowered by one step, the output does not change. Similarly, when it becomes brighter, T:
After the change from 3 to T2 to T, when the integration time becomes shorter than T1 or T1, the brightness modulation level is lowered by one step, and for the same brightness, the integration time becomes longer from T to T3. . Therefore, when changing from a very dark state to a very bright state, the integration end point is 23→22→21→
20→18→17→16→】4→13→12→10→9
→ Move according to 8 → 6 → 5 → 4 → 3 → 2 → 1.

Through the operation described above, by setting the brightness modulation level corresponding to the brightness, it is possible to always obtain an integral output in a time shorter than the constant time T4, and the amplification factor corresponding to the brightness modulation level can be obtained. This prevents the output from decreasing and allows a constant integrated output voltage to be obtained at all times.

Note that since the level transition time condition has hysteresis as shown in the figure -'/-, even if the brightness changes somewhat after the transition, it remains within the set level and a more stable output can be obtained.

Next, specific embodiments of the present invention will be described in detail with reference to FIGS. 3 to 21.

FIG. 3 shows an example of the configuration of an amplifier 300 according to the present invention. The inverting input terminals of operational amplifier 302 and operational amplifier 304 are connected to resistor R.
, 306, and the difference in the input voltages of the non-inverting input terminals of each operational amplifier is applied across the resistor R3306, and the resulting current is connected to each operational amplifier 302.
．． Resistor R4 connected between the output of 304 and the inverting input terminal
By supplying 308 and 310, (R3+2R4)/
Performs differential amplification of R3 times. The amplified voltages at points A and B are input to the inverting amplifier 320 at the next stage. The inverting amplifier 320 includes an operational amplifier 322, a resistor Rr324 connected between the inverting input terminal of the operational amplifier 322 and the output of the operational amplifier 302, a resistor 326 connected between the inverting input terminal and the output, and a non-inverting input terminal and the operational amplifier 304. It consists of a resistor R2330 connected between the non-inverting input terminal and GND, and an amplification factor R2.
/R, , is inverted and amplified, and the output is output to the next stage resistor divider 340. The resistor divider 340 connects the operational amplifier 322 and GN
Resistor 4 connected in series between D R342゜2R344
, R346, R3/18, and a MOS switch 352.354°356 which is connected between the dividing point of each resistor and the non-inverting input terminal of the next stage operational amplifier buffer 360, and whose switching is controlled by the output of the 4-pin 1-register 350. ,3
58. The potential at the dividing point of each resistor is MO
Assuming that the voltage corresponding to the S switch 352 is 1, 1. ,
1/2. ]/4. +/8, respectively, R3
, T32, 13], selected by the BQ signal.

The 4-bit register 350 is connected to the control circuit 110.
0, and the data output to B3 to BO is written by operating the C8 terminal.

The operational amplifier buffer 360 takes out as a buffer the output finally obtained by the first stage amplifier, the next stage inverting amplifier, and the final stage resistor divider. With the above configuration, the amplifier 300 calculates the difference between the signal input from the integrating type photodetector array 200 and the noise by ((R3+2R4) /R3) (R2/Rt)
Amplify by X (set attenuation rate) times (1, 1/2.1/4.1/8) and output.

FIG. 4 shows another configuration example of the amplifier 300. Operational amplifier 372. The non-inverting input of the operational amplifier 378 receives the noise output and the signal output of the integrating type photodetector array 200, respectively, as in FIG. Further, the internal configuration of resistance divider 370 is the same as the configuration of resistance divider 340 in FIG. 3. The inverting input terminal of the operational amplifier 372 is connected to the resistor divider 370.
The common terminal of the OS switch is connected, and the output terminal is connected to the 4R of the resistance dividing section of the resistance divider 370 via a resistor 374.
380 side is connected.

A resistor divider 370 is connected to the inverting input terminal of the operational amplifier 378.
The R386 side of the resistance dividing section is connected. A resistor 4R376 is connected between the output of the operational amplifier 378 and the inverting input terminal. With this configuration, 16R/Z times (Z=R
, 2R, 4R, 8R) and inverting amplifier 320
Output to . Inverting amplifier 320 is the same as that described in FIG. With the above configuration, the difference between the signal and noise is amplified by (16R/Z)×(R2/Rt) and output.

Next, an embodiment of the monitor diode 500 will be described with reference to FIGS. 5 to 7. Figure 5 shows an example where integration is performed from a low potential to a high potential.

The monitor diode 502 is connected between the power supply and the MOS switch, and the other end of the MOS switch is connected to GND. When the gate of the MOS switch becomes old gh, the monitor diode 502 is charged and becomes Low, and integration is performed. FIG. 6 shows an example in which integration is performed from a high potential to a low potential, and a monitor diode 502 is connected between one end of a MOS switch and GND, and the other end of the MOS switch is connected to the power supply. When the gate of the MOS switch goes low, the monitor diode 502 is charged, and when it goes high, integration is performed. FIG. 7 shows a case in which integration is performed from a low potential to a high potential, and an output is produced based on the average integrated value of several monitor diodes. Several monitor diodes 502 are connected in parallel, with one end connected to the power supply and the other end connected to the 11-MOS switch, with the other end of the MOS switch connected to G.
Connected to ND. MOS switch gate is Hi
When the voltage reaches gh, the monitor diode 502 is charged, and when it becomes +'Low, it starts integrating.

Next, an embodiment of the comparison circuit 600 will be described with reference to FIGS. 8 to 10. Figures 8 and 9 are realized using a commercially available bipolar comparator, and the signal S
is higher than the reference voltage R, Lo at 1.1
The circuit of FIG. 8 obtains an output of w, and the circuit of FIG. 9 obtains a high output. 8 and 9 are circuits realized by bipolar comparators, whereas FIG. 10 is a circuit realized by CMOS. The signal S and the reference voltage R are sent to the AC amplifier 6 via SWl and SW2, respectively.
10 is connected to one end of the capacitor C6L2. The AC amplifier 610 is connected to the capacitor C612.
, an inverter 614 connected thereto, and a switch SW3 connected between the input and output of the inverter, and outputs the amplification result to the D terminal of the flip-flop 620. First, SW3 is closed and inverter 614 is turned on = 12
- Output potential is set to ■DD/2. Next, when SWI closes, capacitor C612 is charged to a potential difference between the signal potential and VD,/2. In this state, SW3. When SWl is opened and SW2 is closed, one end of the capacitor C612 changes to the reference potential R, but the other end of the capacitor C612 is only connected to the input of the high impedance inverter 614, so there is no place for the current to flow. Therefore, the potential of capacitor C612 does not change. Therefore, capacitor C6
The difference between the signal voltages applied to one end of capacitor C6
It is added to the potential of 12 and output to the other end. The inverter 614 inverts its output due to this potential change applied to the threshold level and outputs the comparison result to the flip-flop 620, which holds the result and outputs it by the signal φ3 inputted to the clock terminal.

Next, an embodiment of the brightness modulation level generation circuit 700 will be described with reference to FIGS. 11 to 13.

Figure 11 shows a circuit that generates a reference voltage with GND as a reference, using a resistor Ro 712 connected in series from the power supply to GND.
．． 4 R71, 4, 2R716, R71g, R720
a resistor divider 710 consisting of a resistor divider 710;
It consists of a MOS switch 722 that is connected to each dividing point and whose other end is connected to an output, and a 4-bit register 730 that outputs a selection signal to the gate of the MOS switch 722.
It controls the chip select terminal of the bit register 730 to receive setting data from the controller 1100, controls the gate of the MOS switch, and outputs a reference voltage.

Figure 12 shows a circuit that generates a reference voltage based on the power supply.
12 is another embodiment of the resistor divider 710 portion of FIG. 11. FIG. R742, R744, 2R7 in series from power supply to GND
46, 4R74B, and Ro750 are connected to generate voltage by resistance division.

FIG. 13 shows another embodiment of the brightness modulation level generation circuit 700, including an 8-bit register 750 that exchanges data with the controller, and an analog voltage that is connected to the 8-bit register 750 and that corresponds to the set digital amount. The brightness modulation level is generated under the control of the controller.

Next, FIG. 14, which is a specific embodiment of the reference time generation circuit, will be described. The oscillator 802 is connected to the clock terminal of the counter 804 and sends a reference clock to the counter 804 . An integration start signal from the drive circuit 100 is connected to a reset terminal of the counter 804, and the start of integration is synchronized. Counter 804 outputs an output to integral end control circuit 900 after a certain set time.

Next, a specific example of the integration end control circuit 900 will be described. FIG. 15 shows a case where the OR circuit is used to determine whether the output of the comparison circuit 600 is High or the reference time generation circuit 800
This is a case where the integration end control signal high is output to the integrating type light receiving element array 200 when the output of the integration type light receiving element array 200 is High. 16th
The figure shows a case realized by an AND circuit, and the comparison circuit 6
When the output of 00 is Low or the output of the reference time generating circuit 800 is Low, an integration end control signal 1,0ν is output to the integrating type light receiving element array 200.

Next, FIG. 17, which is a specific example of the clock circuit 1000, will be described. A frequency division counter] 002 inputs the output of the oscillator 802, divides the frequency, and outputs the output to the OR circuit 1004.
output to the input of The OR circuit 1004 includes a comparison circuit 6
An output of 00 is input, and the division counter 1 is used only during the integration time.
The output of counter 1002 is gated and output to the clock terminal of counter 1006. The counter 1006 receives an integration start signal from the drive circuit at its reset terminal, and measures the integration time in synchronization with the integration start signal. The 3-state buffer receives the output of the counter 1006 and outputs an output when the C8 terminal is selected.

Finally, FIG. 18, which is an embodiment of the controller 1100, will be described. FIG. 18 shows the controller 1-roller 1100 realized using a one-chip microcomputer 8049, and flowcharts of the program of this one-chip microcomputer are shown in FIGS. 19 to 21. The integration start pulse of the drive circuit 100 is input to the TO terminal of this one-chip microcomputer, and the operation of the system is synchronized. The T1 terminal is an external timer interrupt terminal, which inputs the output of the reference time generation circuit 800, detects an input at the -16=Loν level, and executes the timer interrupt processing routine. The INT terminal is an external interrupt terminal, which inputs the output of the comparator circuit 600, detects an input at the Lov level, and executes an external interrupt processing routine. Either the timer interrupt processing routine or the external interrupt processing routine is executed for one integration. Poe 1-1 O~3 pitch h (
PO to P3) are the C8 terminal of the register of the amplifier 300 and the C8 terminal of the register of the brightness modulation level generation circuit 700, respectively.

It is connected to the C8 terminal of the register of the clock circuit 1000, and controls reading and writing to each register. The data read and written at this time is 8 of the passport (BUS).
It is transferred using all or part of a line of bits.

The operation of the one-chip microcomputer connected as described above will be explained according to the flowcharts shown in FIGS. 19 to 21. FIG. 19 is a flowchart of the main routine. The processes from (1) to (4) are power-on processes in which the brightness modulation level and amplification factor are initialized and the set values are stored in internal registers (R2 and R3, respectively). Q~
During (2), interrupts are first masked, the timer counter is set to 255, and the TO terminal is monitored. The start of integration is detected by monitoring the TO terminal, the interrupt is canceled, and the timer starts counting. Then, the system waits for the interrupt (■).

If the integration time is long and the integration is completed by the output of the reference time generation circuit 800, the T1 terminal detects a low level and the timer interrupt processing routine (■
(processing from) is executed. In the timer interrupt processing routine, when the stored amplification factor is not the maximum value, the amplification factor in the amplification factor setting register is increased by one step, the stored value is also changed, and when the brightness modulation level is not the minimum value, the brightness modulation level is changed. Lower the brightness modulation level of the setting register by one step.

Also, change the stored value so that the integration time becomes shorter with a constant output. Then, it masks the interrupt, operates the stack, and returns to the connector of ■. If the integration time is short and the integration is completed by the output of the comparator circuit 600, the INT terminal detects the LOν level and the external interrupt processing routine shown in FIG. 21 is executed. In the external interrupt processing routine, first, the integral time measured by the clock circuit 1000 is input. Then, this integration time is compared with the specified time, and if it is longer than the specified time, the interrupt is masked without changing the amplification factor and brightness modulation level setting register, and the stack is manipulated to connect the Return to. On the other hand, if the time is longer than the prescribed time,
When the amplification factor stored in the internal register is not the minimum value, the amplification factor in the amplification factor setting register is lowered by one step, and the stored value is also changed accordingly.Furthermore, when the brightness modulation level is not the maximum value, The brightness modulation level in the brightness modulation level setting register is raised by one level, and the stored value is also changed accordingly, so that the integration time becomes longer with a constant output. and,
Mask the interrupt, manipulate the stack, and return to the connector of ■.

As described above, the focus detection device for a camera according to the present invention can always obtain the desired data 19- within a certain set time T2, so it is possible to realize a focus detection device with quick response and to Since the dynamic wrench can be changed by changing the dynamic wrench, focus detection for darker objects is also possible, improving focus detection ability. Furthermore, the fact that the data detection time can always be made shorter than the set time T2 has a great effect in that it is possible to prevent the effects of camera shake and the like, and to provide a device that is easy to use.

[Brief explanation of the drawing]

Fig. 1 is a block diagram corresponding to the claims, Fig. 2 is a graph explaining the functions according to the structure of the present invention, Figs. 3 to 18 are illustrations of one embodiment of each component of the present invention, and Figs. Second
FIG. 1 is a flowchart for explaining one embodiment of the controller. 100... Drive circuit 200... Integral type light receiving element 300... Amplifier 400... Focus detection circuit 50
0... Monitor guide 600... Comparison circuit 70
0... Brightness modulation level generation circuit 800... Reference time generation circuit 900... Integration end control circuit 1000... Time measurement circuit 1100.
...Controller 20 - Fig. 1 Fig. 2 tQ Megout 2 Rotoma -1l (1 Fig. 4 Fig. 14 Fig. 15 Fig. 16 Fig. 17 Fig. 180 Fig. 20 Fig. 2f Figure #i Minute time input fr * Minutes YES N. Minimum amplification? N. Amplification setting value!! 1st class down amplification Rehe '1 and maximum? Tori n degree transformation bow stamen 1 slave 1 punch ヱνfu.

Claims (1)

[Claims] an integral type light-receiving element array, a monitor diode that outputs an integrated voltage corresponding to the average illuminance of the integral type light-receiving element array, an externally settable brightness modulation level generation circuit, an output of the monitor diode, and the brightness modulation level. a comparison circuit that compares the output of the generator circuit; a timing circuit that measures the time from the start of integration until the output of the comparison circuit is output; and a timer circuit that amplifies the output of the integrating type light-receiving element array using an externally settable amplification factor. an amplifier, and when the output of the timer circuit is greater than a first specified time, the level of the brightness modulation level generation circuit is lowered to shorten the integration time, and the amplification factor of the amplifier is increased. When the output of the timer circuit is small for a second specified time shorter than the first specified time, the brightness modulation level is increased. A focus detection device characterized in that the level of the generation circuit is increased to lengthen the integration time, and the amplification factor of the amplifier is lowered to make the output of the integration type light receiving element array constant.