JPS5920153B2 - Function generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a function generation method, and more particularly to a function generation method that can correctly read control marks written on paper regardless of dirt on the paper.

Conventionally, there has been known a device that mechanically reads a function drawn on a sheet of paper and also reads and outputs a control mark drawn as a straight line on the sheet (for example, Japanese Patent Publication No. 1193/1983).
No. 7).

However, this conventional technique has the disadvantage that if the paper is dirty, errors are likely to occur in reading the control marks.

SUMMARY OF THE INVENTION Accordingly, the present invention aims to improve the above-mentioned drawbacks of the prior art, and its object is to provide a function generation method that allows control marks to be read accurately regardless of the dirt on the paper.

In order to achieve this objective, the present invention performs line thinning processing to extract a mark having the maximum signal length for each mark having a width on a mark signal perpendicular to a reference line extracted from a scanning signal, and then A predetermined number of marks are extracted from the extracted marks in descending order of signal length.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1A shows an example of a function to be read. A function curve G is drawn in the function zone F, and the distance between the reference line S and the function curve G is read as the value of the function.

A mark zone M is provided near the function zone F, and control marks M1 and M2 are drawn by straight lines perpendicular to the reference line S.

The two control marks are used, for example, to read the value of the function curve G in the section from the start mark M1 to the stop mark M2.

In Fig. 1 A, the paper is being fed out in the direction of arrow A and arrow B
It is assumed that optical scanning is performed in the direction of .

If you enlarge Figure 1A, it will look like Figure 1B, and the mark M
1 and M2 have stains ml and m2, and another stain N
also exists.

Therefore, remove these stains and make the correct marks.
/2 must be extracted.

FIG. 2 is a block diagram of a mark processing device according to the present invention, in which reference number 1 is a mark length extraction section, 2 is a mark thinning section, and 3 is a start/stop address determination section.

3 is a time chart showing the operation of the apparatus shown in FIG. 2, and FIGS. 4A, B, and C are flow charts showing the operation of each part of the apparatus shown in FIG. 2.

When the data sheet shown in FIG. 1A on which the function curve is written in the longitudinal direction is set in the scanner 10 shown in FIG. 2 and the start switch (ST) is pressed, each counter shown in FIG.
Each memory and each flip-flop are cleared to initialize the device.

Next, the clock generator 11 starts oscillating, and the pixel signals are sequentially read by the scanner 10 in the direction of arrow B in FIG. 1A.

The address of the pixel signal is given by the coordinates X and y (x=0
~9. y-0 to 33), the first clock signal of the clock signal generator causes the coordinates (0, 0) to be
pixels are read.

In this embodiment, it is assumed that the mark zone M is in the range of y=0 to 9.

It is assumed that the X counter 12 indicates the X coordinate of the scanned pixel, and the X counter 15 indicates the X coordinate of the scanned pixel.

The mark signal extractor 13 selects the contents of the X counter 12 from 0 to 9.
When the output of the scanner 10 is applied to the gate circuit, only the signal related to the mark signal is outputted from the extractor 13.

In the example of FIG. 1B, the pixel at coordinates (0,0) is 0 (white)
Therefore, the M counter 14 that counts the signal length of the mark
is not registered.

Next, according to the clock of the clock generator 11, the contents of the X counter 12 are changed to 1, 2, 3, .・・・・・・It was registered as 9,
Accordingly, pixels (0,1), (0,2).

(0,3), . . . (019) are sequentially scanned.

In this embodiment, these (0, i) pixels are all white, so the M counter 14 is not registered at all.

The X counter 12 generates a carry C when y-9 and returns X
The contents of the counter 15 are incremented by 1, the contents of the M counter 14 are stored in the address (0) specified by the value before the increment of the X counter 15 in the first memory 16, and the scanner 10 is further driven. Then, feed the paper one step in the direction of arrow A in FIG. 1A.

Then each pixel of x = 1 (1toL(i, D.

(1, 2), ... (L9) are scanned.

At this time, the two pixels (1, 3) and (1, 4) are black, so the content of the M counter 14 is 2, and 2 is stored in the address corresponding to X21 in the first memory 16. be done.

The above operations are repeated until the X counter 15 becomes X-10 and a carry is generated, reading out the pixel signals according to the flowchart in FIG. It's crowded.

This situation is as shown in FIG. 3, where the signal of the mark zone M is shown by a solid line, and the signals of the reference line S and function curve G are shown by dotted lines.

Further, at the right end of FIG. 3, the value of the mark length of each line, that is, the content written to the first memory 16 is displayed in a bar graph.

Next, the operation of the mark thinning section 2 shown in FIG. 2 will be explained using FIG. 3 and FIG. 4B.

When a carry is output from the X counter 15, another rank generator 20 starts oscillating.

The second X counter 21 specifies the address to be read from the first memory 16, and is connected to the address input terminal of the first memory 16 along with the output of the first X counter 15.

The output pulse of the clock generator 20 drives the first memory 16 to read the contents of the address specified by the second X counter 21, and the read contents A are compared in size with the contents B of the register 23 by the comparator 22. be done.

The comparator 22 generates an output when A>B, the value of A is written into the register 23, and the contents of the second X counter 21 at that time are written into the register 24.

On the other hand, the read output of the first memory 16 is applied to the flip-flop 26 and the NOT circuit 27 via the OR circuit 25, and the outputs of the NOT circuit 27 and the flip-flop 26 are applied to the AND circuit 28.

Therefore, when the read output of the first memory 16 changes from 1 to O, that is, when x=
3, generates output at x=6, x=9.

It is clear that the contents of the register 23 at this time are the maximum value of the signal length of the mark up to that point, and the contents of the register 24 are the X address giving the maximum value of the signal length of the mark.

When the AND circuit 28 generates an output, the address specified by the register 24 in the second memory 29 is stored in the register 23.
The contents of the register 23 are written and the register 23 is cleared.

The above operation continues until the counter 21 generates a carry, and as a result, the contents of the second memory 29 change from address 2 to 5.
．． Address 5 becomes 3, address 8 becomes 7, and the thinning of the mark is completed.

Note that the register 24 is cleared by the carry of the counter 21.

The flowchart in FIG. 4B shows the above operation.

In this embodiment, the mark is thinned by extracting the maximum length mark component as described above and writing its X coordinate and the value of the maximum flame into the memory. It is also possible to use the center coordinates of the marks.

In this case, the maximum length mark component has an X address such as the central coordinate, and its length is that of the maximum flame.

Next, the operation of the start/stop address determining section 3 is
This will be explained in conjunction with Figure C.

The clock generator 30 is activated by the carry of the counter 21.
starts oscillating.

The counter 31 specifies the address to be read from the second memory 29, and together with the output of the register 24, the second memory 29
is connected to the address input terminal of

The comparator 32 compares the thinning data A read from the second memory 29 with the contents B of the register 36, and generates an output when A>B.

The register 36 stores the signal length of the largest mark read so far and its address.

When the comparator 32 generates an output due to A>B, the AND circuit 37 opens and the contents of the register 36 are transferred to the AND circuit 37.
, and the new value of A is written from memory 29 to register 36.

Note that the register 38 stores the second signal length and its address among the marks read so far.

On the other hand, the comparator 33 compares the thinning data A read from the second memory 29 with the length B stored in the register 38 that holds the length and address of the second largest mark signal. Then, when A is greater than B, the output is
1" is generated.

The output "1" is logically ANDed with the output of the comparator 32 by the NOT circuit 34 and the AND circuit 35, so that the thinning data from the second memory 29 is larger than the largest mark signal length. If the mark signal length is also smaller and larger than the second largest mark signal length, the AND circuit 35 outputs "1".

With the outputs 91 and 91 of this AND circuit 35, the AND circuit 3
9 is opened, and the data from the second memory 29 and the value of the counter 31 specifying the address of the data are written into the register 38.

In the example of FIG. 3, the data output of the second memory 29 read out by the clock of the clock generator 30 is 0, 0, 5°, 0, 3, 0, 0, 3,
O, 0, 7, O”.

Therefore, register 3-6 stores the length 7 of the longest mark and its address 8 (7, 8), and counter 38 stores the length 5 of the second mark and its address 2 (5, 2).
).

When the reading of the second memory 29 is completed, the counter 31 generates a carry, and a process begins in which the addresses of the two mark signals are sorted into a start address and a stop address, respectively, in descending order of address.

The address signals of registers 36 and 38 are input to input terminals A and B of comparator 40, respectively, and the magnitudes are compared.

When the input to input terminal A is greater than the input to input terminal B, the gate of AND circuit 41 opens and registers 36 and 38
The address data AI and A2 are respectively stop register 4.
4. It is input to the start register 43 and output to the outside at the timing of the trailing edge of the carry signal from the counter 31.

On the other hand, when the input to the input terminal A of the comparator 40 is greater than the input to the input terminal A, the gate of the AND circuit 42 is opened, and the address data AI and A2 are respectively transferred to the start register 43. It is input to the stop register 44 and output to the outside at the timing of the trailing edge of the carry signal from the counter 31.

In the example of FIG. 1B, the address data AI and A2 are 8, respectively.
2, the comparator 40 outputs the A>B signal,
The gate of the AND circuit 41 opens.

Therefore, the value fl of A2 is sent to the outside as the start address.
29? , A1 as the stop address +! 8
99 will be output.

As described above, it was possible to remove the dirt signal N in FIG. 1B, make the mark signal thinner, and accurately determine the start/stop address.

In addition, in this embodiment, when counting the mark signal length, a method was used in which pixel signals read by a scanner were directly counted, but it is also possible to count signals after performing simple graphic preprocessing. , it goes without saying that the number of marks is not limited to two for start/stop, but may be arbitrary.

Further, in this embodiment, the operation based on random logic has been described, but it goes without saying that exactly the same processing can be executed by a program using an electronic computer.

As explained above, the present invention thins each mark in a mark zone by making the mark represented by the signal component of its maximum flame, and then outputs only predetermined signals in the order of length among the thinned signals. Since predetermined logic control is performed based on the order in which these signals appear, it is possible to provide a function generator that is less likely to extract incorrect logic signals due to dirt on paper. .

[Brief explanation of drawings]

Figures 1A and 1B are examples of graphs to be read,
FIG. 2 is a block diagram of a function generator according to the present invention, FIG. 3 is an operation time chart of the device shown in FIG. 2, and FIG.
Figures A-C are flowcharts of the operation of the apparatus of Figure 2. 1: Mark length extraction section, 2: Mark thinning section, 3. Start/stop address determination section.

Claims (1)

[Claims] 1 In a function generation method that mechanically reads the distance of a function written on a sheet of paper to a reference line, two sufficiently long straight lines are marked in a mark zone that is created near the function zone on the sheet of paper, and are perpendicular to the reference line. By sequentially scanning the paper, electrical signals corresponding to the functions, marks, and dirt on the paper are obtained, and two marks corresponding to the two marks and dirt in the mark zone are obtained. From the above independent electrical signals, count these signal lengths for each address given in the direction orthogonal to the reference line, and calculate the maximum for each independent electrical signal among the signal lengths counted for each address. detect the signal length and its address, extract two signal lengths from the detected signal lengths in descending order of signal length, and determine reading and termination of the function based on the address of the extracted signal length. A function generation method characterized by obtaining a function output.