JPS59201535A - Analog/digital communication method and device - Google Patents
Analog/digital communication method and deviceInfo
- Publication number
- JPS59201535A JPS59201535A JP7647983A JP7647983A JPS59201535A JP S59201535 A JPS59201535 A JP S59201535A JP 7647983 A JP7647983 A JP 7647983A JP 7647983 A JP7647983 A JP 7647983A JP S59201535 A JPS59201535 A JP S59201535A
- Authority
- JP
- Japan
- Prior art keywords
- analog
- communication device
- digital
- digital signal
- current value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 title claims description 43
- 238000000034 method Methods 0.000 title claims description 13
- 230000005540 biological transmission Effects 0.000 claims description 34
- 238000010586 diagram Methods 0.000 description 13
- 230000004044 response Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 101001106432 Homo sapiens Rod outer segment membrane protein 1 Proteins 0.000 description 1
- 102100021424 Rod outer segment membrane protein 1 Human genes 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
- G08C19/02—Electric signal transmission systems in which the signal transmitted is magnitude of current or voltage
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、工業計測等において、アナログ信号とディジ
タル信号とを同一の伝送路によシ伝送する場合に適用さ
れるアナログ・ディジタル通信方法およびその装置に関
するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an analog/digital communication method and its method that are applied when analog and digital signals are transmitted over the same transmission path in industrial measurement, etc. It is related to the device.
従来、工業計測においては、差圧発信器、電磁流量計等
の測定出力を遠隔地点へ伝送する場合、一般に4〜20
mA等の統一信号が用いられておシ、このアナログ信号
の電流値によシ測定値を示すものとなっている。Conventionally, in industrial measurement, when transmitting the measurement output of a differential pressure transmitter, electromagnetic flow meter, etc. to a remote point, it is generally 4 to 20 minutes.
A unified signal such as mA is used, and the measured value is indicated by the current value of this analog signal.
しかし、差圧発信器、電磁流量側等は、広域に分散のう
え設置されるのが一般的であシ、これらの調整および動
作状況チェックを行なうには、係員が巡回のうえ保守9
点検作業を行なわねばならず、既存の設備を利用して遠
隔操作により、調整および動作状況チェック等をも行な
うことのできる手段の出現が要望されるに至っている。However, differential pressure transmitters, electromagnetic flow sides, etc. are generally installed in a distributed manner over a wide area, and in order to adjust them and check their operating status, staff must patrol and conduct maintenance 9.
Inspection work must be carried out, and there is a growing demand for a means that can make adjustments, check operating conditions, etc. by remote control using existing equipment.
本発明は、従来のかかる要望に基づいてなされたもので
あシ、第1の目的は、差圧発信器、電磁流量計等の発信
器と通信器との間において、アナログ信号と重畳のうえ
ディジタル信号の送受信を自在とするアナログ・ディジ
タル通信方法を提供するものであって、この目的を達成
するため、電源部から供給される電流値を発信器によシ
変化させてアナログ信号とする通信方法において、前記
アナログ信号の通ずる伝送路中へ電圧降下素子を挿入し
、該電圧降下素子に通ずる前記アナログ信号と重畳のう
え前記電流値を通信器によシパルス状に正負方向へ変化
させてディジタル信号とし、該ディジタル信号を前記発
信器によシ受信すると共に、前記アナログ信号と重畳の
うえ前記電流値を前記発信器によシパルス状に正負方向
へ変化させてディジタル信号とし、該ディジタル信号を
前記通信器によシ受信することを特徴として構成したも
のである。The present invention has been made based on such a conventional demand, and the first object is to superimpose analog signals and It provides an analog/digital communication method that allows the free transmission and reception of digital signals, and in order to achieve this purpose, a communication method in which the current value supplied from the power supply section is changed by a transmitter to produce an analog signal. In the method, a voltage drop element is inserted into a transmission path through which the analog signal passes, and the current value is superimposed on the analog signal passed through the voltage drop element, and the current value is changed in a pulse-like manner in a positive and negative direction by a communication device to convert the current value into a digital signal. The digital signal is received by the transmitter, the current value is superimposed on the analog signal, and the current value is changed in the positive and negative directions by the transmitter to generate a digital signal, and the digital signal is converted into a digital signal. This configuration is characterized in that the communication is received by the communication device.
第2の目的は、発信器と通信器との間において、アナロ
グ信号と重畳のうえディジタル信号の送受信を自在とし
たアナログ・ディジタル通信装置を提供するものであシ
、この目的を達成するため、伝送路へ電流を供給する電
源部と、前記伝送路へ接続されかつ該伝送路の電流値を
変化させてアナログ信号とする発信器とからなる通信装
置において、前記伝送路へ挿入された電圧降下素子と、
該電圧降下素子よシも前記発信器側の伝送路へ橋絡接続
された前記アナログ信号と重畳のうえ前記電圧降下素子
の電流値をパルス状に正負方向へ変化させディジタル信
号として送信しかつ同様のディジタル信号を受信する通
信器と、該通信器から送信された前記ディジタル信号を
受信しかつ前記アナログ信号と重畳のうえ前記伝送路の
電流値をノくルス状に正負方向へ変化させディジタル信
号として前記通信器へ送信する前記発信器とを備えたこ
とを特徴として構成したものである。The second object is to provide an analog/digital communication device that can freely send and receive digital signals in addition to analog signals between a transmitter and a communication device. In a communication device consisting of a power supply unit that supplies current to a transmission line and an oscillator that is connected to the transmission line and changes the current value of the transmission line to generate an analog signal, a voltage drop inserted into the transmission line Motoko and
The voltage drop element is also superimposed with the analog signal bridge-connected to the transmission line on the transmitter side, and changes the current value of the voltage drop element in a pulse-like manner in positive and negative directions, and transmits it as a digital signal, and the same. a communication device that receives the digital signal transmitted from the communication device, superimposes it on the analog signal, and changes the current value of the transmission path in a positive/negative direction in a spiral shape to generate a digital signal; and the transmitter for transmitting data to the communication device.
以下、実施例を示す図によって本発明の詳細な説明する
。Hereinafter, the present invention will be explained in detail with reference to figures showing examples.
第1図は、全構成のブロック図であシ、線路L1 +L
2かちなる2線式伝送路(以下、伝送路)に対し電流を
供給する電源部psが設けられていると共に、伝送路の
他端には、差圧発信器、電磁流量計等の発信器Txが接
続されておシ、発信器Txが電流値■を制御し、アナロ
グ信号として伝送路へ通ずるものとなっている。Figure 1 is a block diagram of the entire configuration, line L1 +L
A power supply unit PS is provided to supply current to a two-wire transmission line (hereinafter referred to as a transmission line), and the other end of the transmission line is equipped with a transmitter such as a differential pressure transmitter or an electromagnetic flowmeter. When Tx is connected, the oscillator Tx controls the current value (2) and passes it to the transmission line as an analog signal.
また、伝送路中には、電圧降下素子として抵抗器RLが
直列に挿入されておシ、これの端子電圧をアナログ・デ
ィジタル変換器(以下、ADC)へ与え、ディジタル信
号としてから数字表示器等の表示器DPを駆動し、電流
値工によって示されるアナログ信号の値を受信のうえ表
示するものとなっている。In addition, a resistor RL is inserted in series as a voltage drop element in the transmission line, and the terminal voltage of this is applied to an analog-to-digital converter (hereinafter referred to as ADC), which converts it into a digital signal and converts it into a numeric display, etc. The display device DP is driven, and the value of the analog signal indicated by the current value is received and displayed.
一方、抵抗器RLよシも発信器’rx側の伝送路には、
通信器CEが橋絡接続されておシ、これがアナログ信号
と重畳のうえ抵抗器RLに通ずる電流値■をパルス状に
正負方向へ変化させ、ディジタル信号として発信器Tx
へ送信すると、これが発信器Txにおいて受信され、受
信に応じて発信器TXが電流値工を同様に変化させ、デ
ィジタル信号として通信器CEへ送信するため、これが
通信器CEにおいて受信されるものとなっている。On the other hand, both the resistor RL and the transmission line on the oscillator'rx side have
The communication device CE is connected as a bridge, and this superimposes the analog signal and changes the current value flowing through the resistor RL in a pulse-like positive and negative direction, and transmits it as a digital signal to the transmitter Tx.
This is received by the transmitter Tx, and in response to the reception, the transmitter TX similarly changes the current value and transmits it as a digital signal to the communication device CE, so it is assumed that this is received by the communication device CE. It has become.
第2図は、抵抗器RLに通ずる電流値Iの時間tに応す
る変化状況を示す波形図であシ、発信器TXの測定値に
応じて定まるアナログ信号Saは、この場合4〜20m
Aの範囲において変化するものとなっているが、通信器
CEからの送信が行なわれると、ディジタル信号Scの
期間、アナログ信号S8と重畳のうえ、パルス状に正負
方向へ電流値工が変化し、これによって7ラグビツトB
F、スタートビットBs、第1ビツトB1〜第8ビツト
B8が送信される。FIG. 2 is a waveform diagram showing how the current value I flowing through the resistor RL changes over time t.
It changes within the range of A, but when the communication device CE sends a signal, the current value changes in the positive and negative directions in a pulsed manner during the period of the digital signal Sc, and is superimposed on the analog signal S8. , this results in 7 lag bits B
F, start bit Bs, and first bit B1 to eighth bit B8 are transmitted.
なお、各ビットは、正負方向の変化により示され、フラ
グピッ)BFは特にパルス幅が広く設定され、かつ必ず
正負方向へ変化するものとなっているが、データを示す
第1ビツトB1〜第8ピツ)Bsは、論理値”1″のと
き正負方向へ変化し、論理値”0″のときには無変化を
維持するものとなっている。Each bit is indicated by a change in the positive/negative direction, and the pulse width of the flag (B) BF is set particularly wide and always changes in the positive/negative direction. Bs changes in the positive and negative directions when the logic value is "1", and remains unchanged when the logic value is "0".
この電流値変化は、抵抗器RLの1L圧降下変化を生じ
、発信器’rx側の線路L1.L2間電圧変化として発
信器TXへ与えられ、これによってディジタル信号S0
が発信器’rxによシ受信される。This current value change causes a 1L voltage drop change in the resistor RL, and the line L1. It is applied to the oscillator TX as a voltage change across L2, thereby causing the digital signal S0
is received by the transmitter 'rx.
すると、発信器TXは、ディジタル信号Scの終了後、
一定期間tsを糸Jうでからディジタル信号Stの期間
、同様に電流値■を変化させ、フラグピッ)BF、スタ
ートビットBsおよび、データを示す第1ビツトB1〜
第8ピツ)Bsを送信する。Then, after the end of the digital signal Sc, the transmitter TX
After passing the string ts for a certain period of time, the current value ■ is similarly changed during the period of the digital signal St, and the flag BF, start bit Bs, and first bit B1 to indicate data are changed.
8th Pitsu) Send Bs.
このため、前述と同様に線路L1.L2間の電圧変化が
生じ、これが通信器CEによシ受信される。Therefore, as described above, the line L1. A voltage change occurs across L2, which is received by the communicator CE.
ただし、この例では、8ビツトからなる1バイトの送受
信のみを示したが、状況に応じ、所定数のビットからな
る所望数のバイトがディジタル信号5etStの各々に
おいて送受信される。However, in this example, only the transmission and reception of one byte consisting of 8 bits is shown, but depending on the situation, a desired number of bytes consisting of a predetermined number of bits can be transmitted and received in each digital signal 5etSt.
なお、各ビットの正負方向変化は同一電流値となってお
シ、これらの平均値が零となるため、第1図のADC−
A/Dにおいて、入力側へ積分回路等を挿入すれば、ア
ナログ信号Saの受信には全く無関係となる。Note that changes in the positive and negative directions of each bit result in the same current value, and their average value becomes zero, so the ADC-
In an A/D, if an integrating circuit or the like is inserted on the input side, it becomes completely unrelated to the reception of the analog signal Sa.
第3図は、通信器CEのブロック図であシ、マイクロプ
ロセッサ等のプロセッサCPUcを中心とし、固定メモ
リROMc、可変メモリRAM0、キーボードKBc、
数字表示器等の表示器DPc、ユニバーサル非同期送受
信部(以下、送受信部) UARTcおよびインターフ
ェイスI/Fc等が周辺に配され、母線BUcによシ相
互間が接続されておシ、固定メモII ROMcへ格納
されたプログラムをプロセッサCPUcが実行し、所定
のデータを可変メモリRAM cヘアクセスしながら制
御動作を行なうものとなっている。FIG. 3 is a block diagram of the communication device CE, which mainly includes a processor CPUc such as a microprocessor, a fixed memory ROMc, a variable memory RAM0, a keyboard KBc,
A display device such as a numeric display DPc, a universal asynchronous transmitter/receiver unit (hereinafter referred to as a transmitter/receiver unit), a UARTc, an interface I/Fc, etc. are arranged around the periphery, and they are connected to each other by a bus BUc. The processor CPUc executes the program stored in the variable memory RAM c, and performs control operations while accessing predetermined data to the variable memory RAM c.
ここにおいて、キーボードKBcから所望のデータを与
えれば、これに応じてプロセッサCPUcが送受信部U
ART cを制御すると共に、インターフエイスエ/F
cを介してゲートパルスPcg□をH”(高レベル)と
して送出するため、ANDゲートGcl+Gc2がオン
となシ、送受信部UART oから送出される各々“H
″′の増加パルスPuおよび減少パルスPdが電流制御
部CCoへ与えられ、増加パルスPuに応じて電流制御
部CCcが線路端子T1からT2への電流Ieを通ずる
一方、減少パルスPdに応じて同制御部CCcが線路端
子Tlを正極、線路端子T2を負極とする制御電圧を送
出する。Here, if desired data is given from the keyboard KBc, the processor CPUc will respond to the transmitter/receiver unit U.
In addition to controlling ART c, interface
In order to send out the gate pulse Pcg□ as "H" (high level) through the transmitter/receiver UART o, AND gate Gcl+Gc2 is on,
An increasing pulse Pu and a decreasing pulse Pd of ``'' are applied to the current control section CCo, and the current controlling section CCc passes the current Ie from the line terminal T1 to T2 in response to the increasing pulse Pu, while passing the current Ie from the line terminal T1 to T2 in response to the decreasing pulse Pd. The control unit CCc sends out a control voltage with the line terminal Tl as a positive pole and the line terminal T2 as a negative pole.
しだがって、電流Icが通じたときには、抵抗器RLを
通ずる電流値工が、アナログ信号Saを示す電流工tと
電流Icとの和となって増加する反面、制御電圧が送出
されたときには、線路L1 r ” 2間の電圧が上昇
し、電流値Iが減少する。Therefore, when the current Ic passes, the current value flowing through the resistor RL increases as the sum of the current value t indicating the analog signal Sa and the current Ic, but on the other hand, when the control voltage is sent out, , the voltage between the lines L1 r ''2 increases, and the current value I decreases.
また、線路L1+”2間の線間電圧は、デイジタル信号
Siの周波数成分のみを通過させる帯域泥波器等の沖波
器FLcを介し、比較器cPcの一方の入力へ与えられ
ておシ、他方の入力へ与えられている基準電圧Ec8と
の比較がなされ、基準電圧Ec8以上のレベルが受信出
力とじて抽出されるものとなっている。In addition, the line voltage between the lines L1+"2 is applied to one input of the comparator cPc via an offshore transducer FLc such as a bandpass transducer that passes only the frequency component of the digital signal Si, and the other A comparison is made with a reference voltage Ec8 applied to the input of the reference voltage Ec8, and a level higher than the reference voltage Ec8 is extracted as a received output.
このため、ディジタル信号scの送信終了後、ディジタ
ル信号StのフラグビットBFと対応する受信出力がイ
ンターフェイスエ/Fcを介して与えられるのに応じ、
インターフェイスエ/FcがらゲートパルスPeg2を
“H″として送出し、ANDゲートGc3をオンとすれ
ば、スタートビットB8以降と対応する受信出力が送受
信部UART cへ与えられ、とれの出力に応じて表示
器DPcによる受信データの表示が行なわれる。Therefore, after the transmission of the digital signal sc is completed, in response to the reception output corresponding to the flag bit BF of the digital signal St being given via the interface E/Fc,
When the gate pulse Peg2 is sent as "H" from the interface E/Fc and the AND gate Gc3 is turned on, the reception output corresponding to the start bit B8 and after is given to the transmitting/receiving section UART c, and is displayed according to the output of the gate. The received data is displayed by the device DPc.
第4図は、電流制御部cccの回路図であシ、抵抗器R
1およびコンデンサc1による雑音除去用の低域ろ波器
を介するANDゲー)Gelがらの増加パルスPuは、
差動増幅器A1にょシ増幅されfc5え、電界効果形等
のトランジスタQ1をオンとするため、抵抗器R2+
R3を経て踵流工。が通ずる。Figure 4 is a circuit diagram of the current control section ccc, and the resistor R
1 and capacitor c1 through a low-pass filter for noise removal)
The differential amplifier A1 is amplified by fc5, and in order to turn on the field effect transistor Q1, the resistor R2+
After R3, he moved to heel style. is understood.
なお、抵抗器R3の端子電圧は、抵抗器R4を介して差
動増幅器A1へ負帰還されておシ、これによって電流!
。が所定の値に保たれる。Note that the terminal voltage of the resistor R3 is negatively fed back to the differential amplifier A1 via the resistor R4, so that the current!
. is kept at a predetermined value.
一方、抵抗器R5およびコンデンサc2による前述と同
様の低域E波器を介する凧ゲー) Ga4からの減少パ
ルスPdは、差動増幅器A2にょシ反転増幅されたうえ
、前述と同様のトランジスタQ2をオンとするため、抵
抗器R6+R7を介し、直列に挿入された局部電源Ec
Lの電圧が制御電圧として送出される。On the other hand, the decreasing pulse Pd from Ga4 is inverted and amplified by the differential amplifier A2 through the same low-frequency E-wave generator as described above with resistor R5 and capacitor c2, and is also inverted and amplified by the differential amplifier A2. To turn on, the local power supply Ec is inserted in series through resistors R6+R7.
The voltage of L is sent out as a control voltage.
なお1抵抗器R7の端子電圧は、抵抗器R8を介して差
動増幅器A2へ負帰還されており、局部電源EcLから
の電流を所定の値に保っている。Note that the terminal voltage of one resistor R7 is negatively fed back to the differential amplifier A2 via the resistor R8, and the current from the local power supply EcL is maintained at a predetermined value.
第5図は、通信器CEの外形斜視図であり、手持形のケ
ース1に表示器DPcおよびキーボードKBcが配され
ていると共に、コード2が導出されておシ、コード2の
先端にはクリップ3が接続され、線路L1 r ” 2
に対する着脱が自在となっている。FIG. 5 is an external perspective view of the communication device CE, in which a display device DPc and a keyboard KBc are arranged in a hand-held case 1, a cord 2 is led out, and a clip is attached to the tip of the cord 2. 3 is connected and the line L1 r ” 2
It can be attached and detached freely.
第6図は、発信器Txのブロック図であシ、第3図と同
様のプロセッサCPUt、固定メモリROMt1可変メ
モリRAMt)送受信部UARTj、インターフェイス
I/F j等を母線BUtによシ接続し、第3図と同様
にプロセッサCPUjが制御動作を行なうものとなって
いるが、差圧、流量等を検出するセンサSSの出力をデ
ィジタル信号へ変換するADC−VO2、および、これ
の出力をプロセッサCPUjが処理のうえ送出するディ
ジタル信号をアナログ信号へ変換するディジタル・アナ
ログ変換器(以下、DAC)D/Atが設けである。FIG. 6 is a block diagram of the transmitter Tx, in which the same processor CPUt, fixed memory ROMt1, variable memory RAMt, transmitting/receiving unit UARTj, interface I/F j, etc. as in FIG. 3 are connected to the bus BUt. As in FIG. 3, the processor CPUj performs the control operation, but the ADC-VO2 converts the output of the sensor SS that detects differential pressure, flow rate, etc. into a digital signal, and the output of this is sent to the processor CPUj. A digital-to-analog converter (hereinafter referred to as DAC) D/At is provided for converting the digital signal processed and sent by the converter into an analog signal.
また、線路端子T1には、電源回路Pstが接続され、
この場合は、線路L1から4mAの電流を取り入れ、安
定化のうえ局部電源Etとして各部へ供給していると共
に、線路L1sL2間の線間電圧は、ディジタル信号S
cの周波数成分のみを通過させる帯域泥波器等のF波器
FLiを介し、第3図と同様に比較器CPtへ与えられ
ておシ、ここにおいて、第3図と同様に基準電圧Ets
と比較され、比較器CPjが受信出力を生じ、インター
フェイスI/Ftへ与えると共に、瓜ゲー)Gtlを介
して送受信部UART jへ与えるものとなっている。Further, a power supply circuit Pst is connected to the line terminal T1,
In this case, a current of 4 mA is taken from the line L1, stabilized and then supplied to each part as a local power supply Et, and the line voltage between the lines L1 and L2 is determined by the digital signal S.
Similarly to FIG. 3, the reference voltage Ets is applied to the comparator CPt via an F-wave device FLi such as a band-pass wave device that passes only the frequency component of c.
The comparator CPj generates a reception output, which is applied to the interface I/Ft, and also to the transmitter/receiver unit UARTj via Gtl.
このため、フラグビットBvの検出に応じて1”のゲー
トパルスPtg1が送出され、ANDゲー)Gttがオ
ンとなってディジクル信号Scの受信がなされ、ディジ
タル信号Scの受信終了後、期間t8の経過に応じ、プ
ロセッサCPU tがインターフェイスI/Ftを介し
”H”のゲートパルスPtg□を送出すると共に、送受
信部UART iを制御すれば、オンとなったANDゲ
ー)Gt2を介し、パルス状に正負方向へ変化する送信
データが送出され、加算器ADD jの一方の入力へ与
えられる。Therefore, in response to the detection of the flag bit Bv, a gate pulse Ptg1 of 1" is sent out, the AND gate) Gtt is turned on, and the digital signal Sc is received. After the reception of the digital signal Sc is completed, a period t8 elapses. In response to this, the processor CPU t sends out an "H" gate pulse Ptg□ via the interface I/Ft, and controls the transmitting/receiving unit UART i, which then outputs a positive/negative pulse in the form of a pulse via the AND gate (Gt2) which is turned on. Transmission data varying in direction is sent out and applied to one input of an adder ADD j.
なお、加算器ADD jの他方の入力には、センサ88
による測定値に応じたアナログ信号が定常的に与えられ
ておシ、ゲートパルスPtg2が生じないときは、DA
C−D/Atの出力のみが電流制御部CCtへ与えられ
、これには、測定値に応じた値の電流がアナログ信号S
8として通ずるのに対し、ゲートパルス”tg2が生じ
かつ送信データが送受信部UARTjから送出されれば
、加算器ADDtにおいて両人力の加算がなされるため
、アナログ信号SILと重畳のうえ、電流制御部C(4
に通ずる電流がパルス状に正負方向へ変化し、ディジタ
ル信号stとして送信される。Note that the other input of the adder ADD j is connected to a sensor 88.
When the analog signal corresponding to the measured value by DA is constantly applied and the gate pulse Ptg2 is not generated, DA
Only the output of CD/At is given to the current control section CCt, which has a current value corresponding to the measured value as an analog signal S.
On the other hand, if the gate pulse "tg2" is generated and the transmission data is sent from the transmitting/receiving unit UARTj, the adder ADDt adds the power of both hands, so it is superimposed with the analog signal SIL and the current control unit C(4
The current flowing through the terminal changes in the positive and negative directions in a pulse-like manner, and is transmitted as a digital signal st.
ただし、アナログ信号SaO値とディジタル信号Stに
応するデータとをプロセッサCPUjにおいて加算のう
え、DAC−D/Aiから送出し、加算器ADDjを省
略するものとしても同様である。なお、発信器TXは、
EAROM等の不揮発性メモリを有し、通信器CEから
のデータ中必要なものは、このメモリに書き込むものと
している。このため、電源断等の場合にもデータが保持
されるものとなっている。However, the same effect can be obtained even if the analog signal SaO value and the data corresponding to the digital signal St are added together in the processor CPUj and sent out from the DAC-D/Ai, and the adder ADDj is omitted. In addition, the transmitter TX is
It has a nonvolatile memory such as EAROM, and necessary data from the communication device CE is written into this memory. For this reason, data is retained even in the event of a power outage or the like.
第7図は、電流制御部CCtの回路図であシ、第4図の
トランジスタQl側と同様、抵抗器R11、コンデンサ
C11の低域P波器を介し、加算器ADD tの出力を
差動増幅器Allによシ増幅のうえ、トランジスタQl
lの内部インピーダンスを制御しておシ、これによって
定まる電流を抵抗器”12+R13を経て通ずるものと
している。FIG. 7 is a circuit diagram of the current control unit CCt. Similar to the transistor Ql side in FIG. After amplification by amplifier All, transistor Ql
The internal impedance of I is controlled, and the current determined by this is passed through the resistor "12+R13."
ただし、第4図と同様に抵抗器R13の端子電圧が抵抗
器R14を介し、差動増幅器Allへ負帰還されておシ
、加算器ADDjの出力値に応する電流値を保つものと
なっている。However, as in Fig. 4, the terminal voltage of the resistor R13 is negatively fed back to the differential amplifier All via the resistor R14, and the current value corresponding to the output value of the adder ADDj is maintained. There is.
第8図は、他の実施例を示す全構成のブロック図であシ
、第1図におけるADC−A/Dおよび表示器DPO代
シに、低インピーダンスの電流計Aが挿入され、これに
よってアナログ係号Saの指示を行なうものになってい
ると共に、伝送回路中へ挿入された抵抗器RLの端子電
圧を通信器CEへ取υ入れ、ADC−A/Dcによりデ
ィジクル信号としたうえ、表示器DP caを駆服!シ
、ここにおいても、アナログ係号S、の受信を行なうも
のとしている。FIG. 8 is a block diagram of the entire configuration showing another embodiment. A low impedance ammeter A is inserted in place of the ADC-A/D and display DPO in FIG. The terminal voltage of the resistor RL inserted into the transmission circuit is input to the communication device CE, converted into a digital signal by the ADC-A/Dc, and then sent to the display. Defeat DP ca! Also here, it is assumed that the analog signal S is received.
なお、データ送受信部DSRは、第3図に示すものと同
様である。Note that the data transmitting/receiving section DSR is similar to that shown in FIG.
したがって、伝送路を収容する端子板等へ通信器CEを
接続し、所望のデータ送受信を発信器’rxと行なうこ
とが自在となシ、発信器’rxの可変メモIJ RAM
t中へ格納されている各種調整値、設定値等の更新が遠
隔操作によシ可能になると共に、発信器’rxの動作状
況を遠隔チェックすることが可能となるうえ、従来から
の設備に若干の追加を行なうのみによシ目的を達するこ
とができる。Therefore, it is possible to freely connect the communication device CE to a terminal board etc. that accommodates a transmission line and perform desired data transmission and reception with the transmitter 'rx.
It is now possible to update various adjustment values, setting values, etc. stored in the t by remote control, and it is also possible to remotely check the operating status of the transmitter With only a few additions, the desired goal can be achieved.
ただし、第1図および第8図において、発信器’rx用
の電源を別途の線路にょシ供給するものとし、あるいは
、抵抗器RLO代力に他のインピーダンス素子を用いて
もよく、第2図においては、各バイト毎にパリティチェ
ック用のビットを付加し、あるいは、ディジタル信号S
tに発信器Txの個別コードを付加するものとして同様
であり、第3図、第4図、第6図、第7図の構成は、状
況に応じて選定が任意であると共に、第5図の形状は、
手持形に限らず、パネル実装形等とし、スイッチによシ
伝送路の選択および接続を行なうものとしてもよく、通
信器CFから送信のみを行ない、発信器’rxが受信の
みを行なうものとしても場合によっては十分である等、
種々の変形が自在である。However, in FIGS. 1 and 8, the power source for the oscillator 'rx may be supplied to a separate line, or another impedance element may be used for the resistor RLO power. , a bit for parity check is added to each byte, or a digital signal S
The configurations shown in FIGS. 3, 4, 6, and 7 can be selected arbitrarily depending on the situation, and the configurations shown in FIG. The shape of
It is not limited to a hand-held type, but may be a panel-mounted type, etc., and a switch may be used to select and connect the transmission path, or the transmitter CF may only transmit, and the transmitter 'rx may only receive. In some cases, it is sufficient, etc.
Various modifications are possible.
以上の説明によシ明らかなとおり本発明によれば、既存
の設備を大幅に変更することなく、差圧発信器、電磁流
量計等の発信器とデータの送受信が自在となり、かつ、
アナログ信号の受信に対して影響を与えないため、各種
発信器の遠隔H1,′il整および動作状況監視上、顕
著な効果が得られる。As is clear from the above description, according to the present invention, it is possible to freely transmit and receive data to and from transmitters such as differential pressure transmitters and electromagnetic flowmeters without significantly changing existing equipment, and
Since it does not affect the reception of analog signals, significant effects can be obtained in remotely adjusting H1,'il and monitoring the operating status of various transmitters.
図は本発明の実施例を示し、第1図は全構成のブロック
図、第2図は電流値の波形図、第3図は通信器のブロッ
ク図、第4図は第3図における電流制御部の回路図、第
5図は通信器の外形斜視図、第6図は発信器のブロック
図、第7図は第6図における電流制御部の回路図、第8
図は他の実施例を示す全構成のブロック図である。
’rx・・・−発信器、PS・・・・電源部、Ll。
L2・・・・線路、CE・・・・通信器、■・・・・電
流値、PL、・・・・抵抗器(電圧降下素子)、Sa・
・・・アナログ信号、sc、sj ・・・・ディジタル
信号、CPUo、 CPUt@・・・プロセッサ、RO
M、 、 ROM1・・・・固定メモリ、RAMc、
RAMt・−・・可変メモリ、UARTc、UARTj
−@−・送受信部、KBce・・・キーボード、DP
e r DP elk・・・・・表示器、I/Fc+
I/Fj・・・・インターフェイス、FLc、FLt・
・・・沖波器、CPc、CPj・・・・比較器、Ecs
+ Ets ・・・・基準電圧、CCc、CCt・
・・・電流制御部、EcL・・・・局部電源、D/At
・・・・DAC(ディジタル・アナログ変換器)、SW
t・・・・スイッチ回路、Ct・e・−コンデンサ、A
/Dc・・−−ADC(アナログ・ディジタル変換器)
、3・・・・クリップ。
特許出願人 山武ハネウェル株式会社代理人 山川政
樹(ほか1名)
貧1図
第2図
■The figures show an embodiment of the present invention, Fig. 1 is a block diagram of the entire configuration, Fig. 2 is a waveform diagram of current values, Fig. 3 is a block diagram of a communication device, and Fig. 4 is the current control in Fig. 3. 5 is an external perspective view of the communication device, FIG. 6 is a block diagram of the transmitter, FIG. 7 is a circuit diagram of the current control section in FIG. 6, and FIG.
The figure is a block diagram of the entire configuration showing another embodiment. 'rx...-transmitter, PS...power supply section, Ll. L2...Line, CE...Communication device, ■...Current value, PL,...Resistor (voltage drop element), Sa...
...Analog signal, sc, sj ...Digital signal, CPUo, CPUt@...Processor, RO
M, , ROM1...Fixed memory, RAMc,
RAMt --- Variable memory, UARTc, UARTj
-@-・Transmission/reception section, KBce...Keyboard, DP
e r DP elk...Display, I/Fc+
I/Fj・・・Interface, FLc, FLt・
...Okiwaki, CPc, CPj...Comparator, Ecs
+ Ets...Reference voltage, CCc, CCt・
...Current control unit, EcL...Local power supply, D/At
...DAC (digital-to-analog converter), SW
t...Switch circuit, Ct・e...-capacitor, A
/Dc...--ADC (analog-digital converter)
, 3...Clip. Patent applicant Yamatake Honeywell Co., Ltd. Agent Masaki Yamakawa (and one other person) Poverty 1 Figure 2 ■
Claims (7)
させてアナログ信号とする通信方法において、前記アナ
ログ信号の通ずる伝送路中へ電圧降下素子を挿入し、該
電圧降下素子に通ずる前記アナログ信号と重畳のうえ前
記電流値を通信器によシバルス状に正負方向へ変化させ
てディジタル信号とし、該ディジタル信号を前記発信器
によシ受信すると共に、前記アナログ信号と重畳のうえ
前記電流値を前記発信器によシバルス状に正負方向へ変
化させてディジタル信号とし、該ディジタル信号を前記
通信器によシ受信することを特徴としたアナログ・ディ
ジタル通信方法。(1) In a communication method in which a current value supplied from a power source is changed by an oscillator to generate an analog signal, a voltage drop element is inserted into a transmission path through which the analog signal passes, and the voltage drop element is connected to the voltage drop element. After being superimposed on the analog signal, the current value is changed in positive and negative directions by a communication device to produce a digital signal, and the digital signal is received by the transmitter, and the current value is superimposed on the analog signal and then changed into a digital signal. An analog/digital communication method characterized in that the current value is changed in positive and negative directions by the transmitter to generate a digital signal, and the digital signal is received by the communication device.
接続されかつ該伝送路の電流値を変化させてアナログ信
号とする発信器とからなる通信装置において、前記伝送
路へ挿入された電圧降下素子と、該電圧降下素子よシも
前記発信器側の伝送路へ橋絡接続された前記アナログ信
号と重畳のうえ前言己電圧降下素子の電流値をパルス状
に正負方向へ変化させディジタル信号として送信しかつ
同様のディジタル信号を受信する通信器と、該通信器か
ら送信された前記ディジタル信号を受信しかつ前記アナ
ログ信号と重畳のうえ前記電圧降下素子の電流値をパル
ス状に正負方向へ変化させディジタル信号として前記通
信器へ送信する前記発信器とを備えたことを特徴とする
アナログ・ディジタル通信装置。(2) A communication device comprising a power supply unit that supplies current to a transmission line, and a transmitter connected to the transmission line and changing the current value of the transmission line to generate an analog signal, which is inserted into the transmission line. The voltage drop element is superimposed with the analog signal bridge-connected to the transmission line on the oscillator side, and the current value of the voltage drop element is changed in a pulse-like manner in positive and negative directions. a communication device that transmits as a digital signal and receives a similar digital signal; and a communication device that receives the digital signal transmitted from the communication device and superimposes it with the analog signal, and then converts the current value of the voltage drop element into a positive or negative pulse shape. An analog/digital communication device comprising: the transmitter that changes direction and transmits the signal as a digital signal to the communication device.
部から供給される電流を電源とする発信器を用いたこと
を特徴とする特許請求の範囲第1項または第2項記載の
アナログ・ディジタル通信方法またはその装置。(3) The analog according to claim 1 or 2, characterized in that a two-wire transmission line is used as the transmission line, and an oscillator whose power source is a current supplied from a power supply section.・Digital communication methods or devices.
を特徴とする特許請求の範囲第1項または第2項記載の
アナログ・ディジタル通信方法またはその装置。(4) The analog/digital communication method or device according to claim 1 or 2, characterized in that a communication device is used that is detachable from the transmission path.
する特許請求の範囲第1項または第2項記載のアナログ
・ディジタル通信方法またはその装置。(5) The analog/digital communication method or device according to claim 1 or 2, characterized in that a resistor is used as the voltage drop element.
る発信器および通信器を用いたことを特徴とする特許請
求の範囲第1項または第2項記載のアナログ・ディジタ
ル通信方法またはその装置。(6) The analog/digital communication method or device according to claim 1 or 2, characterized in that it uses a transmitter and a communication device that are controlled by a processor that executes a program.
基づきアナログ信号を受信する回路を備えた通信器を用
いたことを特徴とする特許請求の範囲第1項または第2
項記載のアナログ・ディジタル通信方法またはその装置
。(7) Claim 1 or 2, characterized in that a communication device is used that is equipped with a circuit that receives an analog signal based on the terminal voltage of a voltage drop element inserted into a transmission circuit.
The analog/digital communication method or device described in Section 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7647983A JPS59201535A (en) | 1983-04-30 | 1983-04-30 | Analog/digital communication method and device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7647983A JPS59201535A (en) | 1983-04-30 | 1983-04-30 | Analog/digital communication method and device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9009689A Division JPH01302928A (en) | 1989-04-10 | 1989-04-10 | Analog/digital communication method and device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59201535A true JPS59201535A (en) | 1984-11-15 |
JPS6323692B2 JPS6323692B2 (en) | 1988-05-17 |
Family
ID=13606325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7647983A Granted JPS59201535A (en) | 1983-04-30 | 1983-04-30 | Analog/digital communication method and device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59201535A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0298237A (en) * | 1988-10-05 | 1990-04-10 | Yokogawa Electric Corp | Contact signal superimposing type 2-wire signal transmitter |
DE4021258A1 (en) * | 1989-07-04 | 1991-01-17 | Hitachi Ltd | Field sensor communication system - uses digital techniques to collect data from sensors and transmit analog current values |
US5184121A (en) * | 1989-03-03 | 1993-02-02 | Hitachi, Ltd. | Field sensor communication method and system |
US5717385A (en) * | 1990-11-28 | 1998-02-10 | Hitachi, Ltd. | Field bus system and virtual field apparatus |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5652958A (en) * | 1979-10-06 | 1981-05-12 | Meisei Electric Co Ltd | Control signal transmission system of key telephone system |
JPS56140494A (en) * | 1980-04-02 | 1981-11-02 | Hokushin Electric Works | Process amount signal transmitting system |
JPS56153497A (en) * | 1980-04-30 | 1981-11-27 | Fuji Electric Co Ltd | Two-wire type measured value transmission system |
JPS5829097A (en) * | 1981-08-15 | 1983-02-21 | 富士電機株式会社 | 2-wire type measuring apparatus |
JPS5848198A (en) * | 1981-09-16 | 1983-03-22 | 株式会社東芝 | Two-wire transmitter |
-
1983
- 1983-04-30 JP JP7647983A patent/JPS59201535A/en active Granted
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5652958A (en) * | 1979-10-06 | 1981-05-12 | Meisei Electric Co Ltd | Control signal transmission system of key telephone system |
JPS56140494A (en) * | 1980-04-02 | 1981-11-02 | Hokushin Electric Works | Process amount signal transmitting system |
JPS56153497A (en) * | 1980-04-30 | 1981-11-27 | Fuji Electric Co Ltd | Two-wire type measured value transmission system |
JPS5829097A (en) * | 1981-08-15 | 1983-02-21 | 富士電機株式会社 | 2-wire type measuring apparatus |
JPS5848198A (en) * | 1981-09-16 | 1983-03-22 | 株式会社東芝 | Two-wire transmitter |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0298237A (en) * | 1988-10-05 | 1990-04-10 | Yokogawa Electric Corp | Contact signal superimposing type 2-wire signal transmitter |
US5184121A (en) * | 1989-03-03 | 1993-02-02 | Hitachi, Ltd. | Field sensor communication method and system |
DE4021258A1 (en) * | 1989-07-04 | 1991-01-17 | Hitachi Ltd | Field sensor communication system - uses digital techniques to collect data from sensors and transmit analog current values |
US5469156A (en) * | 1989-07-04 | 1995-11-21 | Hitachi, Ltd. | Field sensor communication system |
US5717385A (en) * | 1990-11-28 | 1998-02-10 | Hitachi, Ltd. | Field bus system and virtual field apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPS6323692B2 (en) | 1988-05-17 |
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