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JPS59201412A - Manufacturing equipment of amorphous semiconductor element - Google Patents

Manufacturing equipment of amorphous semiconductor element

Info

Publication number
JPS59201412A
JPS59201412A JP58074908A JP7490883A JPS59201412A JP S59201412 A JPS59201412 A JP S59201412A JP 58074908 A JP58074908 A JP 58074908A JP 7490883 A JP7490883 A JP 7490883A JP S59201412 A JPS59201412 A JP S59201412A
Authority
JP
Japan
Prior art keywords
substrate
layer
reaction
vacuum chamber
amorphous semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58074908A
Other languages
Japanese (ja)
Inventor
Kazumi Maruyama
和美 丸山
Yoshiyuki Uchida
内田 喜之
Shiro Naruse
成瀬 志郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58074908A priority Critical patent/JPS59201412A/en
Publication of JPS59201412A publication Critical patent/JPS59201412A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To strictly control the temperature of substrate at the forming of the layer for improvement of film quality or for adjustment by providing an independent heating area of substrate between the reaction areas of forming each layer in the process of forming each amorphous semiconductor stratum of a photovoltaic element. CONSTITUTION:Each vacuum chamber 31-33 is separated by a valve 14 and exhausted 16 independently. A tray heated to approx. 150 deg.C in the first vacuum chamber 31 carrying a substrate 1 on which a P layer 3 has been formed is, at first, heated 34 in the substrate heating area of the second vacuum chamber and after adjusted to an optimum temperature, approx. 250 deg.C, the tray is sent to a reaction area and an I layer 4 is formed. The tray is again heated to an optimum temperature, approx. 150 deg.C, and heat adjusted 35 and then sent to the third vacuum chamber 33 and an N layer 5 is formed. In this constitution, the film forming is carried out under strictly controlled conditions and amorphous semicondutor elements can be mass-produced.

Description

【発明の詳細な説明】 本発明は例えばアモルファスシリコン(以下a−Siと
記す)のような非晶質半導体の異なる性質の層を積層し
てなる非晶質半導体素子、例えば太陽電池、光センサな
どの光起電力素子の製造装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to amorphous semiconductor devices such as solar cells, optical sensors, etc., which are formed by stacking layers of amorphous semiconductors with different properties, such as amorphous silicon (hereinafter referred to as a-Si). The present invention relates to a manufacturing apparatus for photovoltaic elements such as.

第1図はそのような太陽電池の一例で、ガラスなどの絶
縁性基板lの上に1旬や5n02などからなる透明電極
2を介してpin型のa−8t層3〜5が形成され、さ
らに上部電極としてMなどの金属電極6が蒸着されてい
る。第2図はこの素子の製造装置の構造を示し、n層膜
3、i層膜4、n層膜5はそれぞれ反応室11 、12
 、13内で形成される。各尽応室11 、12 、1
3は相互間および外部と仕切りパルプ14によって隔離
され、それぞれ排気口15を通じて排気装置16にょシ
真空排気可能であシ、また別にガス導入パルプ17がそ
れぞれ接続されている。
FIG. 1 shows an example of such a solar cell, in which pin-type A-8T layers 3 to 5 are formed on an insulating substrate l such as glass via a transparent electrode 2 made of 100% or 5N02, etc. Furthermore, a metal electrode 6 such as M is deposited as an upper electrode. FIG. 2 shows the structure of the manufacturing apparatus for this device, in which the n-layer film 3, the i-layer film 4, and the n-layer film 5 are arranged in reaction chambers 11 and 12, respectively.
, 13. Each reception room 11, 12, 1
3 are separated from each other and from the outside by a partition pulp 14, each can be evacuated to an exhaust device 16 through an exhaust port 15, and a gas introduction pulp 17 is separately connected to each.

各反応室内には高周波電極18と対向電極19が備えら
れ、高周波電極18fiは基板加熱用ヒータが一体化さ
れている。この装置を用いてpin a −8t % 
3〜5を形成するには、基板1を装着したトレイ肋をモ
ータなどにょシ駆動されるローラ21にょシ第−反応室
11に挿入し、第一反応室11を真空排気後、圧力およ
び流量を調整できるガス導入パルプ17を通じてジボラ
ンガス及びシランガスを導入し高周波電極18と対向す
る電極19との間に高周波電界を印加してプラズマ反応
を起こすことにより基板上にp型a−8t膜(pi摸層
)3を形成する。反応終了後残留ガスを排気し、仕切シ
バルブ14を通して第二反応室12内ヘトレイ加を移送
し、ガス導入バルブ17を通して送られるシランガスを
プラズマ分解し、n層膜3の上にi層膜4をさらに形成
する。
Each reaction chamber is provided with a high frequency electrode 18 and a counter electrode 19, and the high frequency electrode 18fi is integrated with a heater for heating the substrate. Using this device, pin a -8t%
3 to 5, the tray rib with the substrate 1 mounted thereon is inserted into the first reaction chamber 11 by a roller 21 driven by a motor or the like, and after the first reaction chamber 11 is evacuated, the pressure and flow rate are adjusted. Diborane gas and silane gas are introduced through the gas introduction pulp 17 that can adjust the Layer) 3 is formed. After the reaction is completed, the residual gas is exhausted, the silane gas is transferred into the second reaction chamber 12 through the partition valve 14, and the silane gas sent through the gas introduction valve 17 is plasma decomposed to form the i-layer film 4 on the n-layer film 3. Form further.

同様にトレイ加を第二反応室へ移送し、ホスフィンとシ
ランガスのプラズマ分解によpn層膜5を形成してa−
8t層の形成を完了する。
Similarly, the tray was transferred to the second reaction chamber, and a pn layer film 5 was formed by plasma decomposition of phosphine and silane gas.
Complete the formation of the 8t layer.

この製造装置において、各層3〜5の生成温度i9同一
でなく、例えばn層膜3は透明電極2への、;1 150〜250℃で生成するので、n層膜3の形成後−
ちに第二反応室12へ移送する際に基板が短時間内に所
望の温度に達し得ないため、実質的には時間と共に膜形
成温度が変化して良質な膜が得られないという欠点があ
る。殊に量産装置へ応用した場合、一定でかつ短時間内
にi層膜形成のためのプラズマ反応を常時維持した第二
反応室内ヘトレイを移送し、膜形成を実行することは、
基板温度調整が膜形成と同時に実行されなければならな
いので上記欠点は回避できない。
In this manufacturing apparatus, the formation temperature i9 of each layer 3 to 5 is not the same; for example, the n-layer film 3 is formed at a temperature of 150 to 250°C to the transparent electrode 2, so that after the formation of the n-layer film 3 -
Furthermore, since the substrate cannot reach the desired temperature within a short period of time when being transferred to the second reaction chamber 12, the film formation temperature essentially changes over time, making it impossible to obtain a high-quality film. be. Particularly when applied to mass production equipment, it is possible to transfer the tray into the second reaction chamber in which the plasma reaction for forming the i-layer film is constantly maintained within a constant and short period of time to form the film.
The above disadvantages cannot be avoided because substrate temperature adjustment must be performed simultaneously with film formation.

本発明は上述の欠点を除去しょシ厳密に制御された条件
下で膜形成が実行され、かつ量産装置としての機能性に
豊んだ非晶質半導体素子製造装置を提供することを目的
とする。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide an amorphous semiconductor device manufacturing apparatus in which film formation is carried out under strictly controlled conditions and is highly functional as a mass production apparatus. .

この目的は一列に配置された複数の反応領域内を通過す
る基板上に各反応領域においてそれぞれ所定の反応条件
によシ異なる性質の非晶質半導体層を順次生成する装置
が、所定の基板温度の異なる反応領域間に基板を次に通
過すべき反応領域に対する所定の基板温度にするだめの
予熱だけを行32 、33は仕切シバルプ14によシ分
離され、それぞれは独立に真空排気装置16により10
 mTorrより高い真空度に排気できる。基板を装着
したトレイの移送は第2図の装置と同様ローラ211(
よシ行なわれる。プラズマ反応は0.1〜10 Tor
rの圧力下で基板加熱用ヒータを兼ねた高周波電極18
と対向電極19との間で生起される。第二真空室32は
高周波電極18及び19で構成される反応領域と各導電
型層形成温度変更時の温度調整用ヒータ讃、35から成
る基板加熱領域とで構成される。基板加熱領域を設置す
ることによって、例えば第一真空室で100〜150℃
に熱せられた基板1の上にn層膜3の形成を終了したト
レイは直ちに第二真空室32の反応領域には移送されず
、一旦基板加熱領域内に送られヒータ34によって所望
のi層最適形成温度150〜250℃に調整後反応領域
に送られ、1層膜形成が行われる。1層膜形成後他方の
基板加熱領域に送られ温度調整用ヒータ35で再びn層
最適形成温度100〜150℃に調整後第三真空室おに
移送されn層膜の形成が行われる。この予熱領域は第一
真空室31、第三真空室おにあってもよいが本実施例に
い。
The purpose of this is to develop an apparatus that sequentially generates amorphous semiconductor layers with different properties depending on predetermined reaction conditions in each reaction region on a substrate that passes through a plurality of reaction regions arranged in a row, at a predetermined substrate temperature. 32 and 33 are separated by a partition system 14, and each is independently operated by a vacuum evacuation device 16. 10
Can be evacuated to a vacuum level higher than mTorr. The tray loaded with substrates is transferred using rollers 211 (similar to the device shown in Fig. 2).
It is done well. Plasma reaction is 0.1-10 Tor
High frequency electrode 18 that also serves as a heater for heating the substrate under a pressure of r
and the counter electrode 19. The second vacuum chamber 32 is composed of a reaction region composed of high-frequency electrodes 18 and 19, and a substrate heating region composed of a heater plate 35 for adjusting the temperature when changing the temperature for forming each conductivity type layer. By setting up a substrate heating area, e.g. 100-150°C in the first vacuum chamber.
After forming the n-layer film 3 on the heated substrate 1, the tray is not immediately transferred to the reaction area of the second vacuum chamber 32, but is once sent into the substrate heating area and coated with the desired i-layer by the heater 34. After adjusting the optimum formation temperature to 150 to 250° C., it is sent to a reaction area where one-layer film formation is performed. After one layer film is formed, the substrate is sent to the other substrate heating region, and after being adjusted again to the optimum n-layer formation temperature of 100 to 150° C. by the temperature adjustment heater 35, it is transferred to a third vacuum chamber to form an n-layer film. This preheating region may be located in the first vacuum chamber 31 or the third vacuum chamber, but in this embodiment.

第4図は第3図の実施例の変形例を示すものであり、第
3図と異なる点は第3図において反応領域と同一真空室
内に設置した基板加熱領域を独立した真空室41 、4
2内に収納した点にある。この結果第3図の構造におい
て可能性のある反応領域からのプラズマの影響を完全に
回避できる利点がある。しかも両実施例に共通した利点
として、一定のサイクルタイムでかつ短時間に膜形成を
実行すべき量産装置へ応用した場合でも基板加熱過程が
膜形成過程とは別過程でしかも並行して実行できるため
サイクルタイム内に厳密な温度制御が可能となる。
FIG. 4 shows a modification of the embodiment shown in FIG. 3, and the difference from FIG. 3 is that in FIG.
It is located at the point stored within 2. As a result, there is an advantage that the influence of plasma from the reaction region, which is possible in the structure of FIG. 3, can be completely avoided. Furthermore, a common advantage of both embodiments is that even when applied to mass production equipment that requires film formation in a short period of time with a constant cycle time, the substrate heating process can be performed separately from and in parallel with the film formation process. Therefore, strict temperature control is possible within the cycle time.

本発明によれば、光起電力素子の各非晶質半導体層形成
過程において各層形成用の反応領域間にこれとは独立し
て基板加熱領域を設置したことにいう効果がある。
According to the present invention, in the process of forming each amorphous semiconductor layer of a photovoltaic device, a substrate heating region is provided independently between the reaction regions for forming each layer.

本発明は、い首まで説明した三層構造のpin押、素子
の形成だけではなく、あらゆる構造、層数
The present invention is applicable not only to the three-layer pin press and element formation described above, but also to any structure and number of layers.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による装置で製造される素子の一例であ
る太陽電池の断面図、第2図は公知の太陽電池製造装置
の側断面図、第3図は本発明による装置の一実施例の側
断面図、第4図は異なる実施例の側断面図である。 l・・・基板、3・・・p層膜、4・・・i層膜、5・
・・n層膜、16・・・排気装置、17・・・ガス導入
バルブ、18・・・高周波電極、19・・・対向電極、
 31,32.33・・・真空反応室、34 、35・
・・温度調整用ヒータ、41 、42・・・基板加熱室
。 T 1 口 2rn
FIG. 1 is a cross-sectional view of a solar cell that is an example of a device manufactured by the apparatus according to the present invention, FIG. 2 is a side cross-sectional view of a known solar cell manufacturing apparatus, and FIG. 3 is an embodiment of the apparatus according to the present invention. FIG. 4 is a side sectional view of a different embodiment. l...substrate, 3...p layer film, 4...i layer film, 5...
... N-layer film, 16... Exhaust device, 17... Gas introduction valve, 18... High frequency electrode, 19... Counter electrode,
31, 32. 33... Vacuum reaction chamber, 34, 35.
...Temperature adjustment heater, 41, 42...Substrate heating chamber. T 1 mouth 2rn

Claims (1)

【特許請求の範囲】 1)−列に配置された複数の反応領域内に通過する基板
上に、各反応領域においてそれぞれ所定の反応条件によ
る異なる性質の非晶質半導体層を順次生成するものにお
いて、所定の基板温度の異なる反応領域間に基板を次に
通過すべき反応領域に対する所定の基板温度にするため
だけの加熱だけを行う領域が備えられたことを特徴とす
る非晶質半導体素子製造装置。 ソ)特許請求範囲第1項記載の製造装置において、反応
領域と基板加熱領域が同一真空室内に設置されたことを
特徴とする非晶質半導体素子製造装置。 3)特許請求範囲第1項記載の製造装置において、基板
加熱領域が反応領域を有する真空室とは独立した真空室
内に設置されたことを特徴とする非晶質半導体素子製造
装置。
[Claims] 1)-A method for sequentially forming amorphous semiconductor layers of different properties under predetermined reaction conditions in each reaction region on a substrate passing through a plurality of reaction regions arranged in a row. , manufacturing an amorphous semiconductor device, characterized in that a region is provided between reaction regions having different predetermined substrate temperatures, for heating the substrate only to bring the temperature of the substrate to a predetermined temperature for the reaction region through which the substrate passes next. Device. (g) An amorphous semiconductor device manufacturing apparatus according to claim 1, characterized in that a reaction region and a substrate heating region are installed in the same vacuum chamber. 3) An amorphous semiconductor device manufacturing apparatus according to claim 1, characterized in that the substrate heating region is installed in a vacuum chamber independent of the vacuum chamber having the reaction region.
JP58074908A 1983-04-30 1983-04-30 Manufacturing equipment of amorphous semiconductor element Pending JPS59201412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58074908A JPS59201412A (en) 1983-04-30 1983-04-30 Manufacturing equipment of amorphous semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58074908A JPS59201412A (en) 1983-04-30 1983-04-30 Manufacturing equipment of amorphous semiconductor element

Publications (1)

Publication Number Publication Date
JPS59201412A true JPS59201412A (en) 1984-11-15

Family

ID=13560952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58074908A Pending JPS59201412A (en) 1983-04-30 1983-04-30 Manufacturing equipment of amorphous semiconductor element

Country Status (1)

Country Link
JP (1) JPS59201412A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270233A (en) * 1988-04-20 1989-10-27 Fujitsu Ltd Cvd equipment for semiconductor device manufacture

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850733A (en) * 1981-09-21 1983-03-25 Fuji Electric Corp Res & Dev Ltd Mass-production apparatus of thin film for solar cell
JPS5870524A (en) * 1981-09-28 1983-04-27 エナ−ジ−・コンバ−シヨン・デバイセス・インコ−ポレ−テツド Method of depositing body material on base and system therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850733A (en) * 1981-09-21 1983-03-25 Fuji Electric Corp Res & Dev Ltd Mass-production apparatus of thin film for solar cell
JPS5870524A (en) * 1981-09-28 1983-04-27 エナ−ジ−・コンバ−シヨン・デバイセス・インコ−ポレ−テツド Method of depositing body material on base and system therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270233A (en) * 1988-04-20 1989-10-27 Fujitsu Ltd Cvd equipment for semiconductor device manufacture

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