JPS59198737A - Leadless multiple chipcarrier - Google Patents
Leadless multiple chipcarrierInfo
- Publication number
- JPS59198737A JPS59198737A JP7329383A JP7329383A JPS59198737A JP S59198737 A JPS59198737 A JP S59198737A JP 7329383 A JP7329383 A JP 7329383A JP 7329383 A JP7329383 A JP 7329383A JP S59198737 A JPS59198737 A JP S59198737A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- adhesive
- glass plate
- sapphire glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000011521 glass Substances 0.000 claims abstract description 16
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 13
- 239000010980 sapphire Substances 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 abstract description 14
- 230000001070 adhesive effect Effects 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000007711 solidification Methods 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 8
- 239000000969 carrier Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 frame Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
発明の属する技術分野
本発明は超小型チップキャリアに関し、特に複数個のＩ
Ｃチップからの多数の端子を他の基板上に接続すること
のできる格子上配列の端子パッドを有し、しかも複数個
のＩＣチップで発生する熱を効率よく外部に伝えること
のできるリードレスマルチチップキャリアに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microchip carrier, and more particularly to a microchip carrier having multiple I/O chips.
A leadless multi-chip has terminal pads arranged in a lattice pattern that can connect a large number of terminals from a C chip to other substrates, and can efficiently transfer heat generated by multiple IC chips to the outside. Regarding chip carriers.
従来技術
従来、この種のり一ドレスチップキャリアは、第１図に
示すように、サブストレート１のキャビティ内にチップ
２がフェースアップ状態で１個接着され、チップ２の端
子５がワイヤボンディングによシサプストレート１上の
ポンディングパッド６に接続され、カバー３が接着され
ている。Prior Art Conventionally, as shown in FIG. 1, this type of glue-less chip carrier has one chip 2 bonded face-up inside a cavity of a substrate 1, and the terminals 5 of the chip 2 bonded to each other by wire bonding. It is connected to a bonding pad 6 on the sysap straight 1, and a cover 3 is adhered thereto.
このチップキャリアにおけるＩＣチップ２の端子５はそ
れぞれはポンディングパッド６からサブストレート１内
の配線を介してサブストレート１の側面に設けられた外
部端子４のそれぞれに接続されている。The terminals 5 of the IC chip 2 in this chip carrier are each connected from a bonding pad 6 to each external terminal 4 provided on the side surface of the substrate 1 via wiring within the substrate 1.
ＩＣ同志の接続は前記リードレスチップキャリアを複数
個基板に並べ基板上で配線することにより行なわれる。Connection between ICs is performed by arranging a plurality of leadless chip carriers on a board and wiring them on the board.
このような構造″の場合以下に述べるような２つの欠点
がある。Such a structure has two drawbacks as described below.
すなわち、サブストレート１の各辺から外部端子４を取
υ出すためＩＣチップ２の端子数が増加するにともない
各辺の外部端子４の数も増加する。That is, since the external terminals 4 are taken out from each side of the substrate 1, as the number of terminals of the IC chip 2 increases, the number of external terminals 4 on each side also increases.
従って、１辺の長さが増大しサブストレートｌの形状が
大きくなる。このため多端子リードレスチップキャリア
を複数個基板に並べるとますます形状が大きくなって小
型化がむずかしくなる。これが第１の欠点である。Therefore, the length of one side increases and the shape of the substrate l becomes larger. For this reason, if a plurality of multi-terminal leadless chip carriers are arranged on a board, the shape becomes larger and smaller, making it difficult to downsize. This is the first drawback.
次に、ＩＣチップ２はサブストレート１に接続されてい
るため、ＩＣチップ２の発生する熱の大部分はサブスト
レート１の底を伝わりチップキャリアの接続される基板
側に′にげる構造である。このためＩＣの集積度が上っ
て発熱量が大きくなると、高集積度チップキャリアを複
数個並べた基板では全体の発熱量が上り、十分にチップ
を冷却できない。Next, since the IC chip 2 is connected to the substrate 1, most of the heat generated by the IC chip 2 is transmitted through the bottom of the substrate 1 and radiated to the substrate side to which the chip carrier is connected. For this reason, as the degree of integration of ICs increases and the amount of heat generated increases, the overall amount of heat generated increases in a board on which a plurality of highly integrated chip carriers are arranged, making it impossible to cool the chips sufficiently.
これが第２の欠点である。This is the second drawback.
発明の目的
本発明の目的はよシ多くの端子数をもち、かつ発熱量の
大きい複数個の高阪積化ＩＣチップを収容できる構造と
し放熱効率が良好で 多端子が可能でかつ組立性を良好
にするようにした超小型リードレスマルチチップチップ
キャリア全提供することにある。Purpose of the Invention The purpose of the present invention is to provide a structure capable of accommodating a plurality of Kosaka integrated IC chips having a large number of terminals and generating a large amount of heat, which has good heat dissipation efficiency, allows for multiple terminals, and is easy to assemble. Our goal is to provide a complete ultra-compact leadless multi-chip chip carrier with excellent features.
発明の構成
本発明によるリードレスマルチチップチップキャリアは
、
表面に塔載された複数個のＩＣチップのリードをボンデ
ィング接続するだめのポンディングパッドと、
裏面に形成された格子状配列の端子パッドと、ポンディ
ングパッド間またはポンディングパッドの端子パッド曲
を接続する接続配線およびヴアホール配線とを備えたサ
ブストレートと、前記サブストレートの周辺側面に接着
された枠と、
前記枠のサブストレートと対向する側に接着されたサフ
ァイヤガラス板と、
ＡｉＪ記サブすトレート上においてチップ本体を前記サ
ファイヤガラス板に接着されかつリードを前記サブスト
レート上のポンディングパッドに接続された複数個のＩ
Ｃチップとを含む。Structure of the Invention The leadless multi-chip chip carrier according to the present invention includes: bonding pads for bonding the leads of a plurality of IC chips mounted on the front surface; terminal pads arranged in a grid pattern on the back surface; , a substrate having connection wiring and via hole wiring connecting between bonding pads or between terminal pad bends of the bonding pads; a frame adhered to a peripheral side surface of the substrate; and a frame facing the substrate of the frame. a sapphire glass plate bonded to one side of the substrate;
C chip.
発明の実施例 次に本発明について図面を参照して詳細に説明する。Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.
第２図全参照すると、本発明の一実施例は、 ＩＣチッ
プ８が横に２個並んでおｐ１セラミックサフ−ストレー
ト７、ＩＣチップ８、枠９、す７アイヤガラス１０、端
子パッド１１、ＩＣリード１２、ボンティングパッド１
３、チップ端子１４、枠抜着剤１５、チップ接着剤１６
、ヴイアホール配線１７、ふた接着剤１８．接続配線１
９で構成されている。Referring to FIG. 2, in one embodiment of the present invention, two IC chips 8 are arranged side by side. Lead 12, bonding pad 1
3, chip terminal 14, frame removal agent 15, chip adhesive 16
, via hole wiring 17, lid adhesive 18. Connection wiring 1
It consists of 9.
前記セラミックサブストレート７は表面にＩＣ端子数と
等しい複数個のポンディングパッド１３が形成されてお
り、このそれぞれのポンディングパッド１３に各ＩＣチ
ップ８のＩＣリード１２がポンディングされている。ま
た、ポンディングパッド１３のそれぞれにはセラミック
サブストレート７の表面に形成された複数個の接続配線
１８がつながっており、接続配線１８のそれぞれはセラ
ミックサブストレートフ内に形成されたグイアホール配
線１７のそれ−それを経由してセラミックサブストレー
ト７の裏面に形成された端子パッド１１のそれぞれに接
続されている。ここでは複数個のＩＣチップの端子を直
接セラミックサブストレート７の裏面に形成された端子
パッド１１に接続される場合を示したが、ＩＣチップ同
志の接続はセラミックサブストレート７に配線層を設け
−ることにより可能となる。A plurality of bonding pads 13 equal to the number of IC terminals are formed on the surface of the ceramic substrate 7, and the IC leads 12 of each IC chip 8 are bonded to each of the bonding pads 13. Further, each of the bonding pads 13 is connected to a plurality of connection wirings 18 formed on the surface of the ceramic substrate 7, and each of the connection wirings 18 is connected to a guia hole wiring 17 formed within the ceramic substrate 7. It is connected via it to each of the terminal pads 11 formed on the back side of the ceramic substrate 7. Here, a case is shown in which the terminals of a plurality of IC chips are directly connected to the terminal pads 11 formed on the back surface of the ceramic substrate 7, but the connection between the IC chips is achieved by providing a wiring layer on the ceramic substrate 7. This becomes possible by
第３図および第４図は上記セラミックサブストレート７
の表面の配線および裏面の端子パッドの配置を示す図で
ある。Figures 3 and 4 show the above ceramic substrate 7.
FIG. 3 is a diagram showing the arrangement of wiring on the front surface and terminal pads on the back surface.
第３図を参照すると、ポンディングパッド１３のそれぞ
れは接続配線１９を介してグイアホール配線１７につな
がり、さらにヴイアホール配線１７のそれぞれはサブス
トレート７内を貫通して裏面の端子パッド１１のそれぞ
れにつながれている。Referring to FIG. 3, each of the bonding pads 13 is connected to a via hole wiring 17 via a connection wiring 19, and each of the via hole wirings 17 is further connected to each of the terminal pads 11 on the back side by passing through the substrate 7. ing.
以上の説明から明らかなようにＩＣチップ８の各端子は
サブストレート７の裏面の格子状に配列された端子パッ
ド１１に外部接続のために取り出されている。従って、
多数の端子を高密度に取）出すことが可、能となってい
る。この高い端子密度を利用して、多端子ＩＣチップを
複数個チップ（ヤリアに搭載することによυ高密度で超
小型の実装が可能となる。As is clear from the above description, each terminal of the IC chip 8 is taken out to the terminal pads 11 arranged in a grid on the back surface of the substrate 7 for external connection. Therefore,
It is possible to take out a large number of terminals at a high density. Utilizing this high terminal density, by mounting multiple multi-terminal IC chips on a chip (Yaria), high-density and ultra-small packaging becomes possible.
第５図は本実施例に用いたＩＣチップのリード形状を示
す図である。ＩＣチップ８のリード１２は、従来のよう
にＩＣチップをサブストレート上に固定した後に、例え
ば、金ワイヤを用いてＩＣチップのそれぞれの端子１４
およびサブストレートの端子パッドのそれぞれを順次ボ
ンディング接続していく方法と異なり、予めＩＣチップ
８のそれぞれの端子１４に接続されている。リード１２
は写真の３５ｍｍフィルムと同じようなスプロケットホ
ール合有するフィルム上に銅箔をはりつけ、これをフォ
トリソグラフィーにより蕗光、現像。FIG. 5 is a diagram showing the lead shape of the IC chip used in this example. The leads 12 of the IC chip 8 are connected to respective terminals 14 of the IC chip using, for example, gold wires after the IC chip is conventionally fixed on a substrate.
Unlike the method of sequentially bonding and connecting each of the terminal pads of the substrate and the substrate, the terminal pads are connected to the respective terminals 14 of the IC chip 8 in advance. lead 12
Copper foil is pasted onto a film that has sprocket holes similar to 35mm photographic film, and this is exposed and developed using photolithography.
およびエツチングして得られる。このようにして−１＃
にフィルム上に形成されたり一ド１２のそれぞれは金メ
ッキを処された後、周知のＴＡＢ （ＴａｐｅＡｕｔｏ
ｍａｔｅｄ Ｂｏｎｄｉｎｇ ）技術によりＩＣチップ
８の端子１４のそれぞれに一括ボンディング接続され、
しかる後リード１２のそれぞれを支えていたフィルムを
切りはなして第５図に示すような’ＰＡＢリードつきの
ＩＣチップが得られる。and etching. In this way -1#
Each of the tapes 12 formed on a film is then gold-plated and then plated with the well-known TAB (Tape Auto).
They are collectively bonded to each of the terminals 14 of the IC chip 8 by mated bonding) technology,
Thereafter, the film supporting each of the leads 12 is cut off to obtain an IC chip with 'PAB leads as shown in FIG.
第６図は本実施例のＩＣチップ８、サブストレート７、
枠９、サファイヤガラス板１０の組立構造の関係を示す
図である。FIG. 6 shows the IC chip 8, substrate 7, and
3 is a diagram showing the relationship between the assembly structure of the frame 9 and the sapphire glass plate 10. FIG.
第６図を参照すると、本発明のＩＣチップが４個実装さ
れた場合の実施例のり一ドレスマルチチッグチップキャ
リアについて説明する。ＩＣチップが４個以外の複数個
実装された場合も同様である。壕ず第１にサブストレー
ト７上にＩＣチップ８のそれぞれがフェースダウンの状
態に置かれ、ＩＣリード１２のそれぞれとサブストレー
ト上のポンディングパッド１３のそれぞれの位置が合わ
された後に一括ボンディングされる。このボンティング
された状態は第２図を参照できる。枠９とす７アイヤガ
ラス板１０とが予め接着剤１８により接着されてあり、
これがサブストレー ドアにはめ込まれる。す７アイヤ
ガラス板１ｏの内側の面にはチップダイボンディング用
の接着剤１６が塗られておシ、透明なす７アイヤガラス
板１ｏの±から見ながら枠９がサブストレート７にはめ
込れていき、接着剤１６が各ＩＣチップ８の裏面にすべ
て接触した１士仮固定される。この状態で温度が加えら
れ接着剤１６が固化され、各ＩＣチップ８のダイボンデ
ィングが行なわれる。次にサブストレート７０周辺０１
１面と枠９の内面との間に接着 ４剤１５が注入され
、温度が加えられて固化され、リードレスマルチチップ
チップキャリアの組立が完了する。Referring to FIG. 6, a glue-less multi-chip carrier according to an embodiment of the present invention will be described in which four IC chips of the present invention are mounted. The same applies when a plurality of IC chips other than four are mounted. First, each of the IC chips 8 is placed face down on the substrate 7, and after the positions of each of the IC leads 12 and each of the bonding pads 13 on the substrate are aligned, they are bonded all at once. . This bonded state can be seen in FIG. The frame 9 and the glass plate 10 are bonded in advance with an adhesive 18,
This will fit into the substray door. An adhesive 16 for chip die bonding is applied to the inner surface of the transparent glass plate 1o, and the frame 9 is fitted into the substrate 7 while looking from the ± side of the transparent glass plate 1o. The adhesive 16 is temporarily fixed once it is in contact with the back surface of each IC chip 8. In this state, temperature is applied to solidify the adhesive 16, and die bonding of each IC chip 8 is performed. Next, the substrate 70 area 01
An adhesive 15 is injected between the first surface and the inner surface of the frame 9, and is hardened by applying temperature, completing the assembly of the leadless multichip carrier.
本発明のチップキャリアに熱伝導特性の橙めて良好なサ
ファイヤガラス板を使用することにより効率的な放熱を
可能とするだけでなく、内部の各ＩＣチップ実装状態を
目視できるため組立が容易であるという特徴をもってい
る。By using a sapphire glass plate with excellent thermal conductivity in the chip carrier of the present invention, it not only enables efficient heat dissipation, but also facilitates assembly because the mounting status of each IC chip inside can be visually observed. It has the characteristic of being
発明の効果
本発明には、リードレスチップキャリアにおいてサブス
トレートの裏面に外部接続端子パッドが格子状に配列さ
れ、かつ複数個のＩＣチップ本代がサブストレートの表
面に対向して接着された熱伝導特性の極めて良好なサフ
ァイヤガラス板に接着させたリードレスマルチチップチ
ップキャリアの構造とすることによｐ１組立が容易で多
数の端子をもち放熱特性の良好な超小型チップキャリア
が実現できるという効果がある。Effects of the Invention The present invention has a leadless chip carrier in which external connection terminal pads are arranged in a lattice pattern on the back surface of a substrate, and a plurality of IC chips are bonded facing each other to the surface of the substrate. The structure of a leadless multi-chip carrier bonded to a sapphire glass plate with extremely good conductivity makes it possible to easily assemble the P1 and realize an ultra-small chip carrier with numerous terminals and good heat dissipation properties. There is.
第１図は従来のリードレスチップキャリアを示す図、第
２図は本発明の一実施例を示す図、第３′図は４個のＩ
Ｃチップを塔載した場合の本発明のチップキャリアのサ
ブストレート表面を示す図、第４図は第３図と同様に本
発明のチップキャリアのサブストレート裏面を示す図、
第５図は本発明で使用するＩＣチップのリード接続を示
す図および第６図は本発明のチップキャリアのサブスト
レート、枠、サファイヤガラス板の組立関係を示す図で
ある。
第２図から第６図において、７・・・・・・セラミック
サブストレート、８・・・・・・ＩＣチップ、９・・・
・・・枠、ｌＯ・・・・・・サファイヤガラス板、１１
・・・・・・端子パッド、１２・・・・・・ＩＣリード
、１３・・・・・・ポンディングパッド、１４・・・・
・・ＩＣチップ端子、１５・・・・・・枠抜着剤、１６
・・・・・・ＩＣチップ接着剤、１７・・・・・・ヴイ
アホール配線、１８・・・・・・サファイヤガラス板接
着剤、１９・・・・・・接線配線。
第１図
寮２閲
第３図
第４区
第５凶FIG. 1 is a diagram showing a conventional leadless chip carrier, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3' is a diagram showing a conventional leadless chip carrier.
FIG. 4 is a diagram showing the substrate surface of the chip carrier of the present invention when a C chip is mounted thereon; FIG. 4 is a diagram showing the back surface of the substrate of the chip carrier of the present invention similarly to FIG. 3;
FIG. 5 is a diagram showing the lead connections of the IC chip used in the present invention, and FIG. 6 is a diagram showing the assembly relationship of the substrate, frame, and sapphire glass plate of the chip carrier of the present invention. In FIGS. 2 to 6, 7...ceramic substrate, 8...IC chip, 9...
...Frame, lO...Sapphire glass plate, 11
...Terminal pad, 12...IC lead, 13...Ponding pad, 14...
...IC chip terminal, 15... Frame removal agent, 16
...IC chip adhesive, 17...Via hole wiring, 18...Sapphire glass plate adhesive, 19...Tangential wiring. Figure 1: Dormitory 2: Figure 3: Ward 5, Ward 4
Claims (1)
ング接続するための複数個のポンディングパッドと、 裏面に形成され他の基板に接続するために格子状に配列
された複数個の端子パッドと、前記ポンディングパッド
間同志および前記ポンディングパッドと前記端子パッド
との間の少なくとも１方を接続する接続配線およびヴア
アホール配線とを備えたサブストレートと、 前記サブストレートの周辺に接着された枠と、前記枠の
前記サブストレートと対向する側に接着されたサファイ
アガラス板と、 前記サブストレートの表面において前記ポンディングパ
ッドのそれぞれにボンディングされた複数個のリードを
有しかつチップ本体が前記サファイアガラス板の内面に
接着された複数個のＩＣチップとを含むことを特徴とす
るリードレスマルチチップチップキャリア。[Claims] A plurality of bonding pads mounted on the front surface for bonding the leads of the plurality of IC chips, and a plurality of bonding pads formed on the back surface and arranged in a grid for connection to other substrates. A substrate including a plurality of terminal pads, a connection wiring and a via hole wiring that connect at least one of the bonding pads and between the bonding pad and the terminal pad; and a periphery of the substrate. a sapphire glass plate bonded to a side of the frame opposite to the substrate; a plurality of leads bonded to each of the bonding pads on the surface of the substrate; A leadless multi-chip chip carrier, wherein the chip body includes a plurality of IC chips bonded to the inner surface of the sapphire glass plate.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7329383A JPS59198737A (en) | 1983-04-26 | 1983-04-26 | Leadless multiple chipcarrier |
| EP84103423A EP0120500B1 (en) | 1983-03-29 | 1984-03-28 | High density lsi package for logic circuits |
| CA000450758A CA1229155A (en) | 1983-03-29 | 1984-03-28 | High density lsi package for logic circuits |
| DE8484103423T DE3479463D1 (en) | 1983-03-29 | 1984-03-28 | High density lsi package for logic circuits |
| US06/758,951 US4652970A (en) | 1983-03-29 | 1985-07-25 | High density LSI package for logic circuits |
| US06/896,348 US4744007A (en) | 1983-03-29 | 1986-08-14 | High density LSI package for logic circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7329383A JPS59198737A (en) | 1983-04-26 | 1983-04-26 | Leadless multiple chipcarrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59198737A true JPS59198737A (en) | 1984-11-10 |
Family
ID=13513960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7329383A Pending JPS59198737A (en) | 1983-03-29 | 1983-04-26 | Leadless multiple chipcarrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59198737A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268049A (en) * | 1985-05-23 | 1986-11-27 | Nec Corp | Mounting structure of package for lsi |
| JPH01253942A (en) * | 1988-04-04 | 1989-10-11 | Hitachi Ltd | Semiconductor package and computer using it |
-
1983
- 1983-04-26 JP JP7329383A patent/JPS59198737A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268049A (en) * | 1985-05-23 | 1986-11-27 | Nec Corp | Mounting structure of package for lsi |
| JPH01253942A (en) * | 1988-04-04 | 1989-10-11 | Hitachi Ltd | Semiconductor package and computer using it |
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