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JPS59195798U - multilayer printed wiring board - Google Patents

multilayer printed wiring board

Info

Publication number
JPS59195798U
JPS59195798U JP1121984U JP1121984U JPS59195798U JP S59195798 U JPS59195798 U JP S59195798U JP 1121984 U JP1121984 U JP 1121984U JP 1121984 U JP1121984 U JP 1121984U JP S59195798 U JPS59195798 U JP S59195798U
Authority
JP
Japan
Prior art keywords
wiring layer
multilayer printed
printed wiring
wiring board
grounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1121984U
Other languages
Japanese (ja)
Other versions
JPH0129837Y2 (en
Inventor
ジェームズ・アーサー・ブリュウアー
ジョン・ケネディ・ラングッド
ハーヴィ・ロセン・マーカム
Original Assignee
インターナシヨナル　ビジネス　マシーンズ　コーポレーシヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by インターナシヨナル　ビジネス　マシーンズ　コーポレーシヨン filed Critical インターナシヨナル　ビジネス　マシーンズ　コーポレーシヨン
Publication of JPS59195798U publication Critical patent/JPS59195798U/en
Application granted granted Critical
Publication of JPH0129837Y2 publication Critical patent/JPH0129837Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例を示す斜視図、第２図〜第
７図は第１図実施例の各絶縁層１〜６のパターンをそれ
ぞれ示す平面図である。FIG. 1 is a perspective view showing an embodiment of this invention, and FIGS. 2 to 7 are plan views showing patterns of the insulating layers 1 to 6 of the embodiment in FIG. 1, respectively.

Claims (1)

【実用新案登録請求の範囲】 多層プリント配線板本体の最上面および最下面にそれぞ
れ形成した第１の信号用配線層および第２の信号用配線
層と、 これら第１の信号用配線層および第２の信号用配線層に
それぞれ絶縁層を介して隣接配置した第１の接地用配線
層および第２の接地用配線層と、これら第１の接地用配
線層および第２の接地用□　配線層の間に配置した少な
くとも１つの第３の信号用配線層とを有してなる多層プ
リント配線板。[Claims for Utility Model Registration] A first signal wiring layer and a second signal wiring layer formed on the uppermost surface and the lowermost surface of the multilayer printed wiring board body, respectively; A first grounding wiring layer and a second grounding wiring layer are arranged adjacent to the second signal wiring layer with an insulating layer interposed therebetween, and these first grounding wiring layer and second grounding wiring layer and at least one third signal wiring layer disposed between the multilayer printed wiring boards.
JP1121984U 1983-06-10 1984-01-31 multilayer printed wiring board Granted JPS59195798U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47337783A 1983-06-10 1983-06-10
US473377 1983-06-10

Publications (2)

Publication Number Publication Date
JPS59195798U true JPS59195798U (en) 1984-12-26
JPH0129837Y2 JPH0129837Y2 (en) 1989-09-11

Family

ID=23879282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1121984U Granted JPS59195798U (en) 1983-06-10 1984-01-31 multilayer printed wiring board

Country Status (4)

Country Link
JP (1) JPS59195798U (en)
BR (1) BR8401005A (en)
DE (1) DE3408046A1 (en)
GB (1) GB8405864D0 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030190A (en) * 1976-03-30 1977-06-21 International Business Machines Corporation Method for forming a multilayer printed circuit board

Also Published As

Publication number Publication date
GB8405864D0 (en) 1984-04-11
BR8401005A (en) 1984-10-16
JPH0129837Y2 (en) 1989-09-11
DE3408046A1 (en) 1984-12-13

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