JPS5919379B2 - data generation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generates data that can be easily processed by the execution unit in a device that processes an instruction by dividing it into a plurality of processing units including an operand extraction unit and an execution unit. The present invention relates to a data generation device.

Conventionally, in pipeline-type instruction execution devices that divide each instruction execution process into multiple processing units, many high-level languages such as PL/1 and FORTRAN are translated into several machine language instructions and executed. There is. For example, FIG. 1 shows an example of an assignment statement written in PL/1 and an example of this assignment statement translated into a machine language instruction. In Figure 1, P
The assignment statement written in L/1 uses s, which is decimal fixed-point data, as the sending data, and two receiving data, indicated by RA, which is binary fixed-point data, and RB, which is decimal fixed-point data. Instruct to send to.

At the same time, when transferring data to the receiving side, an instruction is given to perform data conversion of the sending side data according to the type of the receiving side data. In the example in Figure 1, which translated human language into machine language instructions, first the s of the move command (MOVES, WA,)
The content of the sending data indicated by is transferred to the work memory (or register) indicated by WA. At this time,
WA without any special conversion to the content of the data on the sending side.
Therefore, the type of data transferred to this work memory (register) is the same decimal number as the type of data indicated by s. Next, the data conversion instruction (DTB
WA, WR, ) converts the decimal data in the work memory (register) indicated by WA into a binary number and transfers it to the receiving work memory (register) indicated by WR. Next, in the move command (MOVEWR, RA,), WR
The data converted into binary numbers in the work memory (register) indicated by RA is stored in the location in the main memory indicated by RA. Finally, the transfer command (MOVEWA, RB,)
Now, 10 of the work memory (registers) specified by WA
The base number data is stored as sending data in the location in the main memory indicated by RB. At this time, since the RB data is specified to be a decimal number in the program written in a high-level language, the sending data is not converted. The above four commands perform a process of transferring one data to two receiving data as expressed in a high-level language. FIG. 2 shows a block diagram of a conventional data processing device having a plurality of processing units designed to execute the above machine language instructions.

The device shown in FIG. 2 includes a main memory 1 for storing machine language instruction sequences and data, and an operand address for retrieving instructions from the main memory 1 and at the same time indicating the data position in the main memory 1. an instruction retrieval unit 2 that performs expansion;
An execution unit 3 that processes data retrieved from the main memory 1, etc., and a general-purpose register used as a base register or index register used when performing address expansion, or as a processing result storage register that can be specified with machine language instructions. Group 4. A sequence of machine language instructions to be processed from the main memory 1 is taken out into an instruction buffer 5, and then stored one instruction at a time into an instruction register 6 from the instruction buffer 5. A conventional decoder (not shown) for the stored instruction detects the type of operands of the instruction. As a result, when it is detected that the operand is related to data in the main memory device 1, the address of this operand is calculated using the address calculator 7,
It is stored in the address register 8. Next, the data in the main memory 1 specified by the address register 8 is transferred to the execution unit 3.
- Stored in operand register 9 inside. When the instruction in the instruction register 6 becomes ready to be processed by the execution unit 3, the instruction fetching unit 2 sends the instruction code in the instruction register 6 to the execution instruction code register 10 of the execution unit 3. As a result, in the execution unit 3, according to the instruction code, the operand register 9
Arithmetic operations, comparisons, data conversions, and storage of these processing results are performed using the general-purpose register group 4. When this device is used to execute the machine language instructions shown in FIG. 1, the following advantages arise because the instruction fetch section 2 and execution section 3 operate independently. In other words, the speed at which instructions are processed becomes faster than when instructions are processed by only one processing unit.
On the other hand, problems with the data processing device shown in the conventional example include the following. In other words, each machine language instruction has a low function and can only describe simple operations.
When a somewhat complex high-level language sentence as shown in FIG. 1 is translated into machine language instructions, redundant operands are required and operations associated with the operands are required. For example, WA, which is the operand of the machine language instruction in Figure 1,
and WR indicates data that is not indicated in the assignment statement "RA, RB=S;" of PL/1, and is not an operand that is essentially required to execute the assignment statement. . The two operands can be omitted by defining an appropriate machine language instruction suitable for the assignment statement. Compared to the machine language instructions defined in this way, the machine language instructions shown in FIG. 1 require a larger storage capacity for the instructions required to execute the assignment statement. At the same time, instruction fetch time and operand fetch time increase. Furthermore, a problem with the conventional example shown in FIGS. 1 and 2 is that because the machine language instructions have low functionality, it is not possible to sufficiently prefetch the instructions until they reach the execution unit 3. . In other words, in a processing device that performs prefetching, by increasing the number of processing units that perform prefetching operations independently of each other prior to the execution unit 3, and making the operating time for each processing unit equal for processing instructions, the entire device can be improved. The processing speed can be improved. However, if the functionality of machine language instructions is low, the number of processing units in the processing device shown in FIG.
Reducing the number from one to three makes it difficult to improve the instruction processing speed due to the increased time required to transfer information between each processing unit, and it is necessary to divide the machine language instructions in Figure 1 to pre-process them. becomes difficult. Burr is a data processing device equipped with highly functional machine language instructions suitable for high-level languages.
An example is the Bl7OO calculator manufactured by Oughs.

In this device, instructions are executed by one processing unit. FIG. 3 shows an example in which the high-level language that specifies sending one sending data to two receiving data shown in FIG. 1 is translated into highly functional machine language instructions. The machine language instruction in Figure 3 consists of an instruction cove section, a receiver data number indicator section that indicates the number of receiver data in an assignment statement, an operand section that indicates the sender data, and two napelands that indicate the receiver data. It consists of a department. The instruction code part in Figure 3 is M
It is indicated by MVN and indicates the numerical transfer of sender data to multiple receiver data. The value of the number of data on the receiving side is 2 because it is equal to the number of data on the receiving side. The operand part of the sending data is an operand indicating S data, and the operand part of the receiving data is an operand indicating RA and RB. This machine language instruction can eliminate the need for redundant operands compared to the machine language instruction shown in FIG. That is, the operands indicated by WA and WR in FIG. 1 become unnecessary. At the same time, it is possible to reduce the storage capacity occupied by the machine's erroneous instructions into which high-level language sentences are translated, and further improve the processing speed. however,
Machine language instructions are executed by one data processing device, so if the pipeline type data processing device shown in FIG. 2 is able to execute machine language instructions with high functionality as shown in FIG. The processing speed is comparatively slow. The purpose of this invention is to solve the above-mentioned drawbacks by processing highly functional machine language instructions in a plurality of processing units that operate independently of each other according to the instruction processing process, and by generating operands as prefetch processing that is performed prior to the execution unit. It is an object of the present invention to provide a data generation device that can improve the instruction processing speed by evenly distributing the amount of processing in each processing unit.

That is, the present invention is a data generation device in a data processing device that divides an instruction into a plurality of processing units when processing an instruction, and provides information on an operand to be repeatedly operated and the number of times this operand is repeatedly operated. an instruction decoder that determines whether the instruction is a machine language instruction, including an operation count instruction section that specifies the operation count instruction; a temporary storage device that temporarily stores data specified by the operand retrieved from the storage device; a data count register for monitoring the number of times data is generated as specified by the operand indicated by the part; a data converter for converting the data in the temporary storage device into data of different nature; and the data specified by the operand in the instruction decoder. a control device that performs a control operation to cause the data converter to convert and generate the data in the temporary storage device as many times as allowed by the data number register when it is decoded to be an instruction that has been generated multiple times; It consists of

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 4 shows an example of a machine language instruction translated from the high-level language shown in FIG.

MMOVE is specified in 8 bits of the instruction code, indicating a transfer command in which there is one data on the sending side and the number of data on the receiving side is equal to the number indicated by the receiving side data number indicating section (operation number indicating section). Since the receiving side data is two pieces of data indicated by RA and RB, the value of the receiving side data number indicator is 2.
It is. The attributes of the sending data indicated by S and the receiving data indicated by RA and RB are both fixed point and real numbers, so a machine language instruction is constructed with the operand type shown in Figure 5 below, and each The operand of
They are indicated in the figure as 0S8, 0SRA and 0SRB.

FIG. 5 shows an example of an arithmetic data operand (0S) whose data attribute is a fixed point, and each field in the operand is shown below.

Two bits, bit 0 and bit 1, of the operand indicate the type of this operand. The types include the literal type (00), which has a constant in the operand that is used as data to be processed, and the direct type (00), in which the operand directly indicates the location where data with basic data attributes exists.
01) and indirect type (10). The indirect type is used to indicate complex data such as array length data, variable length data, or edited data.The position of the data descriptor is specified by the operand, and the position of the data to be processed is specified in this data descriptor. Used when directed by the scripter. Here, we will explain the direct type operand. Three bits from bit 2 to bit 4 of the operand indicate the type of data, such as arithmetic data, string data, and label data. In FIG. 5, a case will be explained in which the 3-bit pattern is arithmetic data indicated by 010. Three bits from bit 5 to bit 7 of the operand each indicate the type of arithmetic data. Bit 5 is a mode bit indicating whether the data indicated by this operand is a real number or an imaginary number; when the 1st value is O, it is a real number, and when it is 1, it is an imaginary number. Bit 6 is a base bit indicating whether the data indicated by this operand is a binary number or a decimal number; when this value is O, it is a binary number, and when it is 1, it is a decimal number. Bit 7 is a scale bit that indicates whether the data indicated by this operand is fixed point or floating point; when this value is O, it is fixed point, and when it is 1, it is floating point. FIG. 5 shows a case where this scale bit is O, that is, a case where it is fixed point data. Bits 8 to 23 of the operand indicate the precision of this fixed-point data, 8 bits from bit 8 to 15 indicate the total number of digits of this data, and 8 bits from bit 16 to bit 23 indicate the precision of this fixed-point data. indicates the number of digits to the right of the decimal point for this data. 2 from bit 28 to bit 47 of the operand
The 0 bit is address information indicating the location of this fixed-point arithmetic data in the main memory. This information consists of an index register, each pointer indicating a base register, and a displacement indicating an address within a main memory which is divided into several blocks. FIG. 6 is a block diagram of one embodiment of the present invention, and the entire device shown in FIG. 6 includes a main memory 15 for storing machine language instruction strings translated from high-level languages, data, etc., and an instruction for fetching instructions. An extraction unit 16, a data generation unit 17 that extracts data and generates data specified by operands, and an execution unit 18.
It is composed of.

For transmitting information and data from the instruction fetching section 16 to the data generating section 17 and from the data generating section 17 to the executing section 18, a FIFO having a function of outputting the earliest input is used. (First in Fi
rstOut) buffer (indicated by the dashed line M in FIG. 6) is used. Each FIFO buffer is composed of 4 to 8 words, and these FIFO buffers allow up to several instructions to be processed independently in each processing unit. The instruction retrieval unit 16 reads out the sequence of instructions to be executed from the main storage device 15 to the instruction buffer 20.

The instruction located at the head of the instruction buffer 20 is stored in the instruction register 21. If the operand land in this instruction is a literal type (that is, a constant is stored in the operand of the instruction), the constant in the operand is directly transferred to the data generation unit 17 via the literal data buffer 41.
is output to. If the operand is a direct or indirect type, address expansion is performed using the address information in the operand to find the location in the main memory 15 pointed to by the operand. This address expansion is performed by using the address calculator 23 to calculate the contents of the base register and index register in the address modification register group 22 indicated by each pointer of the address information and the displacement of the address information.
This is done by calculating. If the operand is a direct type, the address expansion result obtained here indicates the data to be processed, so the IF address buffer 4
0 to the data generation unit 17. When the operand is an indirect type, the data descriptor specified according to the address expansion result is read from the main memory 15 and the address information in this descriptor that directly specifies the data to be processed is the same as in the direct type. , are output to the data generation section 17 via the IF address buffer 40.
Data description information such as data type mode, base, scale, and data length in the operand in the instruction register 21 is paired with the address signal and constant data of the corresponding data via the IF type buffer 42 and sent to the data generation unit 17. Output. The instruction code in the instruction register 21 and information attached to the instruction are output to the data generation section 17 via the IF instruction buffer 43. In the data generation unit 17, when the data generation unit 17 becomes ready for data processing of a new instruction, the oldest instruction and instruction attached information stored in the IF instruction buffer 43 are read out to the instruction code register. The operand address register 24 stores the oldest address in the IF address buffer 40.
When the contents of the data in the main memory 15 at the location indicated by this operand address register 24, such as sending data, are required for processing the instruction, the data is used to retrieve the data from the main memory 15. be exposed. When only the location of the data is required, such as for receiving data, the address in the operand address register 24 is output as is to the execution unit 18 via the 0G address buffer 44. If the instruction includes a receiving side data number instruction section, the value of the instruction section is stored in the data number register 26. The data number register 26 is decremented by 1 each time the data generation section 17 generates sending data and sends it to the execution section 18.
The control device 32 operates to detect that the value of the data number register 26 becomes O and terminate the generation of the sending data. The instruction decoder 27 classifies the instruction into several processing types sufficient to specify the processing of data specified by the operand in the data generation section 17 according to the instruction code in the instruction code register 25. The classification work here is 1
There is no need to classify and decode each instruction,
Classify by instruction unit that retrieves and generates similar data. Data description information read from the IF type buffer 42 is stored in the type register S28 and the type register D29. Since the temporary storage device 30 contains data specified by the operand address register 24 and the content of the data is to be processed like the sending data, it is necessary to read it from the main storage device 15 by the data generation unit 17. Data is stored. The data converter 31 converts the data in the temporary storage device 30 into a type specified by the control device 32. In order to designate a conversion operation, the control device 32 classifies the processing type of the data specified by the operand using the output signal of the instruction decoder 27, and simultaneously records the results in the type register S28 and the type register D2.
Refer to the data description information in 9. Conversion designation from the control device 32 to the data converter 31 is performed via a conversion signal line 50. Types of conversion operations include high-level language processing such as conversion from binary to decimal, conversion from decimal to binary, and conversion to packed decimal for convenience when performing internal calculations in the execution unit. In addition, there is an operation to output the data type stored in the temporary storage device 30 as it is. The output of the data converter 31 is sent to the execution unit 18 via the 0G data buffer 45. At the same time, type register S28 or type register D2 has data description information corresponding to this data.
The contents of 9 are sent to the execution unit 18 via the 0G type buffer 46.
sent to. The contents of the instruction code register 25 are sent to the execution unit 18 via the 0G instruction buffer 47. The control device 32 has the function of controlling the operation of the data generation section 17 described above, and is realized by using a normal microprogram. The detailed configuration and operation of the control device 32 will be omitted since they are not directly related to the gist of the present invention. An example of a control device using a microprogram is the computer 360 series already sold by IBM. When the execution unit 18 becomes ready to execute a new instruction, it stores the oldest stored instruction code in the 0G instruction buffer 47 into the instruction execution code register 33. According to the contents of the instruction execution code register 33, an instruction is executed based on the data description information from the 0G type buffer 46, the data from the 0G data buffer 45, and the address from the address buffer 44. Next, refer to FIGS. 4, 5, and 7 for the operation when the machine language instruction in FIG. I will explain while doing so.

The machine language instructions in FIG. 4 are transferred from the storage device 15 to the instruction buffer 2.
After being stored in the instruction register 2 along with several instructions, when this instruction becomes a processing target in the instruction fetching unit 16, the instruction register 2
Shifted to 1. Next, as shown in FIG. 4, the instruction code is MMOVE, and the number of receiving side data is two as indicated by the receiving side data number indicator.
Therefore, it is detected that there are a total of three operands indicating sending data and receiving data, and an address expansion operation for each operand is started. At the same time, the instruction code and 16 bits of the receiving side data instruction part are sent from the instruction register 21 to the IF instruction buffer 43. 7th
The figure shows each operand. Since each operand in FIG. 7 is of direct type and is arithmetic data, the two bits of each operand, bit O and bit 1, are represented by 01, and the three bits from bit 2 to bit 4 are represented by 010. It is indicated by.

Since the data on the sending side is a real number, a decimal number, and a fixed point, the mode, base, and scale bits from bit 5 to bit 7 of the operand in FIG. 7a are 010. The number of digits of this data is four decimal digits, and is shown as an 8-bit value from bit 8 to bit 15 in FIG. 7a. The number of digits after the decimal point is O, from bit 16 to bit 2.
It is indicated by an 8-bit value up to 3. It is shown in three fields from bit 28 to bit 47 that the address information of this sending data includes pointers pointing to index register O and base register 3, and displacements which are DSPs. In the operand of FIG. 7b showing the first receiving data RA, the information from bit 5 to bit 47 includes a real number, binary number, fixed point, 10 digits in binary, number of digits after the decimal point 0, index register 1, Base register 2 and displacement are shown to be DSPRA. In the operand of FIG. 7c showing the second receiving data RB, the information from bit 5 to bit 47 is as follows:
It is shown that the real number, decimal number, fixed point, 6 decimal digits, 1 decimal place, index register O, base register 3, and displacement are DSPRB. Address expansion of these operands is performed in the order of appearance within the instruction, with address expansion of operand 0Ss being performed first. The contents of index register 0 and base register 3 of address modification register group 22 of FIG. 6 and instruction register 2 are determined by the values 0 and 3 of each pointer pointing to the index register and base register of FIG.
The address of the sending data is calculated by inputting the value of the displacement DISPs in FIG. 7a in FIG. 1 to the address calculator 23.
Since this operand is of direct type, the value of the address calculator result obtained here indicates the location in the main memory 15 where the sending data is stored, so this value is sent to the IF address buffer 40. . At the same time, bit O in Figure 7a
Data description information indicating data attributes from bit 23 to bit 23 is sent from the instruction register 21 to the IF type buffer 42. The processing in the instruction fetch unit 16 regarding the operand 0S8 of the sending data is completed, and then the instruction fetch unit 16 processes the operand 0SRA of the first receiving data. The address expansion of this operand is performed in the same way as the operand 0Ss of the sending data, and the result of calculating the contents of index register 1 and base register 2 in the address modification register group 22 and the value of displacement DSPRA by the address calculator 23 is It is sent to the IF address buffer 40.
At the same time, data description information indicating data attributes from bit 0 to bit 23 in FIG. 7 is sent from the instruction register 21 to the IF type buffer 42. Next, the second receiving side data operand 0SRB is processed by the instruction retrieval unit 16. As a result, the address of the 4RB receiving side data is sent to the 1F address buffer 40, and the IF type buffer 42
The data description information regarding the data attributes from bit 0 to bit 23 in FIG. 7c is sent. MM shown in Figure 4
FIG. 8 shows the states of the IF type buffer 42 and the IF address buffer 40 at the time when the OVE instruction has been processed by the instruction fetch section. The data generation unit 17 completes the processing of the instruction preceding the MMOVE instruction, and then
By this time, when the data specified by the operand of the VE instruction can be processed, the IF instruction buffer 4
M, which is the oldest stored instruction among the 3
The instruction code related to the MOVE instruction and the value of the receiving side data number indicator are stored in the instruction code register 25 in the data generation section 17. Then, at the same time as starting data processing regarding the MMOVE instruction, the contents of the instruction code register 25 having MMOVE instruction related information are sent to the 0G instruction buffer 47. The instruction codes in instruction code register 25 are classified by instruction decoder 27 into specific types of data processing. Regarding MMOVE, in accordance with this decoder result, when the control device 32 detects that the instruction is provided with a receiving side data number instruction section and requires data generation the number of times specified by this instruction section, the instruction code register is 25 receiving side data number instruction parts are stored in the data number register 26. The type register S28 stores data description information of the sending data S, which is the oldest information stored in the IF type buffer 42 by this time. At this time, bit O and bit 1 in Figure 7a
I corresponding to the 2 bits indicating the type of operand indicated by
Examine the bits in F-type buffer 42. As a result, since it is a direct type operand indicated by ゛゜01゛, it is found that the address corresponding to the sending data S is stored in the IF address buffer 40, and the IF address buffer 40 is stored in the operand address register 24. An address indicating the position of the sending data S in is stored. Since this address is the address of the sending data, the data generation unit 17 reads the content of the sending data S from the location in the main storage device 15 specified by the operand address register 24 and stores the content in the temporary storage device 30. be done. The number of digits of the number read at this time is four digits, depending on the total number of digits of the data description information regarding the data attribute stored in the type register S28. Also, this data is a decimal number, and one decimal digit is displayed in 1 byte, and a code is displayed in 1 byte before the decimal digit data, so the number of bytes read from the main memory 15 is 5 bytes. Next, IF type buffer 4
The information shown by bits 0 to 23 in FIG. 7b regarding the receiving side data RA, which is the oldest information among the data description information of . One report is stored in type register D29. At the same time, the receiving side data R is transferred from the IF address buffer to the address of the sending side data.
The address corresponding to A is operand address register 2
It is stored in 4. The control device 32 determines the data conversion type based on the data type, mode, base, and scale information shown in FIG. 5 stored in the type register S28 and the type register D129. Since the base bit values of each operand in Figures 7a and 7b are ``1'' and ``0'', the sending data is a decimal number and the receiving data is a binary number, so convert from decimal to binary. According to this conversion decision, a conversion signal line 5 is sent from the control device 32 to the data converter 31 so that the decimal sending data stored in the temporary storage device 30 is converted from decimal to binary.
Directed via 02. The converted binary number is sent to the 0G data buffer 45. At the same time, data description information regarding the sending data S is sent from the type register S28 to the 0G type buffer 46. At this time, bits 0 and 1 indicating the operand type of the operand shown in FIG. 7a are removed as data description information, and information indicating the data type, mode, base and scale after conversion is added. Next, the address of the receiving data RA, which is the current content of the operand address register 24, is sent as is to the 0G address buffer 44.

At the same time, data description information regarding the receiving side data RA is sent from the type register D29 to the 0G type buffer 46. At this time, bits 0 and 1 indicating the operand type of the operand shown in FIG. 7b are removed as data description information. When the above operation is performed, the value of the data number register 26 is decreased by 1 by the control device 32, so that the value becomes 1. The operations related to the first data generation are completed by the operations so far. Next, the data description information of the receiving side data RB in the IF type buffer 42 is stored in the type register D29. At this time, the address corresponding to the receiving side data RB is stored in the operand address register 24 from the IF address buffer as in the case of the sending side data S. The control device 32 determines the data conversion type based on the data description information regarding the sending data S stored in the type register S28 and the information stored in the type register D29. Since the data description information from bit 2 to bit 23 of each operand in FIG. 7a and FIG. The control device 32 instructs the data converter 31 via the conversion signal line 50 to output the signal 31. Data converter 31
The decimal output data is sent to the 0G data buffer 45. At the same time, data description information regarding the sending data S is sent from the type register S28 to the 0G type buffer 46. Creation of data description information at this time is performed in the same manner as in the case of the first data generation. Next, the address of the receiving data RB in the operand address register 24 is sent as is to the 0G address buffer 44. At the same time, the data description information regarding the receiving side data RB is stored in the type register D29 as in the case where the receiving side data is RA.
from there to the 0G type buffer 46. When the above operations are performed, the control device 32 controls the data number register 2.
The value of 6 is subtracted by 1, resulting in a value of 0. The second data generation is completed by the operations so far. In response to the output of the data number register 26, the control device 32 detects that the output has become 0, and that data generation corresponding to the number of receiving side data has been completed. This makes the fourth
The processing in the data generation unit 17 regarding the MMOVE command shown in the figure is completed. Subsequently, the data generation unit 17 starts processing the instruction operands in the IF instruction buffer 43 following the MMOVE instruction. FIG. 9 shows the data generation section 17 to 0 when the MMOVE instruction of FIG. 4 is processed by the data generation section.
G type buffer 46 and 0G data buffer 45 and 0G
The output timings of descriptive information, generated data, and addresses sent to the address buffer 44 are shown.

The operand-related information is 10 at the beginning (time T).
The data generator 17 converts the sending data S, which is a base number, into a binary number and outputs generated data and data description information corresponding to this data. This data description information is information to which information regarding the generated data is added by the data generation unit 17. These outputs end (time t
1) and the address of the receiving side data RA of the binary data, and simultaneously output data description information of RA as data description information. Next, according to the conversion type determined by the data type of the receiving data RB, the sending data S, which is a decimal number, is output as generated data at time T2 without type conversion. At the same time (T2), information on the conversion result and the like is added as data description information corresponding to this data and output. When these outputs are completed (time T3), the above 10
At the same time as the address of the data RB on the receiving side of the hexadecimal data, data description information of the RB is output as data description information. In the execution unit 18, the MM stored in the 0G instruction buffer 47
When the OVE instruction becomes executable, the instruction code and the value of the receiving side data number instruction part are stored in the instruction execution code register 33, and the execution of the MMOVE instruction is started.

The processing in the execution unit 18 is to extract information regarding binary data, which is the sending data, from the 0G type buffer 46, and then extract data description information of the RA, which is the receiving data, from the 0G data buffer 45. The binary data is sent to the location in the main memory 15 indicated by the address of the receiving data RA taken out from the 0G address buffer 44. Next, the main memory 1 is indicated by the address of the decimal data receiving side data RB.
MM by performing the same operation as above to send the MM
End the OE command. When transferring data to the main storage device 15, the following operations are performed depending on the data description information. That is, an operation is performed to match the decimal point positions of the sending data and receiving data, and an operation to perform zero padding or check for overflow when storing data in the main memory. As described above, when the data generation device of the present invention is used, data management in the execution unit can be simplified by generating and converting appropriate data according to the receiving data prior to the execution unit. I can do it. Therefore, in the present invention, if a highly functional machine language instruction is executed using a conventional data processing device configured with four multiple processing units, a large amount of processing will be required in the execution unit. This also solves the drawback that the performance of the device is not improved. Furthermore, in the present invention, the processing that precedes the execution unit is divided into several processing units, and the amount of processing in each processing unit is approximately equalized, thereby making effective use of each processing unit and increasing the instruction execution speed. It can be done quickly.

[Brief Description of the Drawings] Figure 1 is a diagram showing an example of an assignment statement instruction in the PL/1 language and an example of a conventional machine language instruction. FIG. 3 is a diagram showing an example of a machine language instruction with advanced functionality; FIG. 4 is a diagram showing an example of a machine language instruction with advanced functionality used in the present invention; FIG. 5 is a diagram showing an example of a machine language instruction with advanced functionality. A diagram showing an example of operands in a machine language instruction with advanced functions used in the present invention, FIG. 6 is a block diagram showing an embodiment of the present invention, and FIG. 7 shows each of the machine language instructions shown in FIG. FIG. 8 is a diagram showing an example of an operand, and FIG. 9 is a diagram showing an IF type buffer and an IF address buffer when the instruction fetch unit 16 in FIG. 6 finishes processing the machine language instruction shown in FIG. 4. is the fourth in the data generation section.
FIG. 3 is a diagram showing output timing when processing the machine language instruction shown in the figure. In FIG. 6, 15...main storage device, . 16...
Instruction fetch unit, 17...Data generation unit, 18...Execution unit, 20...Instruction buffer, 21...Instruction register, 22...Address modification register group, 23...Address calculator, 24... Operand address register, 25... Instruction code register, 26... Data number register, 27... Instruction decoder, 28... Type register S, 29... Type register D, 3O...・
Temporary storage device, 31... Data converter, 32... Control device, 33... Instruction execution code register, 40...
・IF address buffer, 41... Literal data buffer, 42... IF type buffer, 43...I
F instruction buffer, 44...0G address buffer, 4
5...0G data buffer, 46...0G type buffer, 47...0G instruction buffer, 50...conversion signal line.

Claims (1)

[Claims] 1. In a data generation device of a data processing device that processes an instruction by dividing it into multiple processing units, the operand is a target for repeated operations and an operation count instruction unit that specifies the number of operations of this operand. an instruction decoder that determines whether or not the instruction is a machine language instruction that includes a machine language instruction; a temporary storage device that temporarily stores data specified by the operand retrieved from a storage device; a data count register that monitors the number of times data is generated, a data converter that converts the data in the temporary storage device into data with different properties, and a data count register that monitors the number of times the data is generated as instructed by the operand in the instruction decoder. a control device that performs a control operation to cause the data converter to convert and generate data to be repeatedly generated in the temporary storage device as many times as permitted by the data number register, which is decoded to be an instruction that is a command; configured to repeatedly generate the generation target data stored in the temporary storage device as many times as specified by the operation count instruction part of the machine language instruction, with data conversion necessary for processing the machine language instruction. Characteristic data generation device.