JPS5919373A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide low power consumption and high speed by forming a high density base regin on the part of a main base region, then forming an oxidized films of different thicknesses, and forming base and emitter regions on the thinner polycrystalline silicon layer. CONSTITUTION:A buried diffused layer 2 is formed on a silicon substrate 1, a deep collector region 5 is formed, and the surfaces of epitaxial layers 3, 5 to become collectors are exposed. Then, a main base layer 61 is formed by ion implanting on the surface of the layer 3. Then, polycrystalline silicon layers 7 (71-74) and mask layers 8 (81-84) having the prescribed pattern are laminated on the overall surface of the substrate. Then, with the layer 8 as a mask a high density base region 62 is formed on the part of the layer 61. Thereafter, the unnecessary part of the layer 7 is oxidized to form a thick oxidized film 9, the layer 8 is removed, the surface is then oxidized thinly, and with resist layers 80 (805-807) as masks an impurity is implanted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device.

In the manufacture of bipolar semiconductor integrated circuits, reducing the element area not only improves the integration density, but also reduces power consumption and enables high-speed operation by reducing parasitic capacitance.

For the above purpose, in recent years there has been a lack of technology to further significantly reduce the transistor space area, which is usually defined by the microfabrication limit of electrode metallization and the mask alignment margin, by extracting the electrode using polycrystalline silicon. An example of the proposed method is shown in FIG.

As mentioned above, Figure 1 shows an example in which the electrodes are formed using self-alignment technology using polycrystalline silicon, and polycrystalline silicon is used as a resistor to reduce parasitic capacitance. will be explained step by step below.

First, by using a known technique, N-buried diffusion is performed on a P-type substrate, and through an N-type epitaxial layer growth and oxide film separation process, an N-deep collector region for reducing collector resistance is formed.
The state after diffusion until reaching the N buried layer is shown in FIG.

That is, in FIG. 1 (3), 1 is a P-type silicon substrate, 2 is an N-type buried diffusion layer, and 3 is a collector.
An epitaxial layer, 4 an element isolation silicon oxide film, and 5 an N deep collector region.

Next, as shown in FIG. 1), a P-type impurity such as boron is selectively introduced into the surface of the collector layer 30 by a method such as ion implantation to form the main base layer 6.

Subsequently, as shown in FIG. 1C), a polycrystalline silicon layer 7 is grown on the entire surface, and predetermined portions on the polycrystalline silicon layer 7, namely, the side space, the space electrode lead-out portion, and the emitter/collector are grown. A mask ff1ftLl for selective oxidation is applied to areas where electrodes, resistors, etc. are planned to be formed.
81183184 is formed.

The mask layers 81, Eh, 8g, and 84 are two-layer films in which a silicon nitride film is laminated on a thin silicon oxide film.

Next, by selective oxidation treatment, as shown in FIG. The crystalline silicon layer is replaced by a silicon oxide layer 9.

Subsequently, the mask layer 8184 in the side base and space electrode lead-out portions and the resistor forming portions is removed, and a high concentration of P-type impurity, for example, is implanted into the polycrystalline silicon layers 7□, 74 in those portions by ion implantation or the like.
Introduce boron and perform thermal oxidation treatment. At this time, Figure 1■
As shown in FIG. 2, a part of the P-type impurity in the polycrystalline silicon/ii 7 diffuses into the main base layer 6 and becomes a side space region 10.

Subsequently, the remaining mask layers 82+81 are removed, and a high concentration of N-type impurity, for example, arsenic, is introduced into this portion of the polycrystalline silicon layer 7m+71, and a thermal oxidation treatment is performed to form the emitter region 11 in the main base layer 6. form (Figure 1 (
to)). At the same time, the side space region 10 is diffused deeper.

As shown in Fig. 1Q, he opens a contact hole and connects the metal wiring 123 H122H12s 1124 +1
2g is applied to complete the semiconductor integrated circuit device.

The contact hole is opened in a self-aligned manner through the surrounding thick silicon oxide film 9, and the space electrode is led out of the filial region by the polycrystalline silicon layer 71, and the metal wiring @12. is connected.

Note that both ends of the emitter region 11 in the direction perpendicular to the plane of the paper are in contact with the isolation oxide film 4, forming a so-called walled emitter structure.

The above manufacturing method is an excellent method that allows easy formation of a walled emitter structure transoster with high withstand voltage, and a significant reduction in the area of the shield by drawing out the space electrode using polycrystalline silicon. It also has the disadvantages listed below.

(1) Since there is a lot of heat treatment between the formation of the main base layer (FIG. 1) and the formation of the emitter region (FIG. 1), the main base layer becomes deep.

(2) In removing the mask layer 83 on the emitter region,
Polycrystalline silicon J
*A wedge-shaped silicon oxide film (so-called bird's beak) is formed between the 7s and the mask a8s.
k) remains, it is difficult to supply a sufficient amount of N-type impurity into the polycrystalline silicon layer 7s.

(3) Since the impurity diffusion coefficient in polycrystalline silicon is significantly faster than that in single-crystalline silicon, the N-type impurity introduced into the polycrystalline silicon layer 71 on the emitter region is uniformly distributed throughout the polycrystalline silicon * 7 m. After the main base layer 6
However, since the polycrystalline silicon layer 71 is thick, a high surface concentration of entrants cannot be obtained.

(4) The layer resistance of a polycrystalline silicon layer at a high impurity concentration strongly depends on the film thickness, and becomes higher as the film thickness becomes thinner.

Furthermore, since the surface of the polycrystalline silicon is oxidized, the impurity concentration in the polycrystalline silicon decreases due to the segregation of impurities (boron) into the growing oxide film. Therefore, it is difficult to reduce the resistance of the polycrystalline silicon layer 71 for leading out the pace electrode, whose thickness has been reduced by the two oxidation treatments.

(5) Similarly, the reproducibility of the resistance value is poor due to the large thickness change sound of the resistor polycrystalline silicon layer 74 and the segregation of impurities.

(6) A high-resistance main base layer 6 is interposed between the emitter region 11 and the side space region 10.

(7) The impurity introduced into the emitter region 11 evaporates at the initial stage of the subsequent thermal oxidation treatment, and the emitter impurity concentration becomes non-uniform.

Among the above, according to items )1), [2), and 131, the transistor width is wide and the emitter concentration is low, so the injection efficiency is low and the emitter common current amplification factor hf.
(difficult to obtain), and as a result, the cutoff frequency fT cannot be made high.

゛Also, by terms (4) and (6), the pace series resistance r
When b is high, both of the above two points deteriorate the high frequency characteristics of the transistor.

In other words, miniaturization of elements and use of polycrystalline silicon resistors reduce parasitic sounds and improve the delay time power consumption product in the low power consumption region (low current region), but the current Even if the delay time is increased, the delay time does not decrease as much as in a structure that does not use normal polycrystalline silicon, and for the reasons mentioned in f5) and (7) above, the characteristics of integrated circuit devices are sensitive to changes in processing conditions. However, it has the disadvantage that it is difficult to obtain stable performance.

Furthermore, to improve item (1), low-temperature treatment is required, but if the temperature of the oxidation treatment after introducing Pm impurities (boron) into the polycrystalline silicon layer '7' + +74 is lowered, the polycrystalline silicon layer The segregation of impurities into the silicon oxide film that grows from the silicon oxide film increases, increasing the paste series resistance rb and increasing the variation in resistance value.

In addition, in order to improve items (2) and (3), the oxide film on the polycrystalline silicon layers 71+74 must be made thicker, which leads to deterioration of items (4) and (5). As mentioned above,
Items (1) to (3), and items (4) and (5) had contradictory requirements.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device that can obtain a high-density bipolar conductor integrated circuit device that combines low power consumption and high speed. purpose.

Embodiments of the method for manufacturing a semiconductor integrated circuit device of the present invention will be described below with reference to the drawings. Figure 2 prisoner or second
Figure (G) is a diagram for explaining the manufacturing process of one example. In these figures, the same parts as in Figures 1 (4) to 1 (G) are given the same reference numerals. The explanation will be omitted.

FIG. 2(4) is a diagram showing a state in which the surface of the epitaxial layer (first region) 3 that becomes the collector and the surface of the Dino collector region 5 is exposed after the formation of the Dino collector region 5 is completed in the same manner as in the conventional example. It is.

Next, Pm impurities are introduced into the surface of the epitaxial layer 3 to form main space #61 (second region).
As a method, heavy compounds containing boron, such as BF
, a very shallow main base layer 61 is obtained.

After that, a polycrystalline silicon layer 7 is deposited on the entire surface of the substrate at a thickness of 2000 nm.
The film is grown to a thickness of ~5000 Å, and a mask NjI8 consisting of a silicon oxide film and a silicon nitride film is further laminated (FIG. 2(B)).

Next, using ordinary photolithography, the necessary parts are masked as shown in FIG.
After removing the remaining portions of the mask layer 8, leaving the mask layer 84, a Pm impurity, for example, boron, is added using the Lenost layers 801, 802, 803, 804 used for etching and the remaining mask $8x 181 +8m +84 as a mask. Ions are implanted through the polycrystalline silicon with an acceleration energy that reaches the single crystal silicon region, forming a high-definition base region 6 in the main space Nl 161(7)-1.

Next, the Lennost layer is removed and annealed at a temperature of about 900.degree. C., and as shown in FIG. At this time, in order not to deepen the main base layer 61,
It is desirable to form silicon oxide film 9 at a relatively low temperature by high-pressure oxidation.

Next, after removing the mask layer 51182183184 and thinly oxidizing the surface of the polycrystalline silicon layer 71+7M+74 (not shown), the resist layer 80i H80@, 807 is formed as shown in FIG. As a mask,
Polycrystalline silicon layer 7! +71 by ion implantation, N
Type impurities, such as arsenic deposits, are introduced to a high performance level of about 1016c1n-2.

Note that, unlike the conventional example, all mask layers were heated to 81°F+8
Since 1+84 is removed at the same time, when removing the silicon oxide film below the mask layer, the entire surrounding area is covered with a very thick silicon oxide film 9, so the bird's beak can be removed by sufficient overetching. .

Resist layer 80g, 80. ．． 80. When it is oxidized at a relatively low temperature, a thick oxide film is formed on the polycrystalline silicon layer 72 + 71, which contains a high concentration of impurities, and a thinner oxide film is formed on the other parts 71 + 74. grows.

Next, a polycrystalline silicon layer 71+7 without impurities is formed.
When introducing a high concentration of P-type impurity (e.g. i1' boron) into 4 by ion implantation, by selecting an appropriate acceleration energy according to the above-mentioned oxide film thickness difference, 7 is self-aligned.
You can type only 1174. Thereafter, by heat treatment in a non-oxidizing atmosphere, impurities are diffused from the polycrystalline silicon layer 7F+7 as shown in FIG. 4 regions) 11 are formed.

Subsequently, as in the conventional example, as shown in FIG.
．． 124.12. The semiconductor integrated circuit device is then completed.

According to the embodiments described above, the following advantages can be obtained.

(a) Extremely shallow main base due to the fact that the main paste is formed by compound ion implantation with a small ion implantation range, and that the temperature of the heat treatment between the main paste formation and the introduction of emitter impurities can be lowered. A layer can be formed.

(b) When removing the mask layer 82 on the emitter region, sufficient overetching is possible, so the bird's beak is removed and a sufficient amount of N-type impurity can be supplied into the polycrystalline silicon layer 72.

(C) Since the segregation coefficient of N-type impurities such as arsenic is as large as about 10, even after forming a thick oxide film on the surface of the polycrystalline silicon layer 78, most of the N-type impurities are reduced in thickness. Since the N-type impurity concentration remains in the polycrystalline silicon 73 and becomes high, a region 11 having a high surface concentration can be formed.

(d) This is because the polycrystalline silicon layer 74 for resistance has less oxidation cap, the polycrystalline silicon layer is kept thick, and there is no effect of segregation because there is no oxidation treatment after introducing the P-type impurity. Good reproducibility of resistance values.

(e) For the same reason), it is easy to reduce the resistance of the polycrystalline silicon 17t for leading out the pace electrode, and the high concentration pace region 6g is formed between the emitter region 11 and the side space region 10. Pace series resistance r
b is small.

), N is applied to the polycrystalline silicon layer 72 through a thin oxide film.
By introducing the type impurity, evaporation of the impurity is prevented, and the uniformity of the emitter impurity concentration is significantly improved.

As described above, this embodiment can eliminate all the drawbacks of semiconductor integrated circuit devices manufactured by conventional manufacturing methods, and has stable characteristics suitable for high-speed operation with high hfe ft and low rb. It is possible to manufacture a semiconductor integrated circuit device that can form a transistor and a polycrystalline silicon resistor with good resistance value reproducibility, has low power consumption, high-speed operation, and has stable performance.

As described in detail above, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, after forming a main space region in a buried diffusion seed of a silicon substrate, a mask having a polycrystalline silicon layer and a predetermined pattern is formed on the surface of the substrate. Using this mask as a mask, a high-concentration paste region is formed in a part of the main paste region, and after this high-concentration base region is formed, a thick oxide film and a thin oxide film are selectively formed on the surface of the polycrystalline silicon layer. Then, using the difference in film thickness, impurity ions are implanted into the polycrystalline silicon layer with a thin oxide film to diffuse the impurity into the main base region to form side base regions and emitter regions. Since the necessary portions of the layer are made of polycrystalline silicon resistors, semiconductor devices having transistors having high lfe, high fT, and low rb and polycrystalline silicon resistors can be manufactured stably with good reproducibility.

Accordingly, it can be widely used for manufacturing bipolar type semiconductor integrated circuit devices including ECL, 5TTL, etc., which have low power consumption, high speed operation, and high integration density.

[Brief explanation of the drawing]

Figure 1 ~ (Q is a process explanatory diagram for explaining the conventional manufacturing method of a semiconductor integrated circuit device, Figure 2 ~ (G
) are process diagrams 8A and 8A for explaining an example of the method for manufacturing a semiconductor integrated circuit device according to the present invention. ■...Silicon substrate, 2...Buried diffusion layer, 3...
Epitaxial layer, 4... silicon oxide film, 5...
Deep collector, 6,6. ...Main base, 63
...High concentration base, 7+71-74...Polycrystalline silicon lit, 8°81-84...Mask layer, 9.
... Polycrystalline silicon oxide film, 10... Side base,
11... Engineering Z ivy, 121-125... Metal wiring,
801-807...Lesosto. Patent Applicant Oki Electric Industry Co., Ltd. 331- Procedural Amendment May 20, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1. Indication of the Case 1988 Patent Application No. 127563 2. Name of the Invention Attack on Semiconductor Integrated Circuit Devices Method of construction 3, Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa, Month, Day (spontaneous) 6, Patent of the specification to be amended Scope of Claims and Detailed Description of the Invention, Part of Drawings 7, Contents of Amendment as shown in Attachment 7, Contents of Amendment 1) "2. Scope of Claims" in the specification is corrected as shown in Attachment 7. 2) "Contact" on page 5, line 16 of the specification is corrected to "contact." 3) Corrected page 7, line 19, rhfe Jorhfe J. 4) rrbJThr on page 8, lines 1 and 17, respectively.
Correct it as rbb' J. 5) Delete all "(first area)" on page 9, line 17. 6) Delete all “(M2 area)” at the end of page 9. 7) On page 10, line 3, ``Ogoshigari'' is corrected to ``Suitable''. 8) Delete "(3rd area)" on page 12, line 10. 9) Delete "(4th area)" on page 12, lines 10 and 11. 10) rrbJThr on page 14, lines 1 and 9, respectively.
Correct it as rbb'j. 11) Same page 14, lines 15 and 16 [For the buried diffusion layer of the silicon substrate] and ``For the silicon substrate that has been subjected to prescribed processing.''
I am corrected. 12) Last line of page 14: “After formation of this high concentration”
1. After selective oxidation of polycrystalline silicon, emitter impurities are introduced into a portion of the polycrystalline silicon.'' 13) On page 15, line 4, ``de'' is corrected to ``dan nochi,''. 14) Same page 15, line 8, correct as rrb J k [rbb' J. 15) Correct the drawing Figure 2 (2) as shown in the attached sheet. 2. Claims A first step of forming an epitaxial layer, an element isolation silicon oxide film, and a deep collector region in a buried diffusion layer of a predetermined conductivity type formed in a silicon substrate, and a main space region in the epitaxial layer. a second step of forming a polycrystalline silicon layer and a mask having a predetermined pattern on the surface of the substrate; and a third step of forming a high concentration pace region in a part of the main pace region using this mask as a mask. After forming the high concentration pace region, selectively oxidizing the polycrystalline silicon layer, thinly oxidizing the surface of the polycrystalline silicon layer to introduce impurities into a part of the polycrystalline silicon layer, and a fourth step of selectively forming a thick oxide film on the surface of the polycrystalline silicon layer and forming a thin oxide film on the surface of the polycrystalline silicon layer other than the thick oxide film; Due to the difference in oxide film thickness on the surface! A thin oxide film! After implanting impurity ions into the polycrystalline silicon layer, the impurities are fully diffused into the main space region to form side space regions and an emitter region, and impurity ions are implanted into a predetermined portion of the polycrystalline silicon having the thin oxide film. A method for manufacturing a semiconductor integrated circuit device, comprising a fifth step of completely forming a crystalline silicon resistor. Figure 2

Claims (1)

[Claims] A first step is to form an epitaxial layer, an element isolation silicon oxide film, and a Dino collector region in a buried diffusion layer of a predetermined conductivity type formed on a silicon substrate, and after forming a main space region in the epitaxial layer, a surface of the substrate is formed. a second step of forming a polycrystalline silicon layer and a mask having a predetermined pattern, a third step of forming a high concentration pace region in a part of the main pace region using this mask as a mask, and a third step of forming a high concentration pace region in a part of the main pace region; After forming the space region, the surface of the polycrystalline silicon layer is thinly oxidized to introduce impurities into the polycrystalline silicon layer, and a thick oxide film is selectively formed on the surface of the polycrystalline silicon layer. A fourth step of forming a thin oxide film on the surface of the polycrystalline silicon layer other than the film, and adding impurities to the polycrystalline silicon layer having the thin oxide film due to the difference in oxide film thickness on the surface of the polycrystalline silicon layer. A fifth step of implanting ions to diffuse impurities into the main space region to form a zide space region and an emitter region, and forming a polycrystalline silicon resistor in a predetermined portion of the polycrystalline silicon having the thin oxide film. A method of manufacturing a semiconductor integrated circuit device.