JPS59188259A - Amplifier for bus receiver - Google Patents
Amplifier for bus receiverInfo
- Publication number
- JPS59188259A JPS59188259A JP6313383A JP6313383A JPS59188259A JP S59188259 A JPS59188259 A JP S59188259A JP 6313383 A JP6313383 A JP 6313383A JP 6313383 A JP6313383 A JP 6313383A JP S59188259 A JPS59188259 A JP S59188259A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- circuit
- gain
- equalization
- station
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 abstract description 15
- 239000003990 capacitor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 230000002238 attenuated effect Effects 0.000 description 2
- 241000282693 Cercopithecidae Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はデータウェイのパスレシーバに関し、更に詳し
くはその内部に等化機能をもたせて通信ラインの高速化
、長距離化を図ることができるようにしたパスレシーバ
用増幅器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data way path receiver, and more particularly to a path receiver amplifier that has an internal equalization function to enable faster and longer communication lines. Regarding.
伝送線路(同軸ケーブルが多い)1本を複数の機器で共
有する所謂データウェイは広く普及しており、第1図に
その構成例を示す。図はリニア形のデータウェイを示し
ている。図において、S□〜5n(nは整数、以下同じ
)はステーション、T1〜Tnはトランシーバ、A工〜
Anは結合器、DBは伝送線路である。各ステーション
数工〜Snと伝送線路DBとはバス結合器A□〜Anに
よって行われ、トランシーバT1〜Tnによって論理レ
ベルに変換される。このような構成のデータウェイでは
、伝送長やステーション数に対する制限は、減衰、帯域
及び反射によって決定される。即ち、負荷(ステーショ
ン)数が増すと挿入による減衰増加と反射増加が生じる
。また、ケーブル長が増すと減衰と帯域制限が増加する
。A so-called data way, in which a single transmission line (often a coaxial cable) is shared by multiple devices, is widely used, and an example of its configuration is shown in FIG. The figure shows a linear dataway. In the figure, S□~5n (n is an integer, the same applies hereinafter) are stations, T1~Tn are transceivers, and A~5n are stations.
An is a coupler, and DB is a transmission line. The connections between each station ~Sn and the transmission line DB are performed by bus couplers A□~An, and converted to logic levels by transceivers T1~Tn. In dataways configured in this manner, limitations on transmission length and number of stations are determined by attenuation, bandwidth, and reflection. That is, as the number of loads (stations) increases, attenuation increases and reflections increase due to insertion. Additionally, increasing cable length increases attenuation and bandwidth limitations.
第2図は信号の伝播特性を示す図である。図において、
(a)はステーションS1の、(b)はステーションS
2の、(C)はステーションSnのそれぞれ受信信号波
形を示している。ステーションSにおいては、受信信号
が減衰しかつ波形がなまっていることがわかる。
−猿また、ケーブル長
が増すと減衰と帯域制限が増加する。1対1の伝送であ
れば、減衰や帯域制限はこれと逆特性をもつ回路により
等化が可能である。しかしながら、データウェイの場合
、伝送経路が通信ごとに変わるため等化を行わないのが
一般的であった。このため、1対″1伝送の場合に比べ
第1図のリニア形データウェイの場合、伝送長が大幅に
制限されていた。FIG. 2 is a diagram showing signal propagation characteristics. In the figure,
(a) is station S1, (b) is station S
2, (C) shows the respective received signal waveforms of station Sn. It can be seen that at station S, the received signal is attenuated and the waveform is blunted.
- Monkey Also, as the cable length increases, attenuation and bandwidth limiting increase. In the case of one-to-one transmission, attenuation and band limitation can be equalized by a circuit with opposite characteristics. However, in the case of data ways, equalization is not generally performed because the transmission path changes for each communication. Therefore, in the case of the linear data way shown in FIG. 1, the transmission length is significantly limited compared to the case of one-to-one transmission.
本発明はこのような点に鑑みてなされたものであって、
各ステーションごとのパスレシーバに適当な波形等化機
能をもたせて通信ラインの高速化、長距離化を図ること
ができるパスレシーバ用増幅器を実現したものである。The present invention has been made in view of these points, and
A path receiver amplifier has been realized that can increase the speed and distance of communication lines by providing a suitable waveform equalization function to the path receiver of each station.
以下、図面を参照して本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.
第3図は、トランシーバの構成を示す図である。FIG. 3 is a diagram showing the configuration of the transceiver.
図において、1は伝送線路DBに取付けられた結合器)
2は送信用ドライバ、3は受信用増幅器、4は該アンプ
の出力を受ける識別器である。増幅器3と識別器4とで
パスレシーバを構成し、増幅器3に等化機能を設けてい
る。第4図は信号の伝達特性を示す図である。横軸は周
波数、縦軸はゲインである。fslはステーションS2
(第1図参照)の、fs□はステーションSの特性を示
し、それぞれにおいて1は等化なしの場合を、2は等化
適性の場合を、3は等化不適の場合をそれぞれ示してい
る。第5図は伝送波形を示す図であL(、)はステーシ
ョンSの、(b)はステーションS2の伝送波形を示し
ている。図中の番号1〜5は第4図のそれと同じである
。1は等化がない場合であり、近くのステーションでは
適であるが、遠くのステー/コンでは不適となる。3は
ステーションSで完全な波形が得られるように等化を行
った場合であるが、このようにするとステーションS2
で等化が大きくなりすぎる。これに対し、2ではステー
ションSでは等化不足であるが、その代わシスチージョ
ンS2でもそれほど波形の劣化が生じていない。In the figure, 1 is a coupler attached to the transmission line DB)
2 is a transmitting driver, 3 is a receiving amplifier, and 4 is a discriminator that receives the output of the amplifier. The amplifier 3 and the discriminator 4 constitute a path receiver, and the amplifier 3 is provided with an equalization function. FIG. 4 is a diagram showing signal transfer characteristics. The horizontal axis is frequency and the vertical axis is gain. fsl is station S2
(See Figure 1), fs□ indicates the characteristics of station S, where 1 indicates no equalization, 2 indicates suitability for equalization, and 3 indicates unsuitability for equalization. . FIG. 5 is a diagram showing transmission waveforms, where L(,) shows the transmission waveform of station S, and (b) shows the transmission waveform of station S2. Numbers 1 to 5 in the figure are the same as those in FIG. 1 is the case where there is no equalization, which is suitable for nearby stations, but not suitable for distant stays/cons. 3 is a case where equalization is performed so that a complete waveform can be obtained at station S.
The equalization becomes too large. On the other hand, in case 2, the equalization is insufficient at station S, but the waveform does not deteriorate so much even at system station S2.
このことから、ステーションSにおける等化不足量とス
テーションS2における等化オーバー量が等しくなるよ
うに等化量を設定した等化機能をアンプ3(第3図)に
持たせれば、信号の減衰しないデータウェイを実現する
ことができるととKなる。From this, if the amplifier 3 (Fig. 3) is equipped with an equalization function that sets the equalization amount so that the underequalization amount at station S is equal to the overequalization amount at station S2, the signal will not be attenuated. If a data way can be realized, it becomes K.
第6図社、本発明に係る等化機能をもった受信用増幅器
の一構成を示す電気回路図である。図に示す増幅器は、
トランジスタ骨工r Q2を用いた差動増幅器により構
成されている。2工はトランジスタQ□r Q2のエミ
ッタ間に接続された等化回路で、抵抗R□とキャパシタ
C□の直列回路よシ構成されている。10は定電流源で
ある。Rはエミッタ抵抗、R8はコレクタ抵抗である。FIG. 6 is an electric circuit diagram showing one configuration of a receiving amplifier having an equalization function according to the present invention. The amplifier shown in the figure is
It is composed of a differential amplifier using a transistor RQ2. The second circuit is an equalization circuit connected between the emitters of the transistor Q□r Q2, which is composed of a series circuit of a resistor R□ and a capacitor C□. 10 is a constant current source. R is an emitter resistance, and R8 is a collector resistance.
入力信号はトランジスタQll Q2のペース間に加え
られ、出力はコレクタ間から取出される。このように構
成された回路のゲインは、各抵抗、キャパシタ等の値と
して識別記号をそのまま用い、各ベースへの入力信号を
v1□。The input signal is applied between the paces of transistors Qll and Q2, and the output is taken from between the collectors. The gain of the circuit configured in this way is determined by using the identification symbols as values for each resistor, capacitor, etc., and inputting the input signal to each base to v1□.
V□2、各コレクタの出力信号をVV とすると01
′ 02
次式で与えられる。V□2, the output signal of each collector is VV, then 01
'02 It is given by the following equation.
等化回路2工として図に示すよりなRC直列回路を用い
たものとすると、(1)式は次のようKなる。Assuming that an RC series circuit as shown in the figure is used as the two equalizer circuits, equation (1) becomes K as follows.
(3)式で示されるゲインの周波数特性を図示すると第
7図のようになる。横軸は周波数、縦軸はゲインを示す
。周波数f工までは、通常のゲイン(ノーマライズ値で
1)を維持するが、f□以降ゲインが増加しf2で一定
値に達する。f工、f2及びゲインの増加量ΔGは、そ
れぞれ次式で表わされる。The frequency characteristic of the gain expressed by equation (3) is illustrated in FIG. 7. The horizontal axis shows frequency and the vertical axis shows gain. The normal gain (normalized value of 1) is maintained up to the frequency f, but after f□ the gain increases and reaches a constant value at f2. The f-work, f2, and gain increase amount ΔG are each expressed by the following equations.
2R。2R.
R□ (6)
即ち、第6図に示す回路ではf≧f1で効果が生じ、f
≧f2でゲインがΔGだけ増加する。本発明によれば、
高域でゲインが増加するので接続するステーション数が
増えたときでも信号波形の減衰、波形形状の変化を抑え
ることができ、ケーブル帯域制限を改善することができ
る。本発明回路の特長を列挙すれば、以下のとおシであ
る。R□ (6) That is, in the circuit shown in Fig. 6, the effect occurs when f≧f1, and f
When ≧f2, the gain increases by ΔG. According to the invention,
Since the gain increases in the high frequency range, even when the number of connected stations increases, signal waveform attenuation and waveform shape changes can be suppressed, and cable band limitations can be improved. The features of the circuit of the present invention are listed below.
(1) 差動形式なので入力のコモンモード電圧を除
去できる。(1) Since it is a differential type, input common mode voltage can be removed.
(2) 等化回路が1個であるため、複数個必要とす
る場合に生じる素子のバラツキが問題にならない。(2) Since there is only one equalizer circuit, variations in elements that occur when a plurality of equalizers are required do not become a problem.
り!I) 構成が極めて簡単である。the law of nature! I) The configuration is extremely simple.
第8図は、本発明回路をトランシーバに用いた例ヲ示す
図である。図では、ラインとトランスTで電気的に絶縁
されている例を示している。FIG. 8 is a diagram showing an example in which the circuit of the present invention is used in a transceiver. The figure shows an example in which the line and the transformer T are electrically insulated.
以上詳細に説明したように、本発明によれば各ステージ
11/ごとのパスレシーバに適当な波形等化機能をもた
せて通信ラインの高速化、長距離化を図ることができる
パスレシーバ用増幅器を寅現することができる。As described above in detail, the present invention provides a path receiver amplifier that can provide an appropriate waveform equalization function to the path receiver of each stage 11/11, thereby increasing the speed and distance of the communication line. It can be manifested.
第1図はデータウェイの構成を示す図、第2図は信号の
伝播特性を示す図、第3図はトランシーバの構成を示す
図、第4図は信号の伝達特性を示す図、第5図は伝送波
形を示す図、第6図は本発明の一実施例を示す電気回路
図、第7図はゲイン特性を示す図、第8図は本発明を適
用したトランシーバの構成を示す図である。
S−3・・づテーンヨン、T1〜Tn・・・トランシー
ツよ、n
A□〜An・・・結合器、DB・・・伝送線路、1・・
・結合器、2・・・ドライバ、6・・・受信用増幅器、
4・・・識別器、10・・・定電流源、Ro、 Re、
R□・・・抵抗、C工・・キャパシタ、Q□、Q2・
・・トランジスタ、2工・・等化回路。
第1図
第2図
第3図
第4図
第5図
第6図
Vee
第7図
↑
第8図
eeFigure 1 shows the configuration of the dataway, Figure 2 shows the signal propagation characteristics, Figure 3 shows the transceiver configuration, Figure 4 shows the signal transfer characteristics, and Figure 5. 6 is a diagram showing a transmission waveform, FIG. 6 is an electric circuit diagram showing an embodiment of the present invention, FIG. 7 is a diagram showing gain characteristics, and FIG. 8 is a diagram showing the configuration of a transceiver to which the present invention is applied. . S-3...Ten line, T1~Tn...transit, n A□~An...coupler, DB...transmission line, 1...
・Coupler, 2...driver, 6...receiving amplifier,
4... Discriminator, 10... Constant current source, Ro, Re,
R□...Resistor, C...Capacitor, Q□, Q2...
・Transistor, 2nd piece ・Equalization circuit. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. Vee Fig. 7↑ Fig. 8 ee
Claims (2)
られるものであって、トランジスタ2個を用いだ差動増
幅器の各トランジスタのエミッタ間に伝送線路の高周波
領域でのゲインの低下を補償するための等化回路を具備
したことを特徴とするパスレシーバ用増幅器。(1) This is used in the path receiver of the data way system, and uses two transistors to perform equalization between the emitters of each transistor of the differential amplifier to compensate for the decrease in gain in the high frequency region of the transmission line. A path receiver amplifier characterized by comprising a circuit.
回路を用いたことを特徴とする特許請求の範囲第1項記
載のパスレシーバ用増幅器。(2) The path receiver amplifier according to claim 1, wherein a series circuit of a resistor and a capacitor is used as the equalization circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6313383A JPS59188259A (en) | 1983-04-11 | 1983-04-11 | Amplifier for bus receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6313383A JPS59188259A (en) | 1983-04-11 | 1983-04-11 | Amplifier for bus receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59188259A true JPS59188259A (en) | 1984-10-25 |
Family
ID=13220461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6313383A Pending JPS59188259A (en) | 1983-04-11 | 1983-04-11 | Amplifier for bus receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59188259A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016054452A (en) * | 2014-09-04 | 2016-04-14 | 住友電気工業株式会社 | Optical modulator driving circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5223241A (en) * | 1975-08-15 | 1977-02-22 | Fujitsu Ltd | Frequency compensation system |
JPS52116156A (en) * | 1976-03-26 | 1977-09-29 | Iwatsu Electric Co Ltd | Wide-band amplifier circuit |
JPS5379309A (en) * | 1976-12-23 | 1978-07-13 | Nec Corp | Unit suitable for multi-branching data transmission line |
JPS54115010A (en) * | 1978-02-28 | 1979-09-07 | Fujitsu Ltd | Communication system |
-
1983
- 1983-04-11 JP JP6313383A patent/JPS59188259A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5223241A (en) * | 1975-08-15 | 1977-02-22 | Fujitsu Ltd | Frequency compensation system |
JPS52116156A (en) * | 1976-03-26 | 1977-09-29 | Iwatsu Electric Co Ltd | Wide-band amplifier circuit |
JPS5379309A (en) * | 1976-12-23 | 1978-07-13 | Nec Corp | Unit suitable for multi-branching data transmission line |
JPS54115010A (en) * | 1978-02-28 | 1979-09-07 | Fujitsu Ltd | Communication system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016054452A (en) * | 2014-09-04 | 2016-04-14 | 住友電気工業株式会社 | Optical modulator driving circuit |
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