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JPS59181926A - Synchronizing system of inverter - Google Patents

Synchronizing system of inverter

Info

Publication number
JPS59181926A
JPS59181926A JP58054699A JP5469983A JPS59181926A JP S59181926 A JPS59181926 A JP S59181926A JP 58054699 A JP58054699 A JP 58054699A JP 5469983 A JP5469983 A JP 5469983A JP S59181926 A JPS59181926 A JP S59181926A
Authority
JP
Japan
Prior art keywords
phase
inverter
voltage
output
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58054699A
Other languages
Japanese (ja)
Inventor
渋谷 忠士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP58054699A priority Critical patent/JPS59181926A/en
Publication of JPS59181926A publication Critical patent/JPS59181926A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stand-By Power Supply Arrangements (AREA)
  • Supply And Distribution Of Alternating Current (AREA)
  • Inverter Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は負荷への給電にインバータと商用電源と全瞬時
並列運転で切換える電源設備において、インバータ出力
を商用電源に同期させるための同期方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization method for synchronizing an inverter output with a commercial power source in a power supply facility that switches an inverter and a commercial power source in full-instantaneous parallel operation to supply power to a load.

インバータと商用電源を切換え不のに、インバータと商
用電源(ライン)の電圧9周波数を合せ切換器をランプ
させて一瞬電源を並列にする瞬時並列運転とする制御方
式において、第1図に示すインバータの同期制御では位
相合せ制御を難しくする。同図において、インバータ主
回路/はその直流側又はゲートノールス幅制御で出方電
圧制御され、出力周波数と位相はゲート制御によって行
なわれる。このゲート制御はライン電圧V。とインバー
タ出力電圧V1を夫々電圧検出器2.3で検出され、こ
の検出電圧の位相差全位相差検出器lで対応する電圧信
号として検出され、この検出電圧は位相設定器Sの設定
値が減算されて増幅器6で増幅される。増幅器乙の出力
は電圧制御発振器7によって対応する周波数信号に変換
されてゲート回路どの周波数・位相制御入力にされ、ゲ
ート回路どの出力によってインバータ主回路/の各相ス
イッチ素子のオン・オフ制御がなされる。同期投入制御
回路9はラインからインバータへの切換指令が与えられ
た後、増幅器tの出力を監視し、該出力が零に達したと
きすなわち設定器Sに設定する範囲までラインとインバ
ータ出力位相が合ったときに切換器10□f!:10L
に並列投入させ、その後負荷をインバータ側に移行する
に要する時間後に切換器lOL  を解離させる。
In a control method that performs instantaneous parallel operation by matching the 9 voltage frequencies of the inverter and commercial power supply (line) and turning on the switch to momentarily parallel the power supplies without switching between the inverter and the commercial power supply, the inverter shown in Figure 1 Synchronous control makes phase matching control difficult. In the figure, the output voltage of the inverter main circuit / is controlled by its direct current side or gate Norse width control, and the output frequency and phase are controlled by gate control. This gate control is based on the line voltage V. and inverter output voltage V1 are respectively detected by the voltage detector 2.3, and the phase difference between the detected voltages is detected as a corresponding voltage signal by the total phase difference detector l. It is subtracted and amplified by an amplifier 6. The output of the amplifier B is converted into a corresponding frequency signal by the voltage controlled oscillator 7 and input to the gate circuit for frequency and phase control, and the output of the gate circuit controls the on/off of each phase switching element of the inverter main circuit. Ru. After receiving a switching command from the line to the inverter, the synchronization control circuit 9 monitors the output of the amplifier t, and when the output reaches zero, that is, the line and inverter output phases are adjusted to the range set in the setting device S. When it matches, switch 10□f! :10L
are connected in parallel, and after the time required to transfer the load to the inverter side, the switch lOL is disconnected.

しかし、この従来の同期方式では、切換器10L910
、  がその切換え時に、ランプしたとき、電圧検出器
2,3の横用点が同じになってその位相差量が零となり
、位相差検出器弘による位相合わせ制御ができなくなる
。これ全解決する手段として、有効電力と無効電力を検
出しラインとインバータ間の横流制御音する方法がある
が、この場合には制御回路が複雑と々るし信頼性の低下
並びにコストアンプとなる欠点があった。
However, in this conventional synchronization method, the switch 10L910
When , ramps at the time of switching, the horizontal points of voltage detectors 2 and 3 become the same and the amount of phase difference becomes zero, making it impossible to control the phase alignment by the phase difference detector. One way to solve all of this is to detect the active power and reactive power and control the cross current between the line and the inverter, but in this case the control circuit is complicated, reducing reliability and increasing cost. There were drawbacks.

本発明は電圧制御増幅器出力とライン電圧との同期を取
ることによシ、切換器のランプにも位相差検出を可能に
して確実、容易な位相制御ができるようにした同期方式
を提供することを目的とする。
The present invention provides a synchronization method that enables reliable and easy phase control by synchronizing the output of a voltage control amplifier with the line voltage and detecting a phase difference even in the lamp of a switching device. With the goal.

第2図は本発明の一実施例を示す単相インバータ回路図
である。同図において、第1囚と同じものあるいは同じ
機能を有するものは同一符号で示す。第2図において、
電圧制御発振器7の出力は分周回路/lによって適当な
周波数まで分周され、この分周出力は単安定マルチバイ
ブレータノコによってタイミング信号として取出されて
位相差検出器弘の一方の位相比較入力にされる。位相差
検出器lの他方の入力は電圧検出器コによってライン電
圧位相信号が与えられる。
FIG. 2 is a single-phase inverter circuit diagram showing one embodiment of the present invention. In the figure, the same parts or parts having the same functions as the first prisoner are indicated by the same reference numerals. In Figure 2,
The output of the voltage controlled oscillator 7 is frequency-divided by a frequency divider circuit /l to an appropriate frequency, and this frequency-divided output is taken out as a timing signal by a monostable multivibrator saw and sent to one phase comparison input of the phase difference detector Hiroshi. be done. The other input of the phase difference detector l is provided with a line voltage phase signal by a voltage detector l.

一方、分周回路/lの出力は三角波発生回路13の位相
9周波数制御入力にされ、三角波発生回路13の一定振
幅三角波出力は比較器lダの比較基準にされる。インバ
ータ/の出力はその電圧V、が電圧検出器/3で検出さ
れ、この検出電圧はインバータ出力電圧設定器/6の設
定値と突合わされて電圧制御増幅器/7による演算がな
され、該増幅器/7の出力が比較器lダの比較入力にさ
れる。比較器/ダは三角波発生回路/3の三角波信号と
電圧制御増幅器17の電圧制御出力とをレベル比較する
ことによってインバータ出力電圧2周波数9位相をライ
ンのそれらに合わせるパルス信号を得る。このノくルス
信号はゲート回路どのゲート制御入力とされ、該ゲート
回路ざによってインバータlの各スイッチのゲートパル
スとして分配増幅される。
On the other hand, the output of the frequency divider circuit /l is used as the phase 9 frequency control input of the triangular wave generating circuit 13, and the constant amplitude triangular wave output of the triangular wave generating circuit 13 is used as a comparison reference of the comparator lda. The voltage V of the output of the inverter / is detected by the voltage detector /3, this detected voltage is compared with the set value of the inverter output voltage setter /6, and calculation is performed by the voltage control amplifier /7. The output of 7 is used as a comparison input of comparator Lda. The comparator/da compares the levels of the triangular wave signal of the triangular wave generating circuit/3 and the voltage control output of the voltage control amplifier 17 to obtain a pulse signal that matches the inverter output voltage 2 frequency 9 phase with those of the line. This Norculus signal is input to the gate control of each gate circuit, and is distributed and amplified by the gate circuit as a gate pulse for each switch of the inverter I.

このように、ライン側とインノく一夕側との位相合わせ
のためのPLL回路として、ライン電圧信号とインバー
タの位相2周波数制御信号とを位相比較することによシ
、切換器10L、 IO,の投入状態に無関係に位相差
比較が可能となシ、安定した位相制御すなわち確実な同
期投入全可能にする。
In this way, as a PLL circuit for phase matching between the line side and the inverter side, the switching device 10L, IO, It is possible to compare the phase difference regardless of the closing state of the phase shifter, thereby making it possible to perform stable phase control, that is, reliable synchronization.

第3図は第2図における各部波形囚を示す。電圧制御発
振器7の出力に対して分周間#8//には硲分局出力を
得、この分周出力の立上りタイミングテ単安定マルチバ
イブレータ72に位相論理出力を得、この出力とライン
電圧信号の零クロス点信号とを位相差検出器弘で位相比
較し、この位相比較結果に応じて電圧制御発振器7の出
力位相全制御するPLL回路に構成される。とのアLL
回路テはインバータ出力電圧位相を直接に検出した位相
比較にならないため、切換器ioL、io、が瞬時並列
にあっても位相差検出器グの肉入力が四じ信号味になる
ことがなく、確実な位相比較ひいてはインバータ出力位
相合わせ全可能にする。なお、m3図における三角波出
力はインバータの電圧制御系を含めたゲート制御に使用
され、インバータのパルス幅制御による出力電圧制御も
一括に行なわれ、比較器11の出力に対してU、X、V
、Yのゲート信号が作!lll出され、インバータ出力
は位相論理出力の中間点に合わされる。
FIG. 3 shows waveforms of various parts in FIG. 2. For the output of the voltage controlled oscillator 7, a divided output is obtained between frequency division #8//, and a phase logic output is obtained from the rise timing of this frequency divided output to the monostable multivibrator 72, and this output and the line voltage signal are A phase difference detector Hiroshi performs a phase comparison with the zero cross point signal of , and the PLL circuit is configured to completely control the output phase of the voltage controlled oscillator 7 according to the result of this phase comparison. TonoALL
Since the circuit TE does not directly detect the inverter output voltage phase for phase comparison, even if the switching devices IOL and IO are instantaneously parallel, the input to the phase difference detector GU will not become like a four-signal signal. This enables reliable phase comparison and, in turn, inverter output phase matching. Note that the triangular wave output in the m3 diagram is used for gate control including the voltage control system of the inverter, and the output voltage is also controlled all at once by controlling the inverter's pulse width.
, Y gate signal is created! llll output, and the inverter output is aligned to the midpoint of the phase logic output.

以上のとおり、本発明は、インバータの位相。As described above, the present invention relates to the inverter phase.

周波数制御信号の位相タイミング信号とライン電圧信号
との位相比較によってインバータ出力位相。
The inverter output phase is determined by comparing the phase of the frequency control signal phase timing signal and the line voltage signal.

周波数制御信号を得るため、瞬時並列運転のインバータ
においても位相制御不能に陥ることがなくなり、確実な
同期切換えができる効果がある。
Since the frequency control signal is obtained, phase control is prevented from becoming impossible even in instantaneous parallel operation inverters, and there is an effect that reliable synchronous switching can be performed.

【図面の簡単な説明】 第1図は従来の同期方式全示す回路図、第2図は本発明
の一実施例を示す回路図、第3図は第2図の各部波形図
である。 /・・・インバータ主回路、λ・・・電圧検出器、グ・
・・位相差検出器、S・・・位相設定器、6・・・増幅
器、7・・・電圧制御発振器、!・・・ゲート回路、7
・・・同期役人制御回路、 10L、10.・・・切換
器、/ハ・・分周回路、/2−−− 単安定マルチバイ
ブレータ、/3・・・三角波発生回路、/弘・・・比較
器、 /3・・・電圧検出器、/A・・・電圧設定器、
/7・・・電圧制御増幅器。 第2図 第3図
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing the entire conventional synchronization system, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram of each part of FIG. 2. /... Inverter main circuit, λ... Voltage detector, G...
...Phase difference detector, S...Phase setter, 6...Amplifier, 7...Voltage controlled oscillator,! ...gate circuit, 7
...Synchronous official control circuit, 10L, 10. ...Switcher, /C...Frequency divider, /2--- Monostable multivibrator, /3...Triangular wave generation circuit, /Hiroshi...Comparator, /3...Voltage detector, /A...voltage setting device,
/7...Voltage control amplifier. Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 商用電源とインバータとを瞬時並列運転で切換えて負荷
に給電する電源設備において、上記商用電源の電圧位相
とインバータの位相制御信号の位相との位相差比較によ
って該位相制御信号の位相及び周波数を制御するPLL
回路を備え、上記位相差比較結果が所定範囲内にあると
きに商用電源とインバータと全瞬時並列運転して該イン
バータ側への移行を行なうことを特徴とするインバータ
の同期方式。
In power supply equipment that supplies power to a load by instantaneously switching between a commercial power source and an inverter in parallel operation, the phase and frequency of the phase control signal are controlled by comparing the phase difference between the voltage phase of the commercial power source and the phase of the inverter's phase control signal. PLL to do
An inverter synchronization method, comprising: a circuit, and when the phase difference comparison result is within a predetermined range, the commercial power source and the inverter are operated in parallel at all instants to transfer to the inverter side.
JP58054699A 1983-03-30 1983-03-30 Synchronizing system of inverter Pending JPS59181926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58054699A JPS59181926A (en) 1983-03-30 1983-03-30 Synchronizing system of inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58054699A JPS59181926A (en) 1983-03-30 1983-03-30 Synchronizing system of inverter

Publications (1)

Publication Number Publication Date
JPS59181926A true JPS59181926A (en) 1984-10-16

Family

ID=12978048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58054699A Pending JPS59181926A (en) 1983-03-30 1983-03-30 Synchronizing system of inverter

Country Status (1)

Country Link
JP (1) JPS59181926A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61173636A (en) * 1984-12-18 1986-08-05 三菱電機株式会社 Power source unit
US11539215B2 (en) 2021-03-16 2022-12-27 Kabushiki Kaisha Toshiba Voltage control inverter, power source apparatus, and control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61173636A (en) * 1984-12-18 1986-08-05 三菱電機株式会社 Power source unit
US11539215B2 (en) 2021-03-16 2022-12-27 Kabushiki Kaisha Toshiba Voltage control inverter, power source apparatus, and control method

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