JPS59178763U - stain removal circuit - Google Patents
stain removal circuitInfo
- Publication number
- JPS59178763U JPS59178763U JP6461584U JP6461584U JPS59178763U JP S59178763 U JPS59178763 U JP S59178763U JP 6461584 U JP6461584 U JP 6461584U JP 6461584 U JP6461584 U JP 6461584U JP S59178763 U JPS59178763 U JP S59178763U
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- parallel
- output
- input
- out shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 102100027674 CTD small phosphatase-like protein Human genes 0.000 description 1
- 101000725950 Homo sapiens CTD small phosphatase-like protein Proteins 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Character Input (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は認識の対象となる文字と不要なシミの関係を説
明する図、第２図は従来のシミ除去方法を説明する説明
図、第３図は本考案の実施例のシフトレジスタ部分を示
す回路図、第４図ａ、 ｂは同判定回路部分を示すブ
ロック図および同期信号の説明図、第５図は検査区域の
説明図、第６図および第７図は検査区域の移動を説明す
る図である。
図中、ＳＲ１〜５ＲＩＱはシフトレジスタ、ＰＳＲｌ〜
ＰＳＲＩＱはパラレルアウトシフトレジスタ、５Ｒ１１
〜５ＲＩＱＮは入、出力端子、６はアンド回路、７はノ
ット回路、１０はアンド回路を示す。Figure 1 is a diagram explaining the relationship between characters to be recognized and unnecessary stains, Figure 2 is an explanatory diagram explaining the conventional stain removal method, and Figure 3 is a diagram showing the shift register part of the embodiment of the present invention. Figures 4a and 4b are block diagrams showing the determination circuit portion and explanatory diagrams of synchronizing signals, Figure 5 is an explanatory diagram of the inspection area, and Figures 6 and 7 are illustrations of movement of the inspection area. This is a diagram. In the figure, SR1~5RIQ are shift registers, PSR1~
PSRIQ is a parallel out shift register, 5R11
~5RIQN indicates input and output terminals, 6 indicates an AND circuit, 7 indicates a NOT circuit, and 10 indicates an AND circuit.
Claims (1)
ット数１のビデオ信号の一部を記憶する、直列接続され
たｎ段のレジスタを設け、各段のレジスタの一部１゜ビ
ットはパラレルアウトシフトレジスタにまた残りの１−
１□ビツトはシフトレジスタにし、また該パラレルアウ
トシフトレジスタの入出力を利用して取出した、該パラ
レルアウトシフトレジスタが作るｎライン１２ビツト相
当の大きさの前記画面上の検査区域の周辺のビデオ信号
を入力されるゲート回路を設け、更に該検査区域周辺の
ビデオ信号がすべて非文字レベルであるとき出力される
該ゲート回路の出力を前記パラレルアウトシフトレジス
タのリセット端子に入力して該パラレルアウトシフトレ
ジスタの内容を１本のりセット信号によりすべて非文字
レベルにするリセット回路とを有することを特徴とする
シミ除去回路。There are n stages of registers connected in series to store a portion of the video signal with the number of lines N1 representing the screen of characters to be recognized and the number of bits of each line being 1, and a part of the 1° bit of the register in each stage is stored in parallel. The remaining 1- is added to the out shift register.
The 1□ bit is made into a shift register, and the input/output of the parallel out shift register is used to extract the video of the area around the inspection area on the screen, which is equivalent to the n-line 12 bits produced by the parallel out shift register. A gate circuit to which a signal is input is provided, and the output of the gate circuit, which is output when all the video signals around the inspection area are at a non-character level, is input to the reset terminal of the parallel out shift register to control the parallel output. 1. A stain removal circuit comprising a reset circuit which sets all the contents of the shift register to a non-character level using a single reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6461584U JPS59178763U (en) | 1984-05-01 | 1984-05-01 | stain removal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6461584U JPS59178763U (en) | 1984-05-01 | 1984-05-01 | stain removal circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59178763U true JPS59178763U (en) | 1984-11-29 |
Family
ID=30194799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6461584U Pending JPS59178763U (en) | 1984-05-01 | 1984-05-01 | stain removal circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59178763U (en) |
-
1984
- 1984-05-01 JP JP6461584U patent/JPS59178763U/en active Pending
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