JPS59178091A - Character signal conversion circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a character signal conversion circuit for converting a character signal into an NTSC signal.

[Technical background of the invention and its problems]

In recent years, with the spread of personal computers, color character signals (R,
G and H signals) are often supplied to a general telephoto receiver for display. However,
Television receivers use the NTSC system, which limits the signal band to 4.5 MHz or less, so high character signals with a bandwidth of 7 MHz or more can be directly supplied to the television receiver. It is impossible to display it as such.

Conventionally, therefore, an NTSC conversion circuit as shown in FIG. 1, for example, is provided to convert character signals.

That is, R output from the personal computer 1
The three signals R8°GS and BS of , G, and B are first led to a delay circuit 2ay2bt2c, where their pixel widths are expanded in the horizontal and vertical directions, respectively, and then the signals are converted by a signal conversion circuit 3. Each signal R8' l BS' j YS of RY, BY, and Y is created. 1 Among the above ordinary signals, R-Y and B-Y signals R8',
BS' is passed through low-pass filters 4a and 4b each having a cutoff frequency of 500 kHz, and then sent to a balanced modulation circuit 5a.

5b, the circuits 5a and 5b amplitude-modulate the 3.58 MHz sine wave, the modulated outputs are synthesized in the synthesis circuit 6, and then the superimposition circuit 7 converts the synthesized output from the signal conversion circuit 3. The output is superimposed on the luminance signal YS' and supplied to a television receiver (not shown).

However, this conventional conversion circuit has the following drawbacks.

Medium The pixel widths of character signals R8, GB, and BS are expanded by delay circuits 2 & e2b + 26 to make them compatible with the NTSC system, so the display resolution deteriorates and fine characters cannot be clearly seen. It can be a loaf.

(ii) Character signals generally have higher frequency components in the vertical direction than frequency components in the horizontal direction, so even if the pixel widths in each of the horizontal and vertical directions are expanded, the character signals are still passed through the low-pass filters 4a and 4b. As a result, the signal level in the vertical direction becomes significantly lower than that in the horizontal direction. As a result, the characters become extremely unnatural, with thin vertical lines and only emphasized horizontal lines. This is extremely undesirable, especially when displaying a graph or the like, since the vertical lines are hardly illuminated.

On the other hand, in order to emphasize the vertical direction, the character signal is
It has also been proposed to pass a delay line through the circuit, but such circuits do not have the same effect in the case of characters that are not continuous in the vertical direction, such as dots, and it is still not possible to obtain a clear display. It was powerful.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a character signal conversion circuit that can display a character with uniform brightness and clarity regardless of the direction of the vertical and horizontal luminescent lines or the form of the character.

[Summary of the invention]

In order to achieve the above object, the present invention expands the pixel width of a character signal to be similar to that of an NTSC signal, and for each pixel of the character signal with the expanded pixel width, at least 1 located on either side
Extract a pixel string containing one or more pixels and configure this pixel string! The pixel arrangement state is determined and the signal level of the pixel is varied according to the determination result. [Embodiment of the Invention] FIG. 2 shows a character signal conversion circuit in an embodiment of the present invention. This is a circuit configuration diagram of a signal level control circuit which is a main part of the circuit, and is provided in place of the delay circuits 2a, 2b, and 2c in FIG. 1. Note that a signal level control circuit is provided for each of the R9G, B signals R8, GS, and BS, but only one of them is shown in FIG. 2 because the circuits have the same configuration as the general circuits.

This signal level control circuit controls character signals (for example, R
Delay circuit 11 that expands the pixel width of signal R8) in the horizontal direction
Then, the delayed character signal RDS output from the delay circuit 11 is shifted pixel by pixel in synchronization with the clock signal CK, and a 5-bit shift register 12 is input, and the parallel output of this shift register 12 is determined to be supplied. It consists of a circuit 13, a latch circuit 14 that latches the judgment output of this judgment circuit 13, and a signal level variable circuit 15.

The judgment circuit 13 is composed of a read-on-I-no memory, and guides the parallel output from the shift register 12 as an address signal, and outputs the judgment value stored in the storage area designated by this address signal to the corresponding terminal. D1v
D2 y Ds * This is what is output from D4.

Here, the storage contents of the ROM are set as shown in the following table.

That is, the determination circuit 13 focuses on the pixel A3 located at the center of the 5-bit pixel column, and when this pixel A3 is at '0'' level, the output terminal DL P D2 tD3 * D
No judgment signal is issued from any of the four, while the image purple A3 is “
At the 1″ level, each pixel A1 v located before and after it
A4 and A41 The scale is determined according to the alignment state of the pixels of the A, Nod, and 1# levels, and the first shift is output from the corresponding output terminal DI + D2 t'Ds t D4. . Here, each of the above judgment signals is output as a judgment signal of ``1'' level from DI when making a pixel brighter, from D2 when making a pixel a little brighter, from D3 when making a pixel a little darker, and from D4 when making a pixel darker. ing.

On the other hand, the signal level variable circuit 15 has a transistor Tr to which a collector voltage of +10'V and an emitter voltage of -10V are respectively applied. The output A3 is supplied via an open collector type logic circuit 16.

Then, a reference output voltage of 5V is applied to the pace of the transistor Tr through the resistor R, and the RO
M Z 3 output terminal D1 y D2 + D3 +D
The judgment signal ('°1'' level) output from
4+R3+ are applied via R2, respectively. Here, each of the above resistances R5t R4y R11s R2 is R
The resistance value is determined so that 2<R3<R4<R5. Therefore, when the pixel at the center position of the shift register 12 becomes "1#," the signal level variable circuit 15 connects the resistor Ri (any one of Rz=Rs) to which the determination signal from the ROM 13 is supplied. The output determined by the resistor R1, that is, drives the transistor Tr to send out an output O8 having a signal level corresponding to the output.

Since the configuration is similar to that of jin, personal computer 1
The character signals R3°GS and BS output from
After the pixel width is expanded by the delay circuit 11, the signals are sequentially shifted into the shift register 12 and outputted in parallel as a 5-bit pixel column for each shift. As a result, the determination circuit (ROM) 13 determines the arrangement state of the "1# level" pixels in the pixel row each time the pixel row is input.
The determination signal is output.

For example, when the delayed character signal RDS as shown in FIG. 3 is input to the shift register 12, the shift register 1
When the pixel ``0 level'' is shifted to the center position of ``2'' (corresponding to As), the open collector of the logic circuit 16 is turned on, and the ``1'' level judgment signal is not output from the judgment circuit 13. , the output O8 of the transistor Tr reaches the ``'0# level'' as shown in FIG.

On the other hand, when a pixel of "1 level" is shifted to the center position of the shift register I2, the open collector of the logic circuit 16 turns off.
Since the pixel column 0101 is supplied, the judgment circuit 13 outputs a judgment signal of the ``1'' level from the output terminal D2 according to the above table.As a result, only the resistor R4 is grounded by the inverter 2. , the transistor Tr is driven by a bias voltage of 0. Therefore, the emitter outputs an output O8 ranging from signal level L2, as shown in FIG. 3, corresponding to the above bias.

Similarly, each time a pixel shift operation is performed in the shift register 12 and a pixel at the "1# level" is shifted to the center position, the pace of the transistor Tr is adjusted according to the arrangement state of the pixels at the "1" level at that time. Resistance R2y Rs y
R4s Rs is selected and the signal level defined by this selected pace resistance L41 Lly Ll e
The output OS of Ll is output as shown in FIG.

The character signal whose signal level has been variably controlled is supplied to the signal conversion circuit 3 shown in FIG. 1, and finally outputted from the superimposition circuit 7 as an NTSC signal.

In this way, in this embodiment, the signal level of each pixel is varied according to the arrangement of pixels at the '1# level, so when such a signal is displayed as a character, the horizontal line In the part where the pixels of the bell are continuous, it is possible to reduce the effect of expanding the pixel width by delay circuit 1 and prevent it from becoming extremely bright. In the case of characters consisting of a single pixel, such as a vertical line or a period, it is possible to display them brightly and clearly by emphasizing the signal level.

Therefore, clear display can always be performed regardless of the vertical and horizontal directions and regardless of the type of characters. Furthermore, in this embodiment, since a ROM is used as the determination circuit, it is possible to control various signal levels simply by rewriting the contents of the ROM, and as a result, it is possible to easily respond to the state of the pixel. can.

Note that the present invention is not limited to the above embodiments.

For example, the signal level of each pixel may be controlled by storing the character signal in a frame memory or line memory, and using a microprocessor or the like to read the character signal bit by bit and perform calculations.

In addition, it is not always necessary to extract the previous and next pixels, but either the previous or subsequent pixels may be extracted. For example, if the previous pixel is at a predetermined level or higher and a consecutive pixel is also at a predetermined level or higher, the level of the subsequent pixel may be lowered. Even simple control can be quite effective. In addition, the number of bits of a pixel string, the determination method, etc. can be modified in various ways without departing from the gist of the present invention.

〔Effect of the invention〕

As described in detail above, the present invention extracts, for each pixel of a delayed character signal, a pixel string including each pixel located before or after this pixel, and selects a specific image among the pixels constituting this pixel string. The arrangement state of the pixels at the = level is determined, and the signal level of the pixels is varied according to the result of this determination.

Therefore, according to the present invention, it is possible to provide a character signal conversion circuit that can display a character with uniform brightness and clarity regardless of the direction of the vertical and horizontal bright lines or the form of the character.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional character signal conversion circuit, FIG. 2 is a circuit diagram showing the main part configuration of a character signal conversion circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional character signal conversion circuit. FIG. 3 is a signal waveform diagram used to explain the operation of the circuit. 11... Delay circuit, 12... Shift resistor, 13
... Judgment circuit (ROM), 14 ... Latch circuit, 1
5... Signal level variable circuit, 16... Logic circuit. Applicant's agent Takehiko Suzue, patent attorney

Claims (1)

[Claims] In a character signal conversion circuit that converts a character signal to an NTSC signal, each pixel of the character signal is
means for enlarging the time width to a time width compatible with the C signal; and a pixel row including one or more pixels located at least either before or after each pixel of the character signal output from the means. and means for determining the arrangement state of pixels having a specific signal level among the pixels constituting the pixel array, and means for varying the signal level of the pixel in accordance with the determination result by the means. A character signal conversion circuit characterized by: