JPS59177934A - Pattern formation of semiconductor device - Google Patents

Abstract

PURPOSE:To perform pattern formation in order to deposited layers of the plural number without using a resist by a method wherein radiation ray is projected selectively to a second deposited layer formed on a first deposited layer to form a pattern utilizing the difference of etching speeds, and etching of the first deposited layer is performed using the patterned layer thereof as a mask. CONSTITUTION:A first deposited layer 5 of wiring metal layer to be formed with a pattern is formed on a substrate 4. Then a silicon layer is formed as a second deposited layer 6 thereon. Scanning is performed with radiation rays 7 of a laser beam or an electron beam, etc. in accordance with the prescribed wiring pattern to the second deposited layer 6 thereof to irradiate selectively the deposited layer 6. Largeness of the silicon grains of the part 8 received irradiation of radiation is increased as compared with the part 9 not received irradiation to change crystallizability, and the etching speed becomes extremely slow. As the result of the etching process, the second deposited layer part 9 not received irradiation is removed completely, and the first deposited layer 5 of metal layer existing thereunder is etched using the second deposited layer part 8 as a mask to form accurately a metal wiring pattern 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for forming a pattern in a semiconductor device that is not used for renost.

(Prior Art) In general, a so-called masking technique is used in manufacturing semiconductor devices9. This masking technique uses a renost, which forms a pattern on the resist, and uses the patterned resist as a mask to perform etching, doping, or other processes on the underlying layer, such as a semiconductor layer, an insulating layer, or a metal layer. Processes necessary for manufacturing conductor devices are performed as required.

FIGS. 1A to 1D are process diagrams showing a typical example of a conventional pattern forming method for a semiconductor device, and in particular, the process of forming a pattern (hereinafter simply referred to as patterning) of a wiring metal formed on a semiconductor or insulating film. An example of the process is shown.

According to this conventional patterning method, first, as shown in FIG. 1A, a deposited layer 2, that is, a wiring metal layer, is provided on a base layer 1, that is, a semiconductor layer or an insulating layer.

When this wiring metal layer 2 is slightly turned, as shown in FIG.
A resist 3 is applied on this metal layer 2 as shown in FIG. The resist 3 is then selectively polymerized by irradiating the resist 3 with radiation, for example ultraviolet light, through a glass mask. Thereafter, as shown in FIG. 1C, this resist 3 is developed to form a pattern.

Next, as shown in Figure f1, the patterned resist 3 is used as a mask to etch the underlying deposited metal layer 2 to form a wiring pattern.

In this conventional patterning method, a resist is applied to the deposited layer, and the deposited layer is etched using the resist as a mask to form the pattern, so side etching occurs due to the adhesion between the deposited layer and the resist. . This side etching causes variations in the effective date length when, for example, source and drain regions are subsequently formed in the semiconductor layer.

Furthermore, in the process of patterning a resistor using ultraviolet rays, a difference in dimension conversion from the glass mask pattern occurs due to light diffraction, multiple reflection effects, etc., making it impossible to perform precise patterning.

Furthermore, since the resist is an organic substance, the method using a resist requires sufficient cleaning before proceeding to the subsequent steps, which has the drawback of requiring an extra processing step.

(Object of the Invention) The object of the present invention is to form a pattern by sequentially etching a plurality of deposited layers formed on a base layer without using a resist, in order to eliminate the drawbacks of the conventional turning method described above. An object of the present invention is to provide a pattern forming method for a semiconductor device.

(Structure of the Invention) In order to achieve this object, according to the method for patterning a semiconductor device of the present invention, a base layer such as a semiconductor layer or an insulating layer, for example, a semiconductor thin film to be formed in two turns,
forming a first deposited layer, such as an insulating film or a metal thin film, and forming a second deposited layer, such as a polycrystalline or amorphous semiconductor thin film or a metal thin film, on the first deposited layer; The second deposited layer is selectively irradiated with radiation such as a laser beam or an electron beam, and the second deposited layer portion that has been irradiated with this radiation and the second deposited layer portion that has not been irradiated are separated. Utilizing the difference in etching speed, the entire second deposited layer is etched to form a no-e turn, and the first deposited layer described above is etched using the patterned second deposited layer as a mask. Characterized by molding.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 2A to 2E are process diagrams for explaining an embodiment of the pattern forming method of the present invention.

A method for patterning wiring metal on a base layer such as a semiconductor layer or an insulating layer will be explained using FIG. First, the second
As shown in FIG. A, a first deposited layer 5, which is a wiring metal layer to be patterned, is formed on a base layer 4 of a semiconductor layer or an insulating layer. Next, as shown in FIG. 2B, a polycrystalline or amorphous silicon layer is formed on the first deposited layer 5 as a second deposited layer 6 by CVD.
D or by vapor deposition. Subsequently, as shown in FIG. 2C, this second deposited layer 6 is scanned with radiation 7 such as a laser beam or an electron beam according to a predetermined wiring pattern to remove the deposited layer 6.
selectively irradiate. As a result, the size of the silicon particles in the portion 8 of the second deposited layer 6 that is irradiated with radiation increases compared to the portion 9 that is not irradiated (5) and changes to crystallinity. Therefore, the etching rate of the former silicon layer portion 8 is much lower than that of the latter silicon layer portion 9.

Next, as shown in the second diagram, the second deposited layer 6 after irradiation
A wet or dry etching method is applied to the film, and the etching process is performed using the above-mentioned difference in etching speed. As a result, the non-irradiated second deposited layer portion 9 is completely removed, while the irradiated second deposited layer portion 8 remains only etched over a portion of its thickness. The second deposited layer portion 8 patterned in this way
Using this as a mask, the first deposited layer 5, which is the metal layer existing below, is etched to accurately form a slight turn of the first deposited layer, that is, a metal wiring pattern 10f.

The state is shown in the second diagram.

According to the method of the present invention described above, the second deposited layer, which is a polycrystalline or amorphous silicon layer, is irradiated with an irradiation density of about 0.5 to 10 J/
When irradiated with a laser beam of about Crn2, the size of the particles immediately after deposition was several tens of times to several hundred times (6), but after irradiation with I/- laser light, the size of the particles was several tens of times to several tens of tens of times. μm
Enlarge the tank. As a result, in the next etching process, for example, when dry etching with CF4+50%02 is performed, the etching speed of the irradiated silicon layer portion is 1/10 to 100 minutes of the etching speed of the silicon layer portion that was previously irradiated. The process level is reduced to . Therefore, if the thickness of the polycrystalline or amorphous silicon layer, which is the second deposited layer, is set accurately in advance, taking into account the reduction during subsequent etching,... Turning can be controlled accurately. When an electron beam is used instead of a laser beam as the radiation, the same result as described above can be obtained by using an electron beam with the same energy as the l/-ther beam.

In the above-mentioned embodiment, a method was described in which turning of wiring metal is performed using a polycrystalline or amorphous silicon layer (also referred to as a silicon thin film) as an entire mask.
The present invention is not limited to this, and the first deposited layer to be turn-formed can be any thin film that needs to be patterned in a semiconductor device, such as a semiconductor thin film or an insulating film. Further, the second deposited layer serving as the mask may be a polycrystalline or amorphous semiconductor layer or a metal thin film other than the above-mentioned silicon layer. In this case, different types of layers (thin films) are used for the first deposited layer and the second deposited layer, and when the first deposited layer is etched, the second deposited layer is not etched, or if it is etched, the second deposited layer is etched. It is better to use a combination with a slow etching speed.

(Effects of the Invention) As described above, in the present invention, instead of using a so-called resist, a polycrystalline or amorphous semiconductor layer is placed on the first deposited layer of the semiconductor thin film, insulating film, or metal thin film to be turned. or CVD using a metal thin film as a second deposited layer.
Alternatively, the second deposited layer may be formed by vapor deposition, selectively irradiated with radiation such as a laser beam or an electron beam, and then slightly turned, and then the patterned second deposited layer may be used as a mask to form a layer underneath the second deposited layer. Since the primary turning of the first deposited layer is performed, the adhesion between the first deposited layer, such as a wiring metal thin film, and the second deposited layer, such as a silicon layer, is extremely good. There is an advantage that etching can be substantially eliminated, and therefore the dimensional conversion difference with the mask can be predicted, allowing accurate and precise pattern formation.

In addition, since a resist is not used, the cleaning process that was conventionally required is not required, which simplifies the process and reduces the manufacturing cost accordingly.

[Brief explanation of the drawing]

FIG. 1 is a process diagram for explaining a conventional semiconductor device pattern forming method, particularly a wiring metal pattern forming method;
The figure is a process diagram for explaining one embodiment of the method for forming a pattern of a semiconductor device according to the present invention. 4... Base layer (or semiconductor layer or insulating layer), 5... First deposited layer (or semiconductor thin film, insulating film, or metal thin film), 6
... second deposited layer (or polycrystalline or amorphous semiconductor layer,
or metal thin film), 7... Radiation (or laser light or electron beam), 8... Second deposited layer portion irradiated with radiation, 9
. . . The second deposited layer (9) portion that was not irradiated with radiation, lO . . . Metal wiring pattern (or pattern of the first deposited layer). Patent Applicant Oki Electric Industry Co., Ltd. (10) Figure 1 Figure 2 Showa Year Month Date Commissioner of the Japan Patent Office 1. Indication of the case 1988 Patent Application No. 051515 2. Name of the invention Method for forming patterns of semiconductor devices 3 Relationship with the case of the person making the amendment Patent application Person's address (
Address: 105) 1-7-12 Toranomon, Minato-ku, Tokyo Name (029) 3 Shin@Ki Kogyo I Main Shikikai Neto Representative
Director and President Nankai Hashimoto 4, Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2 No. 6, Contents of the amendment As attached, 6, Contents of the amendment (1) Line 20 of page 5 of the specification and line 20 of page 6: “
Correct the phrase ``particles'' to ``particle size.'' (2) In the 16th line of page 6 of the same book, the phrase "shown in the second drawing" is corrected to "shown in the second drawing E." (3) In the third line of page 7 of the same book, the text "rCF4+50 section 02" is corrected to "rcF4+5%02". (2)

Claims (1)

[Claims] forming a first deposited layer to be patterned on the surface of the base layer, forming a second deposited layer on the first deposited layer, selectively irradiating the second deposited layer with radiation; The second deposited layer is etched by taking advantage of the difference in etching speed between the second deposited layer portion that has been irradiated with radiation and the second deposited layer portion that has not been irradiated to form a pattern. A method for forming a pattern in a semiconductor device, comprising etching the first deposited layer using the etched second deposited layer as a mask to form the pattern.