JPS59176984A - Reference signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a stable reference signal in synchronizing with a vertical and a horizontal signal by utilizing an equivalent pulse arrived after a prescribed period of a tail ridge part of the vertical synchronizing signal as the reference signal of the vertical signal. CONSTITUTION:A pulse signal Sh having the same phase as that of the equivalent pulse EQ is obtained at an output terminal of a count circuit 38 by providing the count circuit 38 having the capacity for counting a clock signal S1 up to the preset final count value for the first time when the equivalent pulse EQ is outputted from a horizontal synchronizing signal separating circuit 37. The phase of a signal Si obtained from the equivalent pulse EQ in this signal Sh and the phase of a signal Sj obtained from a memory 41 according to the count operation of a count circuit 22 are compared to shift the reset timing of the count circuit 22. Thus, this operation is repeated for several vertical scanning periods, resulting that the horizontal and vertical reference signals are synchronized with the horizontal and vertical synchronizing signals.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a reference signal that serves as a phase reference for a vertical synchronization signal or a horizontal synchronization signal in a video signal in, for example, a ghost signal removal system or a teletext receiving system. This invention relates to a reference signal generation circuit that generates a reference signal.

[Technical background of the invention]

As an example of a system for removing ghost signals generated in television broadcast signals, there is a system for removing ghost signals using a circuit within a television receiver. This system focuses on the fact that the vertical synchronization signal portion of the video signal becomes a step waveform due to the ghost signal, and attempts to detect the superimposed phase of the ghost signal using this Ste/Knob waveform. A reference signal that serves as a phase reference for reading the superimposed phase of this ghost signal must be generated in a state that is always accurately synchronized with the vertical synchronization signal in the video signal even if there are ghost signals or noise signals.

A conventional circuit for creating such a reference signal uses an automatic frequency control circuit (hereinafter referred to as AFC) with a phase-locked loop (PLL) configuration to generate a clock signal synchronized with a horizontal synchronization signal.
circuit) and divides the frequency to create a vertical reference signal. FIG. 1 is a circuit diagram showing the circuit configuration, in which a horizontal synchronization signal is separated from a video signal applied to a terminal 11 in a horizontal synchronization signal separation circuit 12, and a phase detection circuit 1
Supply to 3. The voltage controlled oscillation circuit (VCO) 14 oscillates at n times the horizontal scanning frequency (fH). The oscillation output signal of the voltage controlled oscillation circuit 14 is frequency-divided by n in the frequency dividing circuit 15, and is sent to the phase detection circuit 13 as a signal of frequency fH.
supplied to The phase detection circuit 13 compares the phases of both human input signals, and changes the oscillation output frequency of the voltage controlled oscillation circuit 140 based on the comparison result. The oscillation output signal of the voltage controlled oscillation circuit 14 is converted by the frequency dividing circuit 16 into a signal with a frequency of 2fH. This signal of frequency '21H is frequency-divided by 525 by the frequency dividing circuit 17 and converted into a signal of fH above the vertical scanning frequency. The frequency dividing operation of the frequency dividing circuits 25 to 17 is reset by the vertical synchronizing signal separated from the video signal (no. 4) in the vertical synchronizing signal separation circuit 18. A vertical reference signal that is phase-synchronized with is output).

[Problems with background technology]

However, the above configuration has the following problems.

The vertical reference signal output from the frequency dividing circuit 17 largely depends on the vertical synchronizing signal, and more specifically on the horizontal interval j to j signal. Therefore, if a video signal arrives that is not affected by ghost signals or other noise signals, there will be no problem, but if the video signal is affected by noise signals or other effects, there will be a phase shift or Jitter etc. will occur. This is because when a ghost signal or other noise signal occurs, the horizontal synchronization 4m signal separation circuit 12 separates the synchronization signal in the picture part or ghost signal in addition to the original horizontal synchronization signal, or The width of the signal changes. As a result, voltage controlled oscillation circuit 1
The oscillation output frequency of No. 4 is different from the original horizontal synchronization signal. As a result, the phase of the frequency-divided output signal of the frequency divider circuit 16 also differs from that of the original horizontal synchronization signal, causing a phase shift and jitter in the vertical reference signal output from the frequency divider circuit 17. This means that, for example, a ghost signal removal system cannot accurately detect the superimposed position of a ghost signal, and a teletext receiving system cannot accurately extract data from data packets. It turns out.

[Purpose of the invention]

The present invention was made in order to deal with the above-mentioned situation, and even if a ghost signal or other noise signal occurs in the video signal, it can be accurately synchronized with the original vertical synchronization signal and horizontal synchronization signal in the video signal, and The object of the present invention is to provide a reference signal generation circuit that can generate a reference signal that is the reference phase of the previous issue.

[Summary of the invention]

In order to obtain a reference signal for vertical synchronization, the trailing edge of the vertical synchronization signal is contaminated with noise due to the ghost 4H4 component of the video signal. The equivalent pulse is used as a reference signal for the vertical signal.

For this purpose, means is provided for extracting an equivalent pulse after a predetermined period from the trailing edge of the vertical synchronization signal.

Then, a reference counter (22
), and the output of this reference counter (22) is compared with a value obtained by adding the value of the up/down counter (42) to a preset value in a matching circuit (23). In response to the output of this matching circuit (23), the reference counter is reset and phase synchronized with the two equivalent pulses.

Further, the present invention includes a synchronization state determination means for determining a synchronization state by counting a signal indicating a synchronization state corresponding to the relative phase relationship between the horizontal equivalent pulse and the reference counter (22).

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a circuit diagram of one embodiment. In the figure,
A clock signal (Sl
) is applied. This clock signal (Sl) is, for example, P
The signal may be generated by an LL or AFC circuit in phase synchronization with the burst signal, or it may be a signal output from an oscillation circuit that simply performs free-running oscillation.

This clock signal (Sl) is counted by a counter circuit 22, and its count output is supplied to a matching circuit 23 as one input. The output of the selection circuit 24 is supplied to the other input of the matching circuit 23. The matching circuit 23 outputs a reset signal for the counter circuit 22 when the values of both inputs match. The selection circuit 24 is a monostable multivibrator 251 whose details will be described later.
Since the output of 8 is '°1'', the preset fixed value (1) is supplied in binary form to the matching circuit 23 as the other input.On the contrary, the monostable multivibrator 25.26
If the output of is "1", the output of adder circuit 3() is selected. When the output number 1d (sr) of the AND circuit 27 is "0," the above-mentioned binary number of Dif <, 10,000 is the matching circuit 23
is supplied as the other input to the J counter circuit 22.
When the count value becomes lower than , a coincidence pulse, that is, a reset signal for the counter circuit 22 is supplied from the coincidence circuit 23, and the counter circuit 22 is reset. As a result, the clock signal (Sl) having a frequency of mfH is frequency-divided by n to obtain a signal having a frequency of 2fH. When the output signal (Sf) of the AND circuit 27 is P1'', the output of the adder circuit 30 is selected as described above, and when this adder output and the count value match, the counter circuit 22 is reset.

As will be described in detail later, the output signal (Sf) of the AND circuit 27 reaches the 1" level once in the vertical scanning period.
Moreover, the period is approximately half of one horizontal scan M. Therefore, the final count value of the counter circuit 22 is usually wo, or may be set to a value different from f only once in the vertical scanning period.

Here, in connection with the output signal (Sf) of the AND circuit 27, the operation of the adder circuit 30, etc., the configuration and operation of the circuit shown in FIG. 2 will be explained in more detail with reference to the signal waveform diagram shown in FIG. do. A video signal (Sa) is applied to the terminal 31. FIG. 3 particularly shows the vicinity of the vertical synchronizing signal (VS) of the video signal (Sa). Vertical synchronization signal separation circuit 32
separates the vertical direction signal (VS) from the video signal (Sa) applied to the terminal 31 and supplies it to the counter circuit 33 as a reset signal. As shown in Fig. 3, the separated vertical synchronization signal (VS) has a slightly delayed phase than before separation due to the time constant of the vertical synchronization separation circuit 32, and has become a pulse with the cut pulse portion filled in. .

The output 1J (Sc) of the counter circuit 33 is the period during which the output signal (Sl) of the vertical synchronization signal separation circuit 32 is "1".
Also, during this period, the output of the inverter circuit o4 becomes 1'', and the clock signal (Sg) applied to the terminal 35 passes through the AND circuit 36 to the counter circuit 33.
supplied to When the output of the vertical synchronization signal separation circuit 32 becomes 0'', the counter circuit 33 detects the tarokku 4': (Sg
) starts counting. Then, when the count number reaches the preset final count value, the output signal (Sc) of the counter circuit 33 switches from "O" to "1", and the tally clock 1, :' (Sg) is switched from "O" to "1". The counting operation of the counter circuit 33 is stopped because the human power is 4z.
The width of 1δ (VS) is
is the final count value of the counter circuit 33, and T1 is a pulse extended by the period of the clock signal (Sg).

Note that the clock signal (Sg) is obtained, for example, by appropriately dividing the frequency of the clock signal (Sl).

The monostable multi-bi flakes 25 and 243 in UIF form a pulse-like signal (Sd) of a constant width at the rising timing of the output signal (Se) of the counter circuit 33, respectively.
(Se) is output. In addition, Haku'-go (Se),
Of course, a counter circuit may be used instead of a monostable multivibrator to generate (Sd).

Monostable multivibrator 25.26 with AND circuit 27
By taking the AND of the output signals (Se) and (Sd), the aforementioned control signal (Sf) of the selection circuit 24 is obtained. In this case, the 1" period of the control signal (Sf) is equal to the aforementioned The widths of the output signals (Sd) and (Se) are set to be approximately half of the horizontal scanning period (rH).Then, during the period when the control signal (Sf) is °゛1'',
The count value of the counter circuit 22 is calculated from Σ by the adder circuit 30.
The output can be switched to

37 is a horizontal synchronization signal separation circuit. This horizontal synchronizing signal separation circuit 37 has time constants etc. set to different values from those of the vertical synchronizing signal separation circuit 32, and the horizontal synchronizing signal (
83) and equivalent pulses (EQ) can be separated. In this case, δ1 is set so as to be able to reliably separate the equivalent pulse (EQ). The output signal (Sg) of the horizontal synchronization signal separation circuit 37 serves as a reset sword for the counter circuit 38, and resets the counter circuit 58 at a level of 0''.The counter circuit 38 receives the clock signal (Sl).
Now, the final count of 1 shift is 1.
If it is 6, the count will end at 41 after the start of counting.
Until 11 is wanded by the sword; Sj+gj1 becomes 16×m-(H.If the sword is about 93nsec, the above Juj direction (y6X93n5ec-=1.
The time is 49 μsec.

In this case, etc.・11. The pulse width of the ii pulse is approximately 254
Since it is μsec, the output signal (S
h) is one guard, one pulse, 1-1 pulse is 11
It will be the 16th issue with the same amount of El Chi. Of course, horizontal or vertical signal (pressure), (VS)
In the period of a wide pulse such as , the pulse rises at a frequency between trough>'J, but in this invention, the output signal (sh) of the counter circuit 38 is equal to
Q)'s 1i period is used.

The output signal (Sh) of the counter circuit 88 and the output signal (Sd) of the monostable multivibrator 25 are connected to the NAND circuit 39.
and is converted into a signal (Si) as shown in FIG. In other words, the equivalent pulse (EQ) after the vertical synchronization signal (VS) from the output signal (Sh) of the counter circuit 38
The pulse corresponding to is extracted. This 1.8i issue (S
i) is supplied as a reset signal to the flip-flop circuit 40 consisting of NAND circuits 401 and 402. 1g (Sj) and (Sk) are both read-only memory
(hereinafter referred to as ROM) (hereinafter referred to as ROM) is a signal of a frequency (2fH) output from the ROM. In this case, No. 13 (Sj) is a very narrow pulse (for example, the pulse width of one clock is 93 nsec). The signal (Sk) is the if number (Sj
) This is a pulse whose tail is set so as to add a certain ζ- from the position. The signals (Sj) and (Sk) are both
Since they are generated based on the counting operation of the counter circuit 22, they always have the same phase relationship. In short, the ROM 41 is constituted by a combination of various gate circuits, and outputs signals (Sj) and (Sk) when the count value of the counter circuit 22 reaches Σ. 1u-
The number (Sj) is the flip-flop circuit 1 (J's cent 1
It will be number J. As a result, at the output end of the flip knob circuit 40, the beans also reach IJ at the timing of 1+4t' (Si).
rising signal (Sj) timing (rising signal (Sj)
7) is obtained. This signal (SL) corresponds to the up/town power of the up/grand counter 42. The up/down counter 42 performs an up-count operation 1' in the direction υJ when the signal (SZ) is "1", and performs a down-count operation during the period "o". This "r Tsubu/Town Counter 42
Is there a clock signal (Sl) that is used as the counting clock (rj')? up/down counter circuit 42 through
supplied to Therefore, the signal (Sk), (St
) or the like as shown in FIG. 3, the up/down counter circuit 42 always performs an up-amp counting operation. Up/Down Counter Circuit/Calan h of ¥2 □When the signal (Sf) is "1", it is n. Then, the output signal of the adder circuit 30 is F+n.
A reset is applied immediately after counting, and the final count value increases. After that, the signal (Sf) becomes “0”
", and a normal counting operation is performed. At this time, the signal (Sd) also becomes 0", so the up/down counter circuit 42 is reset, and its output becomes the signal (
Sa) is 0″ until it becomes 1′ again. Thus,
In the circuit shown in FIG. 2, the signal (Sj
), (Sk) are shifted to the right in FIG. 3 compared to the video signal (Sa) or signal (sh). When this shift operation is repeated for several vertical scanning periods, the signal (S
The phase relationship of i) to (SZ) is as shown in FIG.

Note that the time axis (horizontal axis) in FIG. 4 is expanded more than in FIG. 3. In this state, the up-count operation period and the down-count operation period are the same, and the output of the up/down counter circuit 42 becomes 0'', and the signals (Sj) and (S
The phase of k) does not move.

In Fig. 4, if the signals (Sj) and (Sk) move slightly to the left, the up-count operation period becomes wider than the down-count operation period; as a result, the signals (Sj) and (Sk) ) is shifted to the right as above. On the other hand, if it were shifted to the right, the distance between the down and down operations J9j would be wider, and the output of the adder circuit 30 would be smaller than Σ. As a result of this 4° i'j, the counter number 22 is quickly regenerated), and j,;
J) and (Sk) are shifted to the left.

Due to this operation, up-count operation period 1, 'I
J and down force ・The width between 2nd movement J'JJ
When this happens, a state of convergence is reached. Like this
4j-yj (Sj) or (Sk) can be used as a horizontal acceptance signal. In addition, these signals (S)
) or (Sl() as shown in Figure 1; 1.j
Passing it through circuit 7 is 5 by obtaining the vertical base number 13.
Ru.

As mentioned above in 6FA, this embodiment uses a video signal (S
etc. 1+i after the 4L vertical synchronization signal (VS) included in a)
ii Based on the pulse (EQ), horizontal or rational basis (
! This is a configuration that generates a signal at l. Specifically, the equal pulse (EQ
) (Actually, ゛ is a signal that has the same polarity as this equivalent pulse (EQ) and has a width above the width range of this equivalent pulse (EQ)). A counter circuit 38 capable of counting up to a set final count value is provided. As a result, the counter circuit 38
A signal (sh) containing a pulse having exactly the same phase as the equivalent pulse (EQ) can be obtained at the output end of the EQ. This 4m issue (
sh), especially the pulse obtained from the special pulse (EQ) after the vertical synchronization signal (VS), that is, the phase of the signal (Si) and the signal (SJ) obtained from the ROM 41 according to the counting operation of the counter circuit 22. Based on the comparison result, the final count value of the counter circuit 22, which is normally set to the final count value i, is applied to the vertical synchronization signal (V
increase or decrease during the existence period of the equivalent pulse (EQ) after S),
The reset timing of this counter circuit 22 is shifted. Therefore, by repeating this operation for several vertical distortion periods, the counting operation of the counter circuit 22 can be made equal to the equivalent pulse (EQ), in other words, the horizontal and vertical synchronizing signals (H8) and (VS) have the same JgJ. As a result, the horizontal and vertical reference 'IFi signals can be synchronized with these signals (2) and (VS).

With this configuration, the horizontal or vertical base t(1
The reason why these signals are not easily affected by ghost signals and other noise signals when signals are obtained will be explained below. First is the groove bottom, which uses the equivalent pulse (EQ) after the vertical synchronization pulse (VS) to control the counting operation of the counter circuit 22.

Since there is originally no picture signal in the region where this equivalent pulse (EQ) exists, the region where this equivalent pulse (EQ) exists (
= The conventional horizontal synchronization signal (I-IS) is used for the separated output near J.
Even if the picture component is included, such as when using the equivalent pulse (
The waveform in the region where EQ) exists becomes a straightforward waveform, and by making the separation level (VT) shallow, the equivalent pulse (EQ)
It is possible to avoid separating the ghost component of

Note that (EQl) and (Eq, z) are positive and negative ghost components of the equivalent pulse (EQ), respectively.

Furthermore, if a noise signal is included in the video signal (Sa) due to a weak electric field or the like, the noise signal will be separated at the output end of the horizontal synchronization signal separation circuit 37. However, since the width of this noise signal is generally narrow, even if the counter circuit 38 is set to the nut state by the noise component, it will be reset before counting the clock signal (Sl) to the final count value. Therefore, the signal (sh) almost never contains pulses due to noise signals.

Note that the present invention is not limited to the above embodiments. For example, in the previous embodiment, it is basically possible to obtain a reference signal that is precisely phase-synchronized with the horizontal or vertical synchronizing signal (H3) or (VS), but due to the difference in width between up-count and down-count, , roughness (correction may cause jitter. In this case, if the count value of the up/down counter circuit 42 is divided by a fraction and supplied to the adder circuit 30, the count value of the counter circuit 22 can be adjusted. The operation can be controlled finely, and the occurrence of jitter as described above can be prevented.In this case, by shifting the count value of the up/down counter circuit 42 by n bits, this count 1lii, f output can be Obtainable.

Another method is to use an up/down counter circuit.
When the operation has converged to some extent, the output of the AND circuit 27 (i'i (Sf)) is forcibly set to °'0'', and the final count value of the counter circuit 22 is further set as soon as possible. In this case, horizontal and vertical same jlJ
Although there is a strong possibility that a reference signal completely phase-matched to the j signal (H8) t (vs ) cannot be obtained, a reference signal with higher quality can be obtained than in the case where jitter occurs.

In addition, (L+ (Sl)) corresponding to the equivalent pulse (EQ)
As means for controlling the counting operation of the counter circuit 22 using the up/down counter circuit 42, the adder circuit 30. A configuration other than the configuration using the matching circuit 23, the selection circuit 2/1, etc. may be used.

FIG. 6 shows how the counter circuit 22 counts clocks according to the relative phase difference between the output (Sl) of the NAND circuit 39 and the output (Sk, Sj) of the read-only memory 41 in response to the above-mentioned horizontal synchronization signal. In a system that generates a reference signal by correcting the reset timing of the system, a circuit 200 for determining whether or not synchronization has been stably determined by (*1) is shown.

That is, one input terminal P1 of the ``identity'' determination circuit 200 shown in FIG.
d (Sl()) is added. Also, the other input terminal P2
A signal (Sl) corresponding to the horizontal synchronization signal is applied to. Then, the AND circuit 100 performs an AND operation between the signal (Sk) and a signal (Sl) obtained by inverting the signal (Sl). The calculation in the AND circuit 100 is such that during the pulse period of the output of the NAND circuit 39 having a phase corresponding to the horizontal synchronization signal, a signal (Sk) outputted from the read-only memory in response to the output of the counter circuit 22 is Determine whether it exists or not. Therefore, as previously shown in FIG. 4, the horizontal synchronizing signal (Si) exists during the pulse period of the signal (Sk), and the output state of the counter circuit 22 has a phase difference υj with respect to the horizontal synchronizing signal. If so, the AND circuit 100 generates a pulse. At this time, the counter 102 in FIG. 6 counts -1', the output pulse of the AND circuit 100, and outputs the AND signal indicating that the phase of the output of the counter circuit 22 is 1ijJ All to the horizontal synchronizing signal. Count the output pulses of 1N3100.

On the other hand, the AND circuit 101 generates a pulse indicating that the output of the counter circuit 22 is not synchronized with the horizontal synchronizing signal. Then, the pulses are counted by the counter 103. This: Karasu, written in - AND circuit 1
00, , 101 are monostable multibibreaks 25
The horizontal interval jυJ・ia gated by the output signal (Sd) of
A pulse is generated in response to the signal (S'i). The counter 102. 103 is the AND circuit 100. 10
Each counter is set to count one output pulse, χ, y. Therefore, when the counter 102 counts the output pulses of the AND circuit 102 by χ, the counter 102 generates a pulse at the output. At this time, the counter 1
02 itself and the counter 103 are reset, and the flip-flop 105 is set, and the output of the flip-flop 105 becomes "1".

Similarly, when the counter 103 counts the output pulses of the AND circuit 101 indicating an asynchronous state by y, it resets the counter 103 itself and the counter 102, and also resets the flip-flop 105.

As a result, the flip-flop 105 becomes "1" when the counter has counted pulses by χ.

In addition, the counter 103 is
When the pulse is current by y, the output of the flip-flop 105 becomes "0".

Therefore, the output of the flip-flop 105 indicates whether or not the state of the counter circuit 22 is synchronized with the horizontal synchronizing signal.

Here, the counter 102. Count value χ of 103
, y, the determination accuracy of the synchronization determination operation can be arbitrarily set, and the synchronization state can be stably determined.

FIG. 7 shows, in the same way as FIG.
A determination circuit 300 is shown.

In Fig. 7, the signal (Si) used for synchronization determination
, (Sk) are the same as in the case of FIG. 6, but differ from the case of FIG. 6 in that a D-type flip-flop circuit is used.

In FIG. 7, the data terminal of the D-type flip-flop 301 is connected to 1 and 1 (Sk) corresponding to the output of the counter 22.
) is applied to the clock terminal, and a signal (Si) corresponding to the horizontal synchronization signal is applied to the clock terminal.

The output terminal Q of the above-mentioned flip-flop is connected to the reset terminal R of the counter 302.
02 uses, as a clock, a signal obtained as a result of ANDing a signal obtained by inverting the output by an inverter circuit 303 and an output (Si) obtained by inverting the above signal (Si) by an inverter circuit 305 in an AND circuit 304.

In the synchronization determination circuit 300 shown in FIG. 7, the above-mentioned flip-flop 301 uses the signal (Sk) corresponding to the output of the counter circuit 22 as data, and the horizontal opening force]
・The clock is No. 13 (Si), which is the 4th target for the melting bow.

Therefore, the signal (Sl) corresponding to the horizontal synchronization signal is
When applied to the clock terminal of the flip-flop 301, the counter circuit 22 is applied to the data terminal.
The state of the signal (Sk) corresponding to the output signal of is detected.

In other words, when the signal (Sk) and the signal (Sl) are out of phase, the signal (Sk) is within the pulse width of the signal (Sk).
If Si) does not exist, the output terminals of the flip-flop circuit described above become "1", and the counter 300 is reset. Manoko, Npuunta 30
0 uses the above signal (wavelength) as a clock and performs a counting operation only in a synchronous state. In this case, the counter 302
is configured so that when it counts χ, its output terminal becomes "1". Therefore, when the counter value of the counter 300 reaches χ', the AND circuit 304 is interrupted by the inverter 303, and the clock supply to the counter 300 is stopped. This means that when the counter 800 counts pulses by χ', the signal (Si) is relatively removed from the pulse 1 state of the signal (Sk) due to the two-letter flip-flop circuit, and the counter 302
Unless the reset pulse of
The output state of 02 remains "1".

That is, when the counter 302 detects the same υj state, the output of the counter 302 becomes "1" and is synchronous! :5υ
Discern. On the other hand, the counter 302 is in a state where it is sufficient to count the output of the AND circuit 304 by χ', which is a synchronization detection pulse, or - it is determined that the carrier synchronization state b is a synchronization detection pulse and the above-mentioned flip-flop 301 is used to de-synchronize it. If a state is detected, the output becomes a "0" state, indicating an asynchronous state.

The output of the synchronization determination circuit shown in FIGS. 6 and 7 described above is subjected to a logical operation with the output of the AND circuit (Sf) shown in FIG. It can be used as a control signal for the selection circuit 24 that selects whether to supply a value or a value obtained by adding one cycle of the up/down counter 42 to a preset value. This makes it possible to perform the phase correction operation using the up/down counter 42 only when the phase correction range is within the phase correction range.

The synchronization determination circuit also has a function of stopping the circuit operation of the ghost removal circuit, which performs ghost removal operation using the trailing edge of the vertical synchronization signal as a reference time, in accordance with the result of determination of the synchronization state.

Therefore, it is possible to prevent the ghost removal circuit from operating unnecessarily in an unsynchronized state.

〔Effect of the invention〕

As described above, according to the present invention, even if a ghost signal or other noise signal occurs in the video signal, it can be accurately synchronized with the main vertical synchronization signal and horizontal synchronization signal in the video signal, and a stable reference signal can be obtained. - A reference signal generation circuit that generates an 11° L-phase signal can be provided.

According to the present invention, it is possible to provide a standard signal generation circuit that can accurately determine whether the device is in an asynchronous state or a synchronous state.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional reference signal generation circuit, FIGS. 2, 6, and 7 are circuit diagrams showing an embodiment of the reference signal generation circuit according to the present invention, and FIG. FIG. 2 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 2, and FIG. 4 is a signal waveform diagram for explaining one signal wave in FIG. 3. 21, 29.31.35...Terminal, 22.33.38
...Counter circuit, 23...-number circuit, 24...
Selection circuit, 25.26... Monostable multivibrator, 27.36... AND circuit, 28.34... Inverter circuit, 30... Adder circuit, 3Z... Vertical synchronization signal separation circuit, 37 ...Horizontal synchronization signal separation circuit, 3
9... NAND circuit, 40... Flip-flop circuit, 41... ROM, 42... Up/down counter circuit, 200. 300. Same N” state profit circuit.

Claims (1)

[Claims] Vertical synchronization signal extraction means for separating a vertical synchronization signal from an incoming signal; horizontal synchronization signal extraction means for separating a horizontal synchronization signal from the incoming signal; and a predetermined period after the trailing edge of the vertical synchronization signal. vertical gate signal generating means (32, 33, 34° 35, 25) for generating a predetermined first gate signal (S d ) for a predetermined period; and the first gate signal generated by the vertical gate signal generating means. Comparison signal separation means (38° three) for separating the horizontal open j'jl signal (Sl) corresponding to the signal period, and a signal to be phase-compared with respect to the previous comparison reference signal separated by the reference signal separation means. a reference counter (22) that generates an output of
a first comparison signal (Si) whose phase is to be compared with the comparison reference signal which is the output of the reference counter, and a decoder means for the reference counter which generates a second comparison signal (Sk) with a wider pulse width; and this decoder means The first comparison signal (Sl
) is used as a clock signal, and is reset in response to a first gate signal (Sd) generated at the output of the vertical gate signal generating means; means (4o) for generating a control signal for controlling an up-down operation in response to a comparison signal; and means (4o) for selectively adding the value of the up-down counter and a preset value, and adding the result of this addition to the counter. a matching circuit for detecting coincidence of the outputs of the matching circuit, a reset means for resetting the reference counter by the output of the matching circuit, and synchronizing the phase of the output of the reference counter f with the previous horizontal synchronization signal; and the decoder means. 1. A reference signal generating circuit comprising: a synchronization state determining means for counting a predetermined number of logical product results of the comparison signal and the RJI comparison signal, and determining a synchronization state based on the counted value.