JPS59175100A - Data storing system - Google Patents

Abstract

PURPOSE:To shorten a data storing time to an RAM by reading the data within a time slot of a writing mode and at the same time performing a parity check together with the writing. CONSTITUTION:The microinstruction data which contains the parity check bit supplied to a processor from a main memory via a bus 400 is stored in a buffer 7. The microinstruction data and its check bit are stored in an RAM1, and the information read out of the RAM1 is stored in a register 6. A command 103 given from another processor is applied to a decoder 4. Then the data is written to the RAM1, and at the same time the data written before the change of the address supplied to the RAM1 is immediately read out and checked. Therefore the writing and reading are carried out in a time slot given for writing. Thus the data loading time to the RAM1 can be shortened.

Description

[Detailed description of the invention] The present invention relates to a data storage system.

Conventionally, in a device that operates using microinstructions that cannot be stored in a random access memory (hereinafter abbreviated as RAM), the microinstructions are first stored in RAM before the device is used. In order to check whether or not the instruction has been executed in error, all stored microinstructions are sequentially read out, their parity is checked, and operation is started after confirming that there are no errors.

That is, in the conventional data storage method of this yuzu, prior to the start of operation, the sum of the data storage time T1 and the subsequent data parity check time T2 (T! + T2
) has the disadvantage that it takes place in the evening.

It is an object of the present invention to eliminate the drawbacks of the above-mentioned conventional method, reduce the time required for starting the above-mentioned operation, and reduce the data storage time of the conventional method.
The object of the present invention is to provide a data storage method that is significantly shortened to equal to 1.

The system of the present invention includes a signal generating means that generates a first signal and a second signal following the first signal at the same cycle in response to a command periodically supplied from the outside, and an initial setting signal. In response to the supply of n, an address of one value is supplied, and the first signal is generated after a certain period of time every time the second key signal is supplied.
an address control means for changing the address to a specified address in fj; and supplying data including a parinai check pit externally supplied to the address supplied from the address control means to the first key number. storage means for storing data in response to the second signal; register means for temporarily storing data including the parity check bit i supplied from the storage means in response to supply of the second signal; and checking means for performing a parity check on data including a parity check bit.

In addition, the system of the present invention responds to a signal supplied periodically from the outside and generates a signal of 1 and a second signal following this first signal at the same period. Generation setting and light #l
M
Is the supply VC of the +i record 2nd address VC response and the fishing record address? address control means for tweeting to a specified address;
storage means for storing data including a parity check bit supplied from the outside at an address supplied from the address control means; register means for temporarily storing data each time the first signal is supplied after a certain period of time before the second signal is generated; and inspection means for performing a parity check on data including the parity check pits supplied from the register means. including.

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, a main memory 100, a processor 200, and a processor 300 are connected to each other by a data bus 400. The data from @100 is transferred to the processor 300V%M via this path 400.
8nru. The processor 200 supplies the processor 200 to the processor 200 via the path 103. Furthermore, processor + r200 and processor 300
It is the same as the 4th clock: 9 蛎σ.

When Zhu 2 is layered with glue, the main memory 1 of the present invention is
00 furnace data bus 400
and 102) to the processor 300.
A buffer (hereinafter abbreviated as BUF') 7 temporarily stores microinstruction data with a parity check pin 1 to be provided to the microinstruction bit 101, and a parity check bit is directly - 1'LAMl and 1'LAMl, which provide micro-age data and its data storage via @102), and IAAl
The controller (hereinafter abbreviated as SQR) 2 that supplies the I3 address, the microinstruction data read from RA = vl 1 and its check pin If'! j! IP
3 micro-instruction register stand game) 311, 31
2 and 313 input at least one of the inverters 302, 306, and 307, each of which has an output of 10", so its output is 10#. Since the other cases can be easily understood, the explanation will be omitted.

The order of command codes when loading microinstructions into RAMI is to repeat commands a, b, and c, and command d is sent after loading is completed r.

FIG. 5 shows a detailed block diagram of C0NT5.

The C0NTs are connected to the DEC4 via connection lines 104-1 to 104-4 (collectively 104).
, [INCμEMENTJ, rRAM ENAB
BU receives the LEJ and [LOAD BUFJ signals, the processor clock from CLK8 via connection line 113, and the "initialization" signal from processor 200.
A clock signal (hereinafter referred to as 113UF LOAD CL) that loads microinstruction data to F7 via connection line 107.
KJ signal) and a write clock signal (hereinafter 1'WRIT) to RAM1 via the connection line 108 to RAMI.
ERAM CLKJ signal), a signal to load the microinstruction read from RAMI via connection line 109 to MIR6 (hereinafter referred to as iIRLOADJ signal), and a signal to PCK3 via connection line 110 to enable PCK3 to operate. signal (hereinafter [PARITY CHECK E
NABLEJ signal) and connection line 111 to 5QR2.
-1,111-2 and 111-3 (collectively 111)
(This signal is only relayed and the main line has been changed from 104-2 to 111-1 for convenience), a signal for switching the multiplexer 22 (hereinafter referred to as " The signal that gives the address of address 0" (i[ZE
ROJ signal). Although the processor clock is distributed, it is omitted in FIGS. 5 and 2 for obvious reasons.

Next, the generation of each signal will be explained (see figure -A7).

“WRITE RAM CLKJ signal is AND gate 4
Occurs on 07. That is, IM/RI'Jl"E)t
The AND gate 407 is opened by the supply of the AMJ signal 11, and the processor clock inverted by the inverter 409 is further supplied (from this point, 1 is WRITE RA).
I(CLKJ code is generated and supplied, i.e. IWR
jW31TE R in synchronization with I T EltAMJ issue
AA4 CLKj signal is generated.

[TFJ (No. 8 is generated by a flip-flop (hereinafter abbreviated as FF') 402. FF 402 is reset by the "initial setting" signal, and the l'-TRFJ signal initially becomes "0". Then [RAM ENAB'LEJ
When the signal "1" is supplied (all or game) 405t and then sampled by the processor clock, the TRFJ signal becomes "1" and is self-held thereafter.

The "MIR, LOADJ signals are created by the OR gate 406. That is, initially, the l"TRFJ signal B is generated as described above.
ゝゝo “The late rMIRLOADJ (N No. 1”i Jl
, NCREMENTJ I^°(・) is supplied synchronously, but the "TR1;" J signal is 11 "403 is reset upon supply of the "initial setting" signal, so [PARIT
The Y CHECK ENABLEJ signal is the current 10" and the first [INCREMENTJ signal 11] is the OR gate 4.
04 to be supplied and sampled with all grossesosacronoku (・Koyori [upper'ARITY CF
iECK 1 NABLEJ E issue is ゝゝ
1", and thereafter FF 403 is self-maintained.

“BUF LOAD C, LKJ signal is AND gate 4
Occurs in 08. In other words, [LOADBUFJ Hakugo'
1", the AND gate 408 opens, and furthermore, by supplying the processor clock inverted by the inverter 410, the "BUFLOA, DCLJ" signal $ILL is generated and supplied. In other words, the "LOAfJU" signal is generated and supplied.
gBUF LOAL in synchronization with L, iPJ and other signals>
CLKJ Hakugo signals.

[ZEROj Signal 1-iFF” 401 occurs.

That is, the F F 401 is initially reset by the "initialization" signal and the "ZERO" signal is 0", but the D terminal (r) is sampled from 111/l supplied by the first processor clock, and thereafter it becomes "ZERO". ERO
The J signal becomes 11'.

FIG. 3 shows a detailed block diagram of S and QR2. 5
QR2 supplies an address to the RAM through the connection line 112, and the address is the address currently being supplied from C and others through the WiHl line 115f.
Addresses stored in the current address register (AR) 21 (abbreviated as AR), addresses stored in the memory (abbreviated as M) 25, and addresses stored in the register (abbreviated as 几) 24. One of these addresses is selected by a multiplexer (abbreviated as 1XfL) 22.The selection of MXR22 is made by a selection signal S.
O, St, if it is accurate, it is the same as the seventh table in Table 2.

In the initial state of Table 2 5QR2, each value is '0#I) [
TFcFJ and other Qf “Z, EROJ signal and igxw[
INCREIx4ENTJ code is supplied from C0NT5. The l-'I' RF J signal is '0', so the AND gates 27 and 28 are closed and the signals So and Sl are respectively 0', so M The selected address is supplied to the AND gate 26. However, 71EWJJ and others supplied to the ground input line of AND gate 20+
=i'v;0"The AND gate 26 is closed,
f'=WW The address supplied to the RAM 112 is OJ. The processor clock (f) is supplied thereto.
- and continues 'C address 'o' is stored in connection line 11
This means that the data can be supplied to the RAM 1 via 2.

111" becomes [INcftEMENTJI λ is AD2
3, AD 23 responds by adding the supplied address value N. In this case l-0-1
-1", that is, the address "1", is newly supplied to R24, and by the processor Kurotsuno! /8 has been changed to MXR22 and AND gate 26 (at this point "Z
Ef (・0" signal is '1" and AND gate 26 is open) and then connects to AM via connection line 112.
IL supplied to I. From now on, it will be called ``INCREME''.
: Every time NJ II is supplied (r(, Kono SG,)
When the addresses added by 1 from J(, 2 to ■ via the string line 112 are supplied to AM1 as a series 'j' CI/, it becomes 7. After J'υ, when all the addresses of +yRAM1 have been supplied , - "becomes ['l" RFJ signal is supplied, and the MXFL22
The address selected in is supplied.

The total p block of PCK3 is shown in FIG.

Microinstruction data and parity check bit (lζ) supplied from PCK 3 MI R5 through connection lines 113 and 114, and if an error is detected (F:
The FF 502 is reset by the "initial setting" signal supplied via the connection line 05, and the FF 502 is reset via the connection line 106.
-Le "PA)tI'l'Y ER, RORJ The ceremonial name is 1o
“is.

Then, n7 is supplied from C0NT5 via the connecting line 110.
-, 1” becomes 1-PAaITY CHECK ENA
The AND gate 503 opens from the BLEJ signal t, and the output of the check circuit (abbreviated as CK) 501 becomes Fl・'
502 input. CK2O2 is a parity check and L! 1, and when an error is detected, it sends a message to 503, "11". The number is ゛Age r5υ4 all through the system'' input into F502 n,
Due to the processor clock, the line 106 is activated and becomes C-V1.
ER Rin C Sakai, No. 1 and 71 yell outside. Top 1
1"502 is 1>, :+j to protect/j 2L.

Is Nobutaka Tanigami of the main memorial service in the 71st funeral? - The output address and the data to be stored are indicated by Munayat. Is the behavior of Erimoto Meihi example shown in Figure 7 and 弗 2 丙 as a king? explain.

First, in "Initial Settings" No. 18, 91:laf 1,0; In response, each F1 in C0NT5 and PCK3 is reset.

0” becomes 1”゛'1゛RF” E and 'JZiROJ
Irosu is sent to 5Qi12, and 5Q) R2 supplies fl & Kono dress "0" to RA. Next, the first part of the broso pomegranate + (Yo D ” 1
〃fil[zEauJi=q7＞= 5IJi2+C
, 4 and the supply of address "0" is continued. Here, a series of commands for data transfer are supplied from the processor 200.

When the command a is supplied, the DEC4 decodes it and ``1'' exists [J, OAJ'). It supplies the BUF'J signal C0NTs (tζ) and outputs C0NT5 (r'i
In response, the microinstruction data and parity check bit (together referred to as Do) are stored.

Next, DEC4 responds to command b's supply by 'bi'' and uses this as a solution.
J (P, No. 1c is supplied to ONT5, and C0NT5 responds to this by sending ``WRITE RA8 to ``1'').
Supply the CLKJ signal to R, AM 1. This is V response)
- Ri', Ml is data D from BUF7.

In response to the supply of ``0'' as an address to history, 5QR is supplied.
Since it is received from 2, Do is stored at address 0.

Furthermore, in response to the supply of the command C, the DEC4 decodes this and supplies a [INc_EMENTj signal of 1" to C0NT4>5, and C0NT5 responds to this with a 111" [MILOADJ and other signals MI At the same time as supplying to R6, lV 1# becomes "I NCRE~IEN'
l'j Iyumi's fX: 8 (and R2 shiko 1 cane ze-5. MIR6 is 1 process 4HL LOAL) J signal is supplied and the processor clock is executed immediately after that! The data DO supplied from RAM1 by the east is stored. On the other hand, 5QR2, which was supplied with "1" [T NCH,EM F:NTj, has Δ+rIR6 as data D.
When O is stored, the address is switched to "1" at the edge of the processor clock and supplied to RAMIK. Also C0
1 following from NT5 [PARITYCHEC
A KENABLEJ signal is provided to PCK3, which in response checks the data provided by MIR6.

As described above, data D by codes a, b, and c is
The posting of O to RAMx and its parity check are completed. After this cycle is repeated, data D1. D
2...Dn is stored and checked. When the final data has been stored r, the command d is completely supplied D
EC4 decodes this and reads ``1'', which is ``几AM ENAB.''
The LEJ signal is applied to CON'f''5, and in response, C0NT5 generates a cd-continuous 11'' signal of ``T'' and [MIRLOADJ, which are applied to 5QR2 and MIR5, respectively. 5QR2 becomes 1” [TRF
So/, which is supplied from the external η in response to the signal from J.
The address rXJ selected by the Si' signal is
Supply to I. MIR6 is 1゛1〃l'-MIR
Data D is supplied from RAM 1 by the node line of the gross output clock after the LOADJ signal is supplied.
X (data stored at address X of R7AM1) is stored and checked by PCK3.

If there is a parity error during data transfer to RAMI, for example if there is an error in data D1, the PC
Detected by K3, the signal becomes 1 and is supplied to the outside.

As described above, in this embodiment, the data Dk is stored in the RAM 1, and the written data Dk is immediately read out and checked at the address supplied to the AMI. What's more, you don't need a special time slot to continuously load data Dk, but if you use the time slot given to you, you can load the data and check it all in parallel, so you can check the loaded data. Including FtAM load+i
:1 interval is noticeably shortened.

In this embodiment, all the data of the signal Muslot given to [INCREMENTJ] is read out to MIR6 and the address is changed thereafter, but the present invention is not limited to this. i.e. IM'RITE
It can also be used to write all the data in the time slot given to RAMJ to AM1, +5- and then read it to MIR6.

In this embodiment, the micro device was able to carry out the transfer of the δ order, but it is obvious that the present invention is not limited to this and can be applied to the transfer of some data.

As described above, the present invention is based on the fact that each time data is written to a random access memory, the data is read within a time slot given for borrowing, and the parity check of the data is performed in parallel with the writing. This has the effect of reducing the time required to store data in a random access memory, including checking the parity of stored data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system for loading microinstructions in main memory into the RA of a first processor (I) of a second processor, and FIG. Figure 3 is a block diagram of the sequencer used in Figure 2, Figure 4 is a block diagram of the decoder used in Section 2, and Figure 5 is a block diagram of the control unit used in Figure 2. , Fig. 6 is a block diagram of the parity check section used in Fig. 2, and Fig. 7 is a time chart of some signals used in Fig. 2. In the figure, 1... Random access memory (
To aA 4), 2...Sequencer (SQR), 3
...Parity check section (PCK), 4...
... Decoder (DEC), 5 ... Control section (
CONT), 6...Micro instruction register (
MIR), 7...Buffer (BUF), 8...
・・・・Clock occurrence part (CLIgu), 21・・・・
・Address register (Alt), 22...Multiplexer (MAR), 23...Adder (AD)
), 24...Register (R), 25...
...Memo IJ (M), 26-28...And Gate, 100...Remembering the Lord, 101-11
4... Connection line, 200... Flosser 1
1300...Processor end, 301-307.
...Inverter, 308...Gate, 309
~316...and gate, 401~403...
...Flip-flop (E'I"), 404~4
06...Or Gate, 407,408...
AND gate, 409, 410... Inverter, 501... Check circuit (CK), 50
2...Flip-flop (FF), 503.
...and gate, 504...or gate. Agent Patent Attorney Uchihara 4 ・'-゛3, Enter-
Nomo (Figure Azr Go 3 figure)

Claims (2)

[Claims] (1) Signal generating means for generating a first signal at the same cycle in response to a command periodically supplied from the outside and generating a second signal following the first signal; an address control means that responds by supplying an address of a constant value and changes the address to a specified address after a fixed period of time every time the second signal is supplied, and before the first signal is generated; storage means for storing data including a parity check pit supplied from the outside at an address supplied from the address control means in response to supply of the %1 signal; and a parity check bit supplied from the storage means. Data characterized in that it includes register means for temporarily storing data in response to the supply of the second signal, and inspection means for performing a parity check on data including the parity check pit supplied from the register means. Storage method. (2) In response to commands periodically supplied from the outside
- signal generating means for generating a first signal and a second signal by combining the first signal with the same period, and supplying an address of a constant value in response to supply of the initial setting signal to generate the second signal; address control means for changing the address to a designated address in response to the supply of the first signal; and address control means for changing the address to a specified address in response to the supply of the first signal; storage means for storing data in response to the supply; and temporarily storing data including a parity check bit supplied from the storage means after a predetermined period of time each time the first signal is supplied and before the second signal is generated. 1. A data storage method, comprising register means for storing data, and checking means for performing a parity check on data including the parity check bit supplied from the register means.