JPS59174965A - Inter-processor communication interrupt control method - Google Patents

Abstract

PURPOSE:To prevent the capacity drop of a processing device due to communication between processing devices, by pending an interruption for communication until another processing device releases the occupation of an interruption message list and, during the pending period, by executing and processing an instruction while checking whether the list is occupied or not. CONSTITUTION:Resetting of interruption for communication pending FEs 6 installed to each processing device is performed after one instruction is processed at a self-processing device and setting of the FFs 6 is performed when an interruption for communication request signal to a processing device is on and its FF6 is off and when another processing device occupies its interruption message list. Then the AND of the off signal of the FF6 and interruption for communication request signal is taken and used as an interruption for communication accepting signal A. When the accepting signal A is on, the interruption processing is performed and, when the signal A is off, an instruction to be made when the interruption for communication processing is not performed is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiprocessor system, and in particular,
The present invention relates to a control method suitable for inter-processor communication.

[Prior art]

The conventional communication between processors is shown in FIG. 1, and the communication interrupt mechanism shown in FIG. 1 is shown in FIG. In the conventional processor) connection side-in control method? When connecting/retrieving a message list including jjll, YCh is used to control message list occupancy/retrieval in order to manage message list conflicts.
You need to release it. For this reason, communication interrupt transmission processing and reception processing (mtt shown in Figure 3 1 and Figure 4)
It becomes l-diagram. (These processes are realized by microprograms) Here, the first
If another processor number is stored in the lock area in the message list shown in the figure, the operation is in progress. In addition, in order for the own processor to occupy the message, store the own processor number in the lock area, and store this occupancy (I - YC to be released).
Is there no processor number in the lock area? Store.

Therefore, while one processor is occupying the message list TF, other processors have to wait until this occupation is divided by 1, resulting in an idle state. During this time, other processors 3 perform operations on the shared memory 1 in order to ink lock the inter-processor shared bus 2 shown in FIG. This has the disadvantage that the processing capacity of each processor 3 is reduced.

In addition, in order to compensate for this drawback, a method can be considered in which the processor that has occupied the interrupt message list bends the communication interrupt acceptance signal Rk to other processors until the occupation is released. In addition to the request signal R, the connection interrupt signal is
Off signal? , it is necessary to provide it outside the processor, which has the disadvantage of being a costly mechanism.

[Purpose of the invention]

Is the purpose of the present invention to reduce the processing capacity of processors due to inter-processor communication? There is a VC that uses a simple mechanism 11 to provide a side leg system for inter-processor communication.

[Summary of the invention]

The uninvented feature is to communicate interrupts until another processor releases the interrupt message list. The point is that the command is executed while checking whether or not it is occupied during bending.

[Hashu J's lol pole row]

Conventional communication interrupt mechanism (FIG. 2): VC1 communication - Flip-flop for the rounded tapending flag and t', ND game type child r are provided, and the communication interrupt + compensation shown in FIG. 5 is provided.

! , In figure g5, the communication interrupt reception '7jA r;
LsConventional communication interrupt grant flag 5 is in the OFF state, and
Sent only when the contact interrupt spring vending flag is in the off state. Here, the cent.
Reset can be done as usual. In addition, by performing the conventional communication interrupt reception processing (Fig. 4) as shown in Fig. 46, the dramatic bending flag can be set in the sequence.
. The communication interrupt bending flag is reset every time the instruction execution process ends, as shown in FIG.

Next, what are the communication interrupt signals from other processors in Figures 5 and 6? The operation of the communication interrupt system from reception to jump to each imprint processing routine is described below.
〉～14〉.

0> After receiving the communication interrupt number 1g from another processor, the command execution process begins.

In Figure 6(b), <1> The presence or absence of the communication interrupt reception signal A is completely determined.

Here, since the bending flag is in the OFF state during the previous instruction execution process, the communication interrupt non-acceptance signal is not accepted.

(Figure 5) 2>Jump to the communication interrupt reception processing routine.

In FIG. 6(a), <3> Does another processor write its own processor's message list? It is determined whether the operation is in progress or not. Tokai in operation, working 4
〉￥C〼, Yang meeting not in operation, Proceed to 12〉.

4> Set the connected interrupt bending flag 6 to the busy on state.

5> Return to instruction execution processing.

In Figure 6(b), 6> Is there a communication interrupt reception signal A? judge.

In this case, since the contact interrupt peding flag 6 is in the ON state, the contact interrupt acceptance signal A is absent. (Figure 5) 7) Take out the command, challenge it, and execute it.

<8> Turn hK4 interrupt bending flag 6 off.

9> Start the next instruction execution process.

<10> Presence or absence of uninterrupted interrupt reception signal A. Add 'tr-flJ.

Here, select Qi) lf′g <1
> Similarly, the communication interrupt reception number 1u Hiromi/Hachi is /rip.

<11> By jumping to the communication interrupt reception processing routine, proceed to step 3>.

In FIG. 6(a), <12> The message list If of the own processor is occupied,
Sending pro sensor message? Take it out and release the message list of the own processor.

<13> Send late interrupt acceptance voice signal τ. Now, there will be no communication reception signal (Figure 5).
The communication interrupt reception processing routine VC does not jump until it receives a communication interrupt request signal from another processor.

<14> Jump to the processing routine according to the message.

More than one work? The time chart is shown in FIG. 7.

〔Effect of the invention〕

According to this invention, it is possible to prevent a decrease in the processing ability of a processor and to quickly carry out communication between processors.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the conventional communication interrupt transmission process between processors, Fig. 2 is a diagram of the conventional communication interrupt mechanism, Fig. 3 is a flowchart of the conventional communication interrupt transmission process, and Fig. 4 is a diagram of the conventional communication interrupt transmission process. Flowchart of interrupt reception processing, Figure 5 is a communication interrupt mechanism diagram of the present invention, Figure 6(a) is a flowchart of the box interrupt reception processing of the present invention, Figure 6(b) μ Command execution processing of the present invention The flow is bad, Figure 7 is 6
It is a time chart of the main 1B issue with respect to the operation issue of the figure. A...Contact interrupt reception signal, 6...Contact interrupt Benzo No. 1 Kyouzu 2 Kousou 30 Dou Kutou Yu Koman triJ

Claims (1)

[Scope of Claims] 1. In a multiprocessor system equipped with a plurality of processors and a processor common memory shared among them, 41J interrupts are used to communicate between the processors, and the processor that issues an interrupt: occupying the queue of the interrupt message assigned to the processor of the other party on the inter-processor common memory, and placing one's own interrupt message thereon, and then releasing the occupation and spending the interrupt money; The processor on the side receiving the interrupt occupies its own processor's @printed message queue, and after releasing the interrupt message, releases the occupancy (Il-) and performs processing according to the interrupt message that was removed. In the interprocessor communication side open/open method, the flip-flop for communication interrupt bending flag provided for each processor is reset after one instruction is processed by the processor itself, and the flip-flop is set. When the contact interrupt request signal for the second processor is on and the flip-flop is off, another processor is occupying the first message list of the own processor, and further, the flip-flop Logic check of the off signal of the flop and the previous contact interrupt request signal, this is the contact side interrupt acceptance signal, and when this contact interrupt acceptance signal is on, no interrupt processing is performed, and the contact interrupt acceptance signal is What to do if the contact interrupt processing line 4 is not executed when is off? 7!
i- A method for controlling communication between processors.