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JPS5917229A - Laminated condenser element - Google Patents

Laminated condenser element

Info

Publication number
JPS5917229A
JPS5917229A JP12694982A JP12694982A JPS5917229A JP S5917229 A JPS5917229 A JP S5917229A JP 12694982 A JP12694982 A JP 12694982A JP 12694982 A JP12694982 A JP 12694982A JP S5917229 A JPS5917229 A JP S5917229A
Authority
JP
Japan
Prior art keywords
dielectric
layer
electrode
dielectrics
multilayer capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12694982A
Other languages
Japanese (ja)
Inventor
横谷 洋一郎
嘉浩 松尾
純一 加藤
新田 恒治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12694982A priority Critical patent/JPS5917229A/en
Publication of JPS5917229A publication Critical patent/JPS5917229A/en
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は積層型コンデンサ素子に関し、特にキュリ一点
の異なる誘電体を用いて素子のみかけの誘電率を大きく
し、その温度変化を小さくする手法を応用した、積層型
コンデンサ素子の構成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer capacitor element, and in particular to a multilayer capacitor that uses a dielectric material with a single point of difference to increase the apparent permittivity of the element and reduce its temperature change. This relates to the structure of the element.

一般にセラミックコンデンサ素子に用いられる誘電体材
料は、素子の大容量化、小型化の要求から高い誘電率が
求められており、このだめ常温付近で強誘電性を示すB
aT i○3系固溶固溶体がこれに用いられている。し
かし、上記の誘電体材料は′常温付近に強誘電相から常
誘電相へ転移するキューリ点をもち、この温度で誘電率
が極大値をとり、この温度付近で誘電率が温度に対して
大きく変化することから実用上問題となっている。
Generally, dielectric materials used in ceramic capacitor elements are required to have a high dielectric constant due to the demand for larger capacitance and smaller size of the element.
An aT i○3 solid solution is used for this purpose. However, the above dielectric materials have a Curie point near room temperature where they transition from a ferroelectric phase to a paraelectric phase, and the dielectric constant reaches its maximum value at this temperature. This poses a practical problem because of the change.

そこで、素子としての3かけの誘電率を大きくし、しか
も誘電率の温度変化を小さくする手法として、キュリ一
点の異なる誘電体を複数個用意し、これらからなるコン
デンサを複合して用いることが知られている。
Therefore, as a method to increase the dielectric constant multiplied by 3 as an element and to reduce the temperature change in the dielectric constant, it is known to prepare multiple dielectrics with different Curie points and use a capacitor composed of these in combination. It is being

たとえば回路上、」−記コンデンザを並列に結合した場
合、各コンデンサの電極面積と厚さが等しいとするなら
ば、素子の見かけの誘電率は第(1)式%式% ここでnはコンデンサの個数、ε、はm番目のコンデン
サの誘電体の誘電率である。
For example, in a circuit, when two capacitors are connected in parallel, and if the electrode area and thickness of each capacitor are equal, the apparent permittivity of the element is expressed by formula (1)%, where n is the capacitor The number of capacitors, ε, is the dielectric constant of the dielectric of the m-th capacitor.

第(1) :uより明らかなようにキュリ一点の異なる
いくつかの誘電体からなるコンデンサを並列に結合した
素子では、キュリ一点VCおける各誘電体の高誘電率か
重畳され、見かけの誘電率が高く、その温度変化の小さ
い特性が得られる。
Part (1): As is clear from u, in an element in which capacitors made of several dielectric materials with different Curie points are coupled in parallel, the high permittivity of each dielectric material at the single Curie point VC is superimposed, and the apparent permittivity is It is possible to obtain the characteristics of high temperature change and small temperature change.

一方、上記のようにキュリ一点の異なる誘電体を組合せ
一つの素子とする具体的な手段としては、(1)各誘電
体を別々に焼結し、これを接着剤ではり合わせる、(2
)個々の誘電体の成形物を一体焼結させるなどが考案さ
れている。
On the other hand, as mentioned above, specific methods for combining dielectrics with different Curie points into one element include (1) sintering each dielectric separately and gluing them together with adhesive;
) Sintering of individual dielectric moldings together has been devised.

しかし、(1)の方法は素子の誘電特性に対して接着剤
の影響があり、壕だ製造コストが高くつく女どの理由か
ら実用化されていない。また(2)の方法は各誘電体間
の相互反応により個々の誘電体の特性が変化し、キュリ
一点における各誘電体の高誘電率が重畳される効果が得
られにくい。
However, method (1) has not been put to practical use because the adhesive affects the dielectric properties of the element and the manufacturing cost of the trench is high. Furthermore, in the method (2), the characteristics of each dielectric change due to the interaction between the dielectrics, making it difficult to obtain the effect of superimposing the high permittivity of each dielectric at one Curie point.

本発明は上記のような問題点を解決するために、キュリ
一点の異なる各誘電体を一体焼結させるとき、個々の誘
電体間に金属層を設けて各誘電体間の相互反応を阻止し
、しかもその金属層を枯層コンデンザの電極として利用
しようとするものである。
In order to solve the above-mentioned problems, the present invention prevents mutual reactions between the dielectrics by providing a metal layer between the individual dielectrics when sintering the dielectrics with different points. Moreover, the metal layer is intended to be used as an electrode for a dead layer capacitor.

丑だ、キュリ一点の異なるいくつかの誘電体を素子に使
用する場合、これらの誘電体のキュリ一点における誘電
率は、一般にそれぞれ異っている。
When several dielectric materials with different Curie points are used in an element, the dielectric constants of these dielectric materials at the Curie point generally differ from each other.

本発明では、各誘電体層に対する電極面積(S)とその
厚さくd)の比(S/d)を各誘電体のキュリ一点にお
ける誘電率の逆数に比例しだ大きさにすることにより、
上記の影響による素子の見かけの誘電率の変動を防ごう
とするものである。つまり一つの誘電体がキュリ一点を
示す温度では他の誘電体の誘電率はキーユリ一点を示す
誘電体の誘電率に比べて小さく、それらは同じレベルレ
こあるだめ、」二記のように各誘電体層の電極面積と厚
さの比を調節し、キュリ一点における各層の静電容量を
平均化することにより、素子としての静電容量の温度に
対する変動をより小さくすることが可能になる。
In the present invention, by making the ratio (S/d) of the electrode area (S) and its thickness d for each dielectric layer proportional to the reciprocal of the dielectric constant at one Curie point of each dielectric,
This is intended to prevent variations in the apparent dielectric constant of the element due to the above-mentioned effects. In other words, at a temperature where one dielectric material exhibits a single point, the permittivity of other dielectric materials is smaller than that of the dielectric material that exhibits a single point, and they must be on the same level. By adjusting the ratio of the electrode area and thickness of the body layer and averaging the capacitance of each layer at a single Curie point, it is possible to further reduce fluctuations in capacitance as an element with respect to temperature.

この場合の素子の見かけの誘電率は第(2)式で与えら
れる。
The apparent dielectric constant of the element in this case is given by equation (2).

ここでnは積層した誘電体の数。ε□+ Sm + d
mはそれぞれm層目の誘電体の誘電率、電極面積、厚さ
である。
Here, n is the number of laminated dielectrics. ε□+ Sm + d
m is the dielectric constant, electrode area, and thickness of the m-th dielectric material, respectively.

以上のように本発明は積層型コンデンサに対して、誘電
体を複合化し、見かけの誘電率を太きくし、その温度変
化を小さくする手法を応用しようとするものであり、そ
の複合化の具体的な手法に特徴がある。
As described above, the present invention attempts to apply a method of compounding dielectric materials to increase the apparent permittivity and reduce temperature changes to multilayer capacitors. It is characterized by its method.

次に本発明の積層型コンデンサ素子の構成について実施
例をもとに説明する。
Next, the structure of the multilayer capacitor element of the present invention will be described based on examples.

第1図は本発明の一実施例による積層型コンデンサの断
面を示し、第2図はこれに用いた誘電体の誘電率の温度
変化を示す。第1図において、1〜6は電極層で、7,
8はそれぞれ電極層1〜3と同4〜,6の引出し電極で
ある。キ、り一点の異なる誘電体9〜13は電極層1〜
6を介して積層し、誘電体9〜13と上下の電極層1〜
6からなる各層のコンデンサは回路上並列に結合した。
FIG. 1 shows a cross section of a multilayer capacitor according to an embodiment of the present invention, and FIG. 2 shows a temperature change in the dielectric constant of a dielectric material used therein. In FIG. 1, 1 to 6 are electrode layers, 7,
Reference numeral 8 represents the lead-out electrodes of electrode layers 1 to 3 and electrodes 4 to 6, respectively. The dielectrics 9 to 13 that differ from each other in one point are the electrode layers 1 to 13.
dielectrics 9 to 13 and upper and lower electrode layers 1 to 13.
The capacitors of each layer consisting of 6 were connected in parallel on the circuit.

14は基板層で、素子に機械的強度を/jえる。14 is a substrate layer that provides mechanical strength to the device.

第2図において、101〜105はそれぞれ誘電体9〜
13の誘電率の温度依存性を、また201〜2つ6はそ
れぞれ誘電体9〜13の誘電損失−δの温度依存性をそ
れぞれ示す。
In FIG. 2, 101 to 105 are dielectrics 9 to 105, respectively.
13 shows the temperature dependence of the dielectric constant, and 201 to 2 and 6 show the temperature dependence of the dielectric loss -δ of the dielectrics 9 to 13, respectively.

各誘電体層に対する電極面積(8)と各誘電体層の厚さ
くd)の比(s/d)は、第2図に示しだ各誘電体のキ
ュリ一点における誘電率の逆数の比に比例した大きさに
する。この場合、電極面積のみを変化させるか、誘電体
の厚さのみを変化させるか、あるいは電極面積、厚さと
もに変化させるかについては適宜選択できる。
The ratio (s/d) of the electrode area (8) for each dielectric layer and the thickness d) of each dielectric layer is proportional to the ratio of the reciprocal of the permittivity at one Curie point of each dielectric as shown in Figure 2. Make it the same size. In this case, it can be appropriately selected whether only the electrode area, only the dielectric thickness, or both the electrode area and thickness are changed.

第3図(〜、■)に各誘電体層の厚さを一定にし、電極
面積のみを変化させた場合の実施例の平面図を示す。2
0〜22は電極層を示し、それぞれ第1図に示した実施
例の電極層1〜3に対応する。
FIG. 3 (-, ■) shows a plan view of an embodiment in which the thickness of each dielectric layer is constant and only the electrode area is changed. 2
0 to 22 indicate electrode layers, and correspond to electrode layers 1 to 3 of the embodiment shown in FIG. 1, respectively.

23〜26も電極層で、これはそれぞれ第1図に示した
実施例の電極層4〜6に対応する。第1図の実施例の誘
電体層9〜13に対する電極面積はそれぞれ電極層20
と23、同23と21.同21と24と22.同22と
26の重なった部分であり、これらは誘電体層9〜13
のキュリ一点における誘電率6000,6500,70
00,7E500゜5oooの逆数に比例した大きさに
構成した。
23 to 26 are also electrode layers, which correspond to electrode layers 4 to 6 in the embodiment shown in FIG. 1, respectively. The electrode area for dielectric layers 9 to 13 in the embodiment shown in FIG.
and 23, 23 and 21. 21, 24 and 22. These are the overlapping parts of dielectric layers 9 to 13.
Dielectric constant at one Curie point of 6000, 6500, 70
The size is proportional to the reciprocal of 00,7E500°5ooo.

第4図に第2図に示した各誘電体を用い、第1図および
第3図に示しだ構造に作製した積層型コンデンザ素子の
見かけの誘電率εと誘電損失hnδの温度変化を示す。
FIG. 4 shows temperature changes in the apparent permittivity ε and dielectric loss hnδ of a multilayer capacitor element fabricated using each of the dielectrics shown in FIG. 2 and having the structure shown in FIGS. 1 and 3.

次に本発明の積層型コンデンザ素子の製造手順を具体的
に説明する。捷ず、誘電体の出発材料としては、B a
 T 103にB aNb206 をそれぞれ2.8モ
ル係、2.3モル係、1.8モル係、1.3モル係。
Next, the manufacturing procedure of the laminated capacitor element of the present invention will be specifically explained. As a starting material for the dielectric, B a
B aNb206 was added to T 103 in amounts of 2.8 mol, 2.3 mol, 1.8 mol, and 1.3 mol, respectively.

0.8モル係固溶した五種を用いた。これらの誘電体の
出発材料の粉末の仮焼および粉砕条件を調整し、焼成時
の膨張、収縮率を概略あわせた。この他、誘電体として
は実施例に挙げたBaNb2o6 の他に5rTi○3
+ BaTa2O6等をBaTlO3に固溶させたもの
を用いてもよい。また一つの素子の中に用いる誘電体は
実施例に挙げたようにBaT i○3に同一組成を固溶
させ、その固溶量のみを変えたものを用いると、焼成温
度等の条件がほぼ同一になるので望ましい。
Five kinds of solid solutions with a concentration of 0.8 mol were used. The conditions for calcination and pulverization of the powders of the starting materials for these dielectrics were adjusted to roughly match the expansion and contraction rates during firing. In addition to this, as a dielectric material, in addition to BaNb2o6 mentioned in the example, 5rTi○3
+ A solid solution of BaTa2O6 or the like in BaTlO3 may also be used. In addition, if the dielectric used in one element is a solid solution of BaT i○3 with the same composition as mentioned in the example, and only the amount of the solid solution is changed, the firing temperature and other conditions can be approximately the same. This is desirable because they will be the same.

電極部としてはAg、 Au、 Pd、 Pt 等から
なる導電性金属を用い、これも粒度組成等を調整して誘
電体層と焼成時の膨張、収縮率を概略あわせた。
A conductive metal made of Ag, Au, Pd, Pt, etc. was used for the electrode part, and its particle size composition and other properties were adjusted to approximately match the expansion and contraction rates during firing with the dielectric layer.

基板層は誘電体層と同じ系の固溶体を用いた。The substrate layer used the same solid solution as the dielectric layer.

これも仮焼および粉砕条件を調整し誘電体層と焼成時の
膨張、収縮率を概略あわせた。この他、基板層としては
誘電体層と焼成時の膨張、収縮率が概略等しい任意の累
月を用いればよいが、焼結温度等の条件から誘電体層と
同じ系の固溶体を用いるのが望捷しい。
The calcination and pulverization conditions were also adjusted to approximately match the expansion and contraction rates of the dielectric layer during firing. In addition, as the substrate layer, any material having approximately the same expansion and contraction rate during firing as the dielectric layer may be used, but due to conditions such as sintering temperature, it is recommended to use a solid solution of the same type as the dielectric layer. It's hopeful.

積層方法としては、」二記誘電体粉末に適当なバインダ
(ポリビニルアルコール、セルロースなト)と有機溶媒
(アルコール、エステルなど)を混合し、ペーストとし
たものを、ドクターブレード法でシート化し、これに電
極用金属粉末を上記同様バインダ、有機溶媒等を加えペ
ースト化したもの全印刷し、やはり−に記同様の方法で
ノート化した  ・基板層とともに積層し、熱圧着した
。このほか誘電体層基板層については印刷法によって積
層してもよい。これらは焼成炉によって焼成しく136
0℃、2時間)、さらに引出電極を印刷し再度焼成炉に
よって焼付けた(8oO℃、30分)。
The lamination method is to mix the dielectric powder mentioned above with an appropriate binder (polyvinyl alcohol, cellulose, etc.) and an organic solvent (alcohol, ester, etc.) to form a paste, which is then formed into a sheet using the doctor blade method. The metal powder for the electrode was added to the paste as described above with a binder, an organic solvent, etc., and the whole thing was printed, and a note was also made in the same manner as described in -. - It was laminated with the substrate layer and bonded by thermocompression. In addition, the dielectric substrate layer may be laminated by a printing method. These are fired in a firing furnace136
0° C., 2 hours), and then an extraction electrode was printed and baked again in a baking furnace (80° C., 30 minutes).

−4−記実施例より明らかなように、本発明は(1)誘
電体層を電極層を介して積層し、(2)各誘電体層の電
極面積と厚さの比を各誘電体のキュリ一点における誘電
率の逆数に比例した大きさにすることの二点に大きな特
徴がある。(1)によって各誘電体層を同時焼成した際
の、それらの間の化学反応を抑制し、各誘電体の誘電率
の温度変化曲線が変化することを防止し、さらに工程上
釜誘電体層の寸法精度の高い安定性を可能にし、素子の
見かけの誘電率が大きくその温度係数の小さい積層型コ
ンデンザ素子を馬え、また素子の小型化を可能にした。
As is clear from the example described in -4-, the present invention (1) laminates dielectric layers via electrode layers, and (2) determines the electrode area and thickness ratio of each dielectric layer. The two major features are that the size is proportional to the reciprocal of the dielectric constant at one Curie point. (1) suppresses the chemical reaction between the dielectric layers when they are fired simultaneously, prevents the temperature change curve of the dielectric constant of each dielectric from changing, and furthermore prevents the dielectric layer from changing during the process. This has made it possible to create a multilayer capacitor element with a large apparent dielectric constant and a small temperature coefficient, and it has also made it possible to miniaturize the element.

寸だ(2)によって積層型コンデンサ素子のみかけの誘
電率の温度変化をきわめて小さくすることを可能にした
By using (2), we have made it possible to minimize the temperature change in the apparent dielectric constant of a multilayer capacitor element.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の積層型コンデンザ素子の断
面図、第2図は本発明の積層型コンデンサ素子に用いる
キュリ一点の異なる誘電体の誘電率と誘電損失の温度変
化の一例をそれぞれ示す図、第3図(5)、■)は本発
明の他の実施例の積層型コンデンサの電極層の構造を示
す平面図、第4図は本発明の実施例の素子の見かけの誘
電率と誘電損失の温度変化を示す図である。 1〜6・・・・・電極層、7,8・・・・引き出し電極
、9〜13・・・・・誘電体層、14・・・・・・基板
層、20〜25・・・・・電極層。
Fig. 1 is a cross-sectional view of a multilayer capacitor element according to an embodiment of the present invention, and Fig. 2 is an example of temperature changes in the dielectric constant and dielectric loss of dielectric materials with different Curie points used in the multilayer capacitor element of the present invention. Figures 3(5) and 3) are plan views showing the structure of the electrode layer of a multilayer capacitor according to another embodiment of the present invention, and Figure 4 is a diagram showing the apparent dielectricity of the element according to the embodiment of the present invention. FIG. 3 is a diagram showing temperature changes in dielectric loss and dielectric loss. 1-6... Electrode layer, 7, 8... Extraction electrode, 9-13... Dielectric layer, 14... Substrate layer, 20-25...・Electrode layer.

Claims (1)

【特許請求の範囲】 一シ− (1)電極層と誘電体層を交互積層した積層型コンデン
ザ素子において、キュリ一点の異なる二種以」二の誘電
体を上記電極層を介して積層したこΣを特徴とする積層
型コンデンサ素子。 (2)各誘電体層に対する電極面積(S)と各誘電体層
の厚さくd)の比(S/d)を各誘電体のキュリ一点に
おける誘電率の逆数に比例しだ大きさにしたことを特徴
とする特許請求の範囲第1項に記載の積層型コンデンサ
素子。
[Scope of Claims] (1) A multilayer capacitor element in which electrode layers and dielectric layers are laminated alternately, in which two or more dielectrics having different Curie points are laminated with the electrode layers interposed therebetween. Multilayer capacitor element featuring Σ. (2) The ratio (S/d) of the electrode area (S) to the thickness d of each dielectric layer for each dielectric layer was made proportional to the reciprocal of the dielectric constant at one Curie point of each dielectric material. A multilayer capacitor element according to claim 1, characterized in that:
JP12694982A 1982-07-20 1982-07-20 Laminated condenser element Pending JPS5917229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12694982A JPS5917229A (en) 1982-07-20 1982-07-20 Laminated condenser element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12694982A JPS5917229A (en) 1982-07-20 1982-07-20 Laminated condenser element

Publications (1)

Publication Number Publication Date
JPS5917229A true JPS5917229A (en) 1984-01-28

Family

ID=14947877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12694982A Pending JPS5917229A (en) 1982-07-20 1982-07-20 Laminated condenser element

Country Status (1)

Country Link
JP (1) JPS5917229A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285968A (en) * 2004-03-29 2005-10-13 Kyocera Corp Glass ceramic multilayer wiring board with built-in capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285968A (en) * 2004-03-29 2005-10-13 Kyocera Corp Glass ceramic multilayer wiring board with built-in capacitor
JP4578134B2 (en) * 2004-03-29 2010-11-10 京セラ株式会社 Glass ceramic multilayer wiring board with built-in capacitor

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