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JPS59171131A - Method for testing semiconductor integrated circuit - Google Patents

Method for testing semiconductor integrated circuit

Info

Publication number
JPS59171131A
JPS59171131A JP509583A JP509583A JPS59171131A JP S59171131 A JPS59171131 A JP S59171131A JP 509583 A JP509583 A JP 509583A JP 509583 A JP509583 A JP 509583A JP S59171131 A JPS59171131 A JP S59171131A
Authority
JP
Japan
Prior art keywords
substrate
probe
integrated circuit
control system
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP509583A
Other languages
Japanese (ja)
Inventor
Kenji Togashi
健志 冨樫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP509583A priority Critical patent/JPS59171131A/en
Publication of JPS59171131A publication Critical patent/JPS59171131A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To increase the efficiency of measurement of the titled integrated circuit by a method wherein a plurality of probing needles, which can be selectively moved in vertical direction, are provided on a substrate in matrix form, said substrate is placed on the semiconductor wafer whereon a plurality of ICs are formed, and electric characteristics are tested by moving the desired probe needle using a control system and have the probe needle to come in contact with the IC chip. CONSTITUTION:The lower substrate 2-1, whereon a number of probe needles 3 which can be telescopically moved facing downward are provided in matrix form, is placed on the semiconductor wafer 1 whose electric characteristics are going to be tested. Then, the upper substrate 2-2 having a number of vertically movable press pins 4, to be used to push out the desired probe 3, is provided on the lower substrate 2-1, and the probe 3 is pushed out and brought to come in contact with the measuring point of the wafer 1 using a probe needle driving control system 5 through the intermediary of an air cylinder 7 and a pipe 8. Subsequently, the electric characteristics of the measuring point is measured using the measuring system 6 which is connected to the substrate 2-1.

Description

【発明の詳細な説明】 (a、)  全閉の技イホi分野 本発明は半導体集積1す1路の試験方法に係り特に半導
体・“ノーT−ハの電斌的特性検査試験方法に関するも
のである。
[Detailed Description of the Invention] (a) Field of Totally Closed Techniques The present invention relates to a test method for semiconductor integrated circuits, and particularly relates to a test method for inspecting the electrical characteristics of semiconductors. It is.

(い)技術の背は 一般に]じ9丁・STなどの半導体装置を製造す、B1
1稈において、−・枚の半導体ウコニハ十に多数個の半
導体装−f(チップ)を製造したのち、これらをチップ
ごとに切断する1)IJに、並設さ7Lだ個/!Ll’
、)チップが良品であるか不良品であるかf、 −1−
、、:l−ツクスルウェーハチ」ニック]二稈がある。
(b) The backbone of the technology is generally] B1, which manufactures semiconductor devices such as J9T and ST.
In one culm, a large number of semiconductor devices -f (chips) are manufactured on -1 sheets of semiconductor turmeric, and then these are cut into chips. 1) 7L pieces/! Ll'
,) Whether the chip is good or defective f, -1-
,, :l-Tuxuruwehachi” Nick] There are two culms.

(C)  従来技術と問題点 この上うなつニーハチ−1ニツクは、i常フパローバー
と呼ばれる装(IYにゾローブ力−Fを−18:続し、
1′ロープカーI・の探[1flJ体チップの所定?&
[(パッド)十に接触させた状態で’td(気的*lI
′!jt+チェックを行ない、以下)1)1次インデツ
クプ、移11111I、′C1)p設さノまた全チップ
について測定が行7tI−)れ−Cいる。
(C) Prior Art and Problems The above-mentioned knee hachi-1 technology is equipped with a device called I-Fupa Rover (IY followed by Zorob force-F-18:
1' Search for rope car I [1 fl J body tip prescribed? &
[(Pad) 'td (ki*lI) when in contact with the
′! jt+ check is performed, and the following) 1) Primary index, transfer 11111I, 'C1) p is set, and measurements are made for all chips in line 7tI-) and -C.

しかしながら半導体装置の多様化により、″−1′導体
素子のパターン及び千ンブ・」法も多様化の傾向にある
。そのためそれに対応して測定C(=使用さ7する)′
ローブカートの種類も増加して、作成−1′v1−プカ
ート黄用の増大と測定時におけるゾD −−)カードの
交換に手間がかかる問題があった。又同時にヌテーシ(
ウェーハを乗せている台)を少くとも半導体ウェーハ上
のチップ数/ζけイノブツクス移動させる必要があるた
め、時間がかがりイ1業11L率の悪い問題点がある。
However, with the diversification of semiconductor devices, the pattern of the "-1" conductor element and the 1,000-inch method also tend to become diversified. Therefore, correspondingly, measurement C (= used 7)'
The number of types of Robe Carts has also increased, resulting in an increase in the number of Robe Carts (1'v1-1'v1-Pu Cart Yellow) and the problem that it takes time and effort to replace cards during measurement. At the same time, Nuteshi (
Since it is necessary to move the table on which the wafer is placed by at least the number of chips/ζ on the semiconductor wafer, there is a problem in that it is time consuming and has a poor rate of work.

(・t)発明の目的 本発明の目的は、かかる問題点に此みなされたもので、
品種別にブ1.J−ブθ−ドを交換する必要がなく、か
−) −7’ vl−バーのチップに対応するインデッ
クス移動なしで能率よく一度に全チップを測定すること
ができ又、ウェーハ」二にナツプザイズの違う別品種も
一度に測定できる。半導体集積回路の試験書法の提供に
ある。
(・t) Purpose of the Invention The purpose of the present invention is to solve these problems,
Bu1 by variety. There is no need to replace the J-bar, and all chips can be efficiently measured at once without the corresponding index movement of the chips on the 7'vl-bar. Different varieties with different values can be measured at the same time. The purpose is to provide test documentation methods for semiconductor integrated circuits.

(0)発明の構成 その目的f達成する/Cめ、本発明の半導体集積回路の
試験書法は、選択的にF十にiJ動な複数の10−ブ釦
が一7トリツクス状しこ[11L!設された基板を、複
数の半導体集積回路が形成された半導体ウェーハ+に載
置し、制御系によって所望のプローブ針を選択的に上−
1−動させ各半導体集積回路のパッドに接触せしめて該
ミ1(導体集積回路の電気的特性を試験することを特徴
とする。
(0) Structure of the Invention To achieve the object f/C, the test writing method for semiconductor integrated circuits of the present invention is to selectively press a plurality of 10-buttons in a 17-tricks shape [11L ! The prepared substrate is placed on a semiconductor wafer+ on which a plurality of semiconductor integrated circuits are formed, and desired probe needles are selectively moved upward by a control system.
It is characterized by testing the electrical characteristics of the conductive integrated circuit by moving the conductive integrated circuit in contact with the pads of each semiconductor integrated circuit.

(f′)発明の実施例 1づ、下水発明の半導体集積回路の試験書法につい−C
1IX1面を呑1j(して1況明する。第1図は本発明
の一実施例の半導体集積回路の1バ験方法を説明−4る
ための模式的概略分解斜視図である。同図において]は
半導体ウェーハ、2−1fdl・部基板、2−2は1部
基板、3は下部基板に71リツクヌ状に配設されブこ−
1−不可動なプローブ針、・1・は下部基板に前記プロ
ーブ釧に対応して配設された[−: ’−1;−i+J
動な押えビン、5は10−バー装置内の)゛「l−ゾ釦
駆動制佑l糸、6は同じくプローバー装置内のY↓1.
気的特性γ11:]定糸、7はエアーシリンダー系、8
りA、パイプを示す。上記のようにtlI/i成され/
こ基板2を用いて半導体ウェーハ]の電気的特性を測定
すZ) (/i=は、第2図に示すごとく組会わされた
基板2をグU −7<−9に装着1.、該基板2 kヌ
フ−−ゾ1. (ン、、、l=に載置された」′導体ウ
ェーハ]、 −f=の所定位置(でセツトスる。次いで
崖導体ウェーハの品fliによって設定さtまたプ’C
iダラム力−1−′をプローブ♀1駆動制御系h K装
着す、nH1該プロクラムカードの重紙信号指令により
、エアーシリン、ター糸7及びバイブ8全介して半導体
ウェーハl−,l−にJl4成さ)7−た各チップのバ
ラi11 (第3図)に対応する所望の下部基板2−2
の押えビン4がエアー駆動によってトノjに移動し、第
3図に示すように下部基板2−1に配設さノまたプロー
ブ鎖3を下方に押して半導体ウェーハ1−1−に形成さ
れ/こ各チップのパッド11に接触する。次いで電気的
特性測定糸6によって、メテーシ10を移動することな
く各チップ。
(f') Embodiment 1 of the invention - Regarding the test writing method for semiconductor integrated circuits of the sewage invention -C
Figure 1 is a schematic exploded perspective view for explaining a one-test method for a semiconductor integrated circuit according to an embodiment of the present invention. ] is a semiconductor wafer, 2-1 is a semiconductor wafer, 2-2 is a 1-part substrate, and 3 is a lower substrate, which are arranged in a 71-round shape.
1-immovable probe needle, 1 is arranged on the lower board corresponding to the probe tip [-: '-1;-i+J
A dynamic presser pin, 5 is a thread in the 10-bar device, and 6 is a Y↓1 thread in the prober device.
Temperature characteristics γ11: ] Fixed thread, 7 is air cylinder system, 8
Figure A shows the pipe. tlI/i is made as above/
This substrate 2 is used to measure the electrical characteristics of a semiconductor wafer. The substrate 2 is set at a predetermined position of -f= (conductor wafer placed on the conductor wafer). P'C
i Durham force -1-' is applied to the semiconductor wafers l-, l- through the air cylinder, tar thread 7 and vibrator 8 by the heavy paper signal command of the nH1 program card attached to the probe ♀1 drive control system hK. The desired lower substrate 2-2 corresponding to the rose i11 of each chip (FIG. 3)
The presser pin 4 is moved to the top by an air drive, and as shown in FIG. It contacts the pad 11 of each chip. Each chip is then measured by the electrical property measuring thread 6 without moving the mesh 10.

の電気的特性を111μ次測だし、一度に全部各チップ
の特性がチェックさ第1る。各チップの電気的特性のチ
ェックが終了l〜/こならば、前記駆動制御系5によっ
て押えビン4・が1一方へ移動し、それに付なってプl
ll−グ釧3は、バ+12によつ−C半導体つ工−ハ1
上より離脱される。更eこ品神の異なつ/ζ21′導体
つJ−ハの゛itf気的特1/1ユを測定する場合には
、それに対応するノ°ログラノ、カードを駆動制御系5
に入れ替えることによ“りて、全く同様に所望のプロー
ブ針が該十導体つ−■−−ハ1−の各パッドに接触l、
で測定することが可能である。尚下記基板2は2分割さ
れず1体物と17で製作をれてもよい。
The electrical characteristics of each chip were measured 111μ times, and the characteristics of each chip were all checked at once. Once the electrical characteristics of each chip have been checked, the drive control system 5 moves the presser pin 4 to one side, and
ll-G 3 is attached to B+12-C semiconductor tool-H1
It is detached from above. Furthermore, when measuring the 1/1 unit of the ``ITF'' characteristic of the ζ21' conductor, the corresponding controller and card are connected to the drive control system 5.
By replacing the probe needles with 1 and 1, the desired probe needles are brought into contact with each pad of the 10 conductors in exactly the same way.
It is possible to measure by Note that the substrate 2 described below may be manufactured as a single unit 17 without being divided into two parts.

(/υ 41・、明の効宋 以十説1明し/Cごと< −i\光明の半導体集積回路
の試験書法によhけ、品種別によるグt1−ツカ Iの
装着が妃・要なく、該)′ローブカー1−の費用が節約
され、かつメゾーシは各J−ッグに苅するインデックス
移動の必認がなく、測定t1..li間の短縮が川「1
しとなり、又1つJ−ハ上にヂツプリイズの」tう別品
種も一度に測定ができ能率向上にPi’ L <寄り、
するものである。尚木実施例は一例としてあItf l
こものであり本発明の範囲を制限するもので(・:1な
い。
(/υ 41・、Effectiveness of the Ming Dynasty since the Sung dynasty. This saves the cost of the lobe car 1-, and there is no need to move the index to each J-g, and the measurement t1. .. The shortening between li is the river “1
In addition, it is possible to measure different types of products at the same time by placing one on top of the J-Ha, which improves efficiency.
It is something to do. The Naoki embodiment is an example.
This does not limit the scope of the present invention (・:1).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の半導体用hT回1洛の試験
書法を説明するだめの模式的椴、略分9pl斜視1ヌ1
、第2図は、児;板2をプローバーに装j賞シた誇1.
明をする為の一部断面斜視図、第3図はツ°11 −プ
釧の駆動機構を説明するだめの一部1υi i’、Ni
斜祝しlである。 図において、1は半導体ウェーハ、2←1、爪板、:3
tまプローブ 動制御系、6(弓−’;43:気的特性測定系、7は一
Lアーシリンダー糸、8はバイブ、9 idソ°l」−
バー、] 0はヌデージ、Jlはバット、1.2fd、
ハネを示す。
FIG. 1 is a schematic diagram for explaining the test method for semiconductor hT times 1 according to an embodiment of the present invention, approximately 9 pl, perspective view 1 nu 1
, Figure 2 shows the result of mounting board 2 on a prober.
A partially sectional perspective view for clarity, and Fig. 3 shows a part 1υi i', Ni
It's a diagonal congratulations l. In the figure, 1 is a semiconductor wafer, 2←1, nail plate, :3
tma probe movement control system, 6 (bow-'; 43: air characteristic measurement system, 7 one L cylinder thread, 8 vibe, 9 id so °l'-
Bar,] 0 is Nudage, Jl is Butt, 1.2fd,
Show the wings.

Claims (1)

【特許請求の範囲】[Claims] 選択的に11−にl+J動な複数のブローゾ釧がマトリ
ックス状に配設された基板を、複数の半導体集積回路が
形成さ!1フこ半導体ウニハトに載置し、制御系に、L
1〕て所望の10−プ釧を選択的に上ト動させ各半導体
集積回路のパッドに接触せしめて該゛1イ導体集積回路
の電気的特性を試験することを特徴とする半導体集積回
路の試験方法。
A plurality of semiconductor integrated circuits are formed on a substrate on which a plurality of Brozots having l+J motion are selectively arranged in a matrix in 11-! Place it on a semiconductor unihat, and connect it to the control system.
1] Testing the electrical characteristics of the 1-conductor integrated circuit by selectively moving a desired 10-pocket up and bringing it into contact with a pad of each semiconductor integrated circuit. Test method.
JP509583A 1983-01-13 1983-01-13 Method for testing semiconductor integrated circuit Pending JPS59171131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP509583A JPS59171131A (en) 1983-01-13 1983-01-13 Method for testing semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP509583A JPS59171131A (en) 1983-01-13 1983-01-13 Method for testing semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS59171131A true JPS59171131A (en) 1984-09-27

Family

ID=11601822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP509583A Pending JPS59171131A (en) 1983-01-13 1983-01-13 Method for testing semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS59171131A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220347A (en) * 1985-03-26 1986-09-30 Rohm Co Ltd Measurement of characteristics of semiconductor device
JPS63207146A (en) * 1987-02-23 1988-08-26 Nec Corp Probe card
JPH03185847A (en) * 1989-12-15 1991-08-13 Toshiba Corp Universal probe card
US5055780A (en) * 1989-03-09 1991-10-08 Mitsubishi Denki Kabushiki Kaisha Probe plate used for testing a semiconductor device, and a test apparatus therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220347A (en) * 1985-03-26 1986-09-30 Rohm Co Ltd Measurement of characteristics of semiconductor device
JPS63207146A (en) * 1987-02-23 1988-08-26 Nec Corp Probe card
US5055780A (en) * 1989-03-09 1991-10-08 Mitsubishi Denki Kabushiki Kaisha Probe plate used for testing a semiconductor device, and a test apparatus therefor
JPH03185847A (en) * 1989-12-15 1991-08-13 Toshiba Corp Universal probe card

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