JPS59169257A - Phase control circuit for burst signal - Google Patents

Abstract

PURPOSE:To eliminate the effect of variation of the burst time and to attain a normal operation with a phase locked characteristic by providing a frequency control means containing an ON/OFF control function to a phase locked loop which is formed in response to the burst type signal input. CONSTITUTION:The intermittent phase error signal produced in response to the burst type signal input is compared with a prescribed reference level through binary identifying circuits 17-21. Then binary level signals are produced from these circuits 17-21. A generating circuit 25 produces another prescribed binary level signal with the binary level signals produced from the circuits 17-21 used as triggers. Then frequency control circuits 26-28 supply the prescribed binary level signals and produce the frequency control signals to the voltage control oscillator via an integrating function. As a result, the oscillation frequency of the voltage control oscillator is always controlled normally to the input carrier wave regardless of the variance of the burst time. Thus the normal function is secured to the demodulation characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase control circuit for burst signals, and in particular uses a carrier wave of a burst signal as a reference signal.

This invention relates to improvements in a burst signal phase control circuit that generates a frequency control signal for a voltage controlled oscillator included in a phase locked loop.

For example, the time division multiple connection blade QTime Divisio
nMultiple Access: TDMA for short
In satellite communication systems, etc., which transmit information only during predetermined time slots, corresponding to the stations participating in this communication system, a burst communication system is used. The advantages of this communication system are that it can effectively form a TDMA system that connects a large number of earth stations using the same seven communication satellites and the same frequency band, and that the power consumption required for information transmission VC can be reduced. be.

Conventionally, in the TDMA system using such a burst communication system, for example, in the case of the above-mentioned satellite communication system, in order to demodulate the burst-like phase modulation signal in the participating earth station equipment, the first The main parts are shown in the figure and FIG. A phase demodulator including a burst signal phase control circuit as a component is used.

The conventional phase demodulator H4 phase PSK (Phas
This is one example of the application of the phase control circuit for burst signals of the present invention in the case of 8-hift keying (e.g. Only the main points relevant to explaining the operation of the invention will be described.

The burst-like four-phase signal P8 input from the terminal 101 is inputted to the phase detectors 1 and 2VC, and the inverse modulator 3Vc, where the carrier wave is regenerated through the inverse modulation effect and frequency converted. The signal is sent to the device 4. In the frequency converter 4,! The oscillation output of the pressure-controlled oscillator 9 and the regenerated carrier wave are mixed, the frequency of this regenerated carrier wave is converted, and is inputted to the frequency converter 7 via the delay circuit 5 and the bandpass filter 6. This delay circuit 5 does not necessarily include a specific delay circuit.

The delay time and the like in the circuit including the amplifier, amplitude limiting circuit, and bandpass filter 6yk corresponding to the illustrated positions are collectively expressed. In the frequency converter 7, the oscillation output of the voltage controlled oscillator 9 and the output of the bandpass filter 6 are mixed to generate a reference signal corresponding to the carrier frequency. Phase detector IVC
The other is directly supplied to the phase detector 2VC.

The phase detectors 1 and 2Vc receive all of the reference signals, synchronously detect the burst-like phase modulated signal, and output it from terminals 102 and 103, respectively.

The phase detection outputs output from the phase detectors 1 and 2 are input to the burst signal phase control circuit 10 on the other hand. These two phase detection outputs are shown as el and e2 in FIG. Burst signal phase control circuit 10t! , are input to these phase detection outputs e1 and 62 to generate frequency control signal voltages e, , t- for controlling the oscillation frequency of the voltage controlled oscillator 9, and send them to the voltage controlled oscillator 9.

This frequency control signal voltage is a frequency control voltage generated corresponding to the relative phase difference between the carrier wave of the phase modulation signal inputted from the ecUh terminal 101 and the oscillation output of the voltage controlled oscillator 90, and this control voltage ee As a result, the oscillation frequency of the voltage controlled oscillator 9 is controlled and adjusted, and its frequency and phase are automatically controlled so as to be always in phase synchronization with the carrier wave of the twisted phase modulation signal input. In the phase demodulation device shown in Fig. 1, the deterioration of the custom-made phase demodulation caused by the carrier frequency fluctuation in the burst-like phase modulation signal input can be eliminated by forming a phase-locked loop as described above. Yosi.

Automatically corrected0 In the conventional phase demodulator shown in FIG.

As the burst signal phase control circuit 1O included as one of its constituent elements, a phase control circuit, the main part of which is shown in FIG. 2, for example, has conventionally been used. In FIG. 2, the phase detection signals e1 and e2 are output from terminals 1.04 and 105, respectively. These el and e2H are input to an adder 11 and a subtracter 12, and signals corresponding to e1+e2 and el-e2 are outputted, respectively, and multiplied by a 1 multiplier 13. Further, e1 and e2rl;c are multiplied in the multiplier 14rC, and the outputs of the multipliers 13 and 14 are both multiplied by the multiplier 14rC.
5 is input and multiplied.

-□□□- The output is output from the terminal 106 as the frequency control signal voltage ec through the peak hold circuit 16t-.

Looking at the case where the phase modulation signal input is a 4-phase PSK signal, the above e1 and e2'C are expressed by the following equation: Signal carrier wave and voltage controlled oscillator 9
The phase difference (in radians) between the output and the 0 oscillation output is nut and an integer of 2. For the above el and e2, the 1 multiplier 15 outputs a phase error signal voltage E corresponding to a linear equation as O in the phase error Δθ.

E=ni・(△θ) (K: number of feet) However, since the input signal to the 5-phase demodulator is a burst PSK signal, the frame periodic tone Tf of the above-mentioned signal is assumed, and the burst time is Tli T2.
and T3, the time waveform of E and the frequency control signal voltage e outputted via the peak hold circuit 16,
1 (i = 1, 2, 3). The peak hold circuit 16 is a charging/discharging circuit consisting of a normal detector, a resistor, a capacitor, etc., and in a steady state, as shown in FIGS. 3(a), (b) and (C1),
Burst time T1. Corresponding to T2 and T3, respectively, the average output voltage, i.e. the frequency control signal voltage eel
Output ee2 and ewa3. Obviously KT 1<T
2 < T 3vc compatible -cm eFl(eezkue
. It becomes 3.

Therefore, in the conventional burst signal phase control circuit, the voltage level of the frequency control signal to the voltage controlled oscillator changes as the burst time changes, and therefore,
In the case of the burst signal phase control circuit used in the phase demodulator shown in FIG. Therefore, in a phase-locked loop formed using the carrier wave of the input 4-phase PSK signal as a reference signal, the loop gain changes to 4-phase P8 depending on the burst time of the signal, and as a result, This burst-like four-phase P8 impedes the phase synchronization of the voltage controlled oscillator 9 for signal demodulation, and becomes a factor that deteriorates the demodulation characteristics of the phase demodulation device itself.

In the above description, the operation of a conventional burst signal phase control circuit as a component of a phase demodulation device corresponding to a burst-like phase modulation signal in the TDMA system has been described. In a phase control circuit, generally speaking, in a phase locked loop that includes this phase control circuit for burst signals as a component, output from the phase control circuit for burst signals is generated in response to fluctuations in the burst time of a burst signal input. . 9. The frequency control voltage for the pressure-controlled oscillator changes, making it impossible to always maintain the loop gain of the phase-locked loop at an appropriate value.9. This has the drawback of degrading the phase locking of the phase locked loop and, as a result, impairing the phase locking function of the voltage controlled oscillator that is synchronized to the carrier wave of the burst signal input.

The object of the present invention is to eliminate the above-mentioned drawbacks, and to always generate a proper frequency control signal for a voltage controlled oscillator, regardless of the burst time, from an intermittent phase error signal generated corresponding to the burst time. An object of the present invention is to provide a phase control circuit for burst signals.

The burst signal phase control circuit of the present invention functions as a component of a phase locked loop formed in response to a burst signal input, and generates a frequency control signal for a voltage controlled oscillator included in the phase Pj lA loop. A phase control circuit for a burst signal generates a first binary signal by comparing an intermittent phase error signal generated in response to the burst signal input with a predetermined reference level. an identification circuit; a generation circuit that generates a predetermined second binary bell signal using the first binary bell signal as a trigger; and a frequency control circuit that generates a frequency control signal for the voltage controlled oscillator.0 Below, the present invention will be explained in detail with reference to the drawings.〇Figure 4μMain parts of an embodiment of the present invention In FIG. 4, which is a block diagram showing this embodiment, the burst signal phase control circuit of the present invention, which refers to this embodiment, includes an adder 17, a subtracter 18, multipliers 19, 20, and 21, ! Pressure comparison circuit 22. A binary discrimination circuit including a reference voltage generation circuit 23 and a slicer 24, and a one-shot trigger circuit 25Vc
and a second binary bell signal generation circuit formed by the following.

An embodiment of the present invention shown in FIG. 4, which is equipped with a reversible counter 261, an oscillator 27, and a frequency control circuit including a D-'A converter 28, is capable of controlling the burst phase modulation signal in the TDMA system described above. Corresponding phase adjustment & (
An example of the application of the present invention as an improvement means to an example of a conventional burst signal phase control circuit (see FIG. 2) applied as a component of a phase control circuit (see FIG. 4) will be shown.

In FIG. 4, the aforementioned phase detection outputs e1 and e2 are input to terminals 107 and 108, respectively.

From this el and e2, adder 17. The operation of generating phase error signal voltage E via subtracter 18 and multipliers 19, 20 and 21 is the same as in the conventional example shown in FIG. This phase error signal voltage E is inputted to the voltage comparison circuit 22, and with reference to a predetermined reference voltage vr generated in the reference voltage generation circuit 23 and inputted to the voltage comparison circuit 22, The phase error signal voltage corresponding to Vr is determined as H (high) level, the phase error signal voltage corresponding to E≦Vr is determined as iL (low) level, and the first 2-value is determined. A level signal is generated and output to the one-shot trigger circuit 25. FIG. 5(a) shows the correspondence between the phase error signal voltage outputted from the 1 multiplier 21 and compared with a predetermined reference level and the reference voltage Vr, and FIG. 5(b)
2 shows the first binary bell signal input to the one-shot trigger circuit 25I/c. In FIG. 5(a), Tf and T represent the frame period and burst time of the burst signal, respectively, as described above.

The one-shot trigger circuit 25 which inputs the first binary bell signal as a trigger uses a monostable multivibrator, for example, and receives a trigger signal input via a resistor and a capacitor with a predetermined time constant from the Tf. It therefore has the ability to hold at the foot level for a larger predetermined period of time.

In response to the first binary bell signal inputted from the slide t24, the one-shot trigger circuit section outputs a second binary bell signal shown in FIG. 5(C)K. That is, the one-shot trigger circuit 25 outputs the frame period Tf and burst time T of the burst signal.
Regardless of the length of , a second binary bell signal corresponding only to the first binary bell signal is output and input to the reversible converter 26 . As mentioned above, in the 1-lol example, Ha, 1! Frequency control times F for pressure controlled oscillators! Six,
Reversible counter 26, two oscillators 27, and DA converter 28
The second binary bell signal from the one-shot trigger circuit 25 is input to the reversible counter 26, and the reversible counter 26 receives a clock signal of frequency f from the oscillator 27. .

Counting in both directions of up and down in response to both the H and [L levels of the second binary bell signal,
It is output to the DA converter 28. The DA converter 28 inputs this counter output, performs DA conversion, and outputs it as a frequency control signal voltage e0 at a terminal 109. As shown in FIG. 5(d), at the output voltage of the J)-A converter 28 corresponding to FIGS. 5(a), (b), and (C), the frequency control signal voltage ec is.

As shown in the figure, 1! It can be seen that the voltage V c O is formed as a frequency control voltage for the voltage controlled oscillator as a center voltage. Obviously, this phase-locked loop constitutes an on-off control system that targets one phase synchronization, and various constants related to the binary discrimination circuit, one-shot trigger circuit 25, and frequency control circuit described above are set appropriately. By selecting , it is possible to always maintain the phase lock customization of the phase lock loop normally, regardless of the length of the burst time of the four-phase PSK signal input. Therefore, the first frequency control voltage corresponds to the relative phase error between the carrier wave of the burst-like four-phase P8 signal and the oscillation output of the voltage-controlled oscillator included in one phase-locked loop, as shown in FIG. In the phase demodulator 1iVc, the voltage controlled oscillator 9
It is clear that the rooting frequency of is always properly controlled in response to the input carrier, regardless of burst time variations, and that the demodulation percentage of the phase demodulator functions normally.

Next, a case will be described in which the above embodiment of the present invention is applied to another phase demodulation device.

FIG. 6 is a block diagram showing the main parts of the phase demodulation device when the present invention is applied to a phase demodulation device using another method. This phase demodulation device ah is an example of a phase demodulation device that is said to be a frequency multiplication type for a four-phase P8 signal, and an embodiment of the present invention described above with reference to FIG. 2 is shown in FIG. A burst signal phase control circuit 39 is included as a component of the phase demodulation device.

To briefly explain the phase demodulation operation of the phase demodulator shown in Fig. 6, the 4-phase PSK input from terminal 1'I
The signal is branched into two and sent to phase detectors 29 and 30Vc, and on the other hand is input to a single frequency multiplier 31 where it is multiplied by 4, output as a non-modulated signal, and input to a frequency converter 32. In the frequency converter 32, the output of the voltage controlled oscillator 380 and the non-modulated signal are mixed, the frequency of this non-modulated signal is converted, and the signal is passed through the delay circuit 53 and the bandpass filter 34 to the frequency converter 3.
5 is input. This delay circuit 33 is I'1m as in the case of the above-mentioned phase demodulation device of FIG. 1, and a specific delay circuit is not necessarily inserted therein.

Amplifiers, amplitude limiting circuits, and bandpass filters corresponding to the illustrated positions (34" ft): Delay circuits, etc. in the included circuits are collectively represented. In the frequency converter 35, the oscillation output of the voltage controlled oscillator 38 and the bandpass filter 3
A reference signal having a frequency corresponding to the frequency of the non-modulated signal, that is, four times the carrier frequency of the 4-phase PSK signal is generated by mixing the output of the 4-phase PSK signal and the output of the 4-phase PSK signal, and is input to the 1-channel splitter 36. The frequency division i EI Zi - 10,000 tffH is supplied to the phase detector 29 via the phase shifter 37 , and the other is supplied directly to the phase detector 30 . The phase detectors 29 and 30 respectively input the reference signal and synchronously detect the burst-like four-phase P8 signal input from the terminal 110, and output the respective phase detection signals from the terminals 111 and 112. , and in -10,000, these phase detection outputs are m
Burst signal phase control circuit 39 as el and e2
The operation input to the phase demodulator is the same as that of the phase demodulator shown in FIG. Further, these phase detection outputs el and e2 are inputted to the burst signal phase control circuit 39 to generate a one-frequency control signal voltage ee, control and adjust the oscillation frequency of the voltage controlled oscillator 38, and output the two-phase detectors 29 and 30. Regarding the function of forming a phase-locked loop consisting of an on-off control system including such as This is exactly the same as applying the non-inventive embodiment to the device.

Note that in the above description, one embodiment of the present invention has been described in the case where it is applied to the two phase demodulators shown in FIG. 1 and FIG. 6, but as an example of application of the present invention,
The present invention is not limited to these phase demodulators, but the present invention is not limited to these phase demodulators.

For example, it goes without saying that the present invention can be applied to phase demodulators that handle burst phase modulated signals that have various phase synchronized detection functions, including modulator plate type phase demodulators that include voltage controlled oscillators. In addition, the phase demodulation device described above is used not only in the field of communications, but also in areas such as radar navigation systems and measurement control, where the carrier wave of a burst signal is used as a reference signal and the reproduction processing of a signal synchronized with this is used. Of course, the present invention can be effectively applied in this regard.

As explained in detail above, one aspect of the present invention is to provide a frequency control means having an on/off control function for a phase-locked loop formed in response to a burst signal input. without being affected by time fluctuations.

There is an advantage that the phase lock customization of the phase lock loop can always be operated normally.

[Brief explanation of drawings]

Figure 1 shows the main parts of an example of a 1-phase demodulator to which the invention is applied as a component, and Figure 2 shows an example of a conventional phase control circuit for burst signals. Fig. 4 is a block diagram showing the main parts of an embodiment of the present invention; Fig. 5(a), b), (C) and (d)
T! The operational waveform diagram in one embodiment of the present invention and FIG. 6 respectively apply the present invention as a component. FIG. 3 is a block diagram showing the main parts of another example of a phase demodulation device. In the figure: 1. 2. 29. 30... Phase detector, 3... Inverse modulator, 4. 7. 32.
35...Frequency converter, 5.33...Delay circuit, 6
．． 34...Band filter, 8.37...-phase shifter, 9.38...Voltage controlled oscillator, 10.39...
Burst signal phase control circuit, 11.17... Addition circuit, 12.18... Subtraction circuit, 13. 14.
15. 19. 20.21... Multiplier, 16...
Peak hold circuit, 22... Voltage comparison circuit, 23.
...Reference voltage generation circuit, 24...Slicer, 25...
・One spot trigger circuit, 26... Reversible counter, 27... Excavator, 28... D-A converter, 31
... Frequency multiplier, 36... Frequency divider.

Claims (1)

[Claims] In a burst signal phase control circuit that functions as a component of a phase-locked loop formed in response to a burst-shaped signal input and generates a frequency control signal for a voltage-controlled oscillator included in the phase-locked loop, the burst-shaped a binary discrimination circuit that generates a first binary signal by comparing an intermittent phase error signal generated in response to a signal input with a predetermined reference level; a generation circuit that generates a predetermined second binary bell signal as a signal trigger; and a frequency control circuit that inputs the second binary bell signal and generates a frequency control signal for the voltage controlled oscillator through an integral action. 1. A phase control circuit for burst signals, comprising: a circuit.