JPS59168707A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- JPS59168707A JPS59168707A JP4173083A JP4173083A JPS59168707A JP S59168707 A JPS59168707 A JP S59168707A JP 4173083 A JP4173083 A JP 4173083A JP 4173083 A JP4173083 A JP 4173083A JP S59168707 A JPS59168707 A JP S59168707A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- circuit
- time
- modulation signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/0009—Time-delay networks
Landscapes
- Networks Using Active Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は、ＦＭ変調信号をその周期の数十〜数百倍遅延
さすことが出来る遅延回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a delay circuit that can delay an FM modulation signal by several tens to hundreds of times its period.
（ｂ） 従来技術と問題点
従来の遅延回路としては、ケーブルを使用するものがあ
るが、これは遅延時間が大刀信号周期の数倍位迄は遅延
さすことが出来るが、それ以上になるとケーブル長が膨
大となり実現が困難になる欠点がある。又ＦＭｆ調信号
を一旦復調して遅延させ再度変調する方法があるが、こ
の方法では復調及び再度変調することで出方ＦＭ変調信
号と入力ＦＭｉ調信号との間に誤差が生じる欠点がある
。(b) Conventional technology and problems Some conventional delay circuits use cables, which can delay the delay time up to several times the period of the Tachi signal, but if the delay is longer than that, the cable is used. The drawback is that the length is enormous, making it difficult to realize. There is also a method of demodulating the FMf modulation signal, delaying it, and modulating it again, but this method has the disadvantage that an error occurs between the output FM modulation signal and the input FMi modulation signal due to the demodulation and remodulation.
尚又水晶フィルタ、表面弾性波フィルタ等を通過させて
遅延さす方法があるが、この方法ではフィルタによって
遅延時間が定ってしまい可変さすことが困！＠な欠点が
める。There is also a method of delaying the signal by passing it through a crystal filter, surface acoustic wave filter, etc., but with this method, the delay time is fixed depending on the filter and it is difficult to vary it. ＠I blame the flaws.
（ｅ） 発明の目的
本発明の目的は上記の欠点に鑑み、小形で、誤差もなく
、ＦＭ変調信号を、その周期の数十〜数百倍の希望する
時間容易に遅延さすことが出来る遅延回路の提供にある
。(e) Object of the Invention In view of the above-mentioned drawbacks, the object of the present invention is to provide a delay that is compact, has no error, and can easily delay an FM modulation signal by a desired period of time several tens to hundreds of times its period. It is in providing the circuit.
（ｄ） 発明の構成
不発明は遅延線を使用することにより比較的長い時間を
遅らせるようにするものである。一般的に遅延線での遅
延量は立上り時間の１０倍程度迄であるため、そのまま
では長い遅延量が得られない。そこで不発明は上記の目
的を達成するために、人力ＦＭＫ調信号の周波数を１／
Ｎに分周した後、周波数が低りことで相対的に長い遅延
量がとれる遅延線を通し入力ＦＭ変調信号の周期の数十
〜数１１、倍遅延させ、その後Ｎ逓倍５を通して再度大
刀ＦＭ変調信号と同じ周波イタに変換することを性徴と
する。(d) Construction of the Invention The non-invention is to delay a relatively long time by using a delay line. Generally, the amount of delay in a delay line is up to about 10 times the rise time, so a long amount of delay cannot be obtained as is. Therefore, in order to achieve the above purpose, the invention was designed to reduce the frequency of the human-powered FMK tone signal by 1/1.
After dividing the frequency into N, it is passed through a delay line that can take a relatively long delay due to the low frequency, and is delayed by several tens to eleven times the period of the input FM modulation signal, and then passed through N multiplication 5 and output again to the Tachi FM. The sexual characteristic is that it converts to the same frequency as the modulated signal.
（ｅ） 発明の実施クリ 以下本発明の１実砲例につき図に従って説明する。(e) Implementation of the invention An example of an actual gun of the present invention will be explained below with reference to the drawings.
化１図は本発明の実施例の遅延回路のブロック図、第２
図は第１図の各部の波形のタイムチャートで（Ａ）〜ｃ
Ｆ）Ｉｉｍｒ１図のａ−ｆ点に対応している。Figure 1 is a block diagram of a delay circuit according to an embodiment of the present invention, and Figure 2 is a block diagram of a delay circuit according to an embodiment of the present invention.
The figure is a time chart of the waveforms of each part in Figure 1 (A) to c.
F) Corresponds to points a-f in the Iimr1 diagram.
図中１は方形波変換回路、２！″ｉＮ分周器、３は遅ｉ
ｒｇ４）、４ ｒ、ｔ Ｎ Ａ 倍ｐｓ、ｓｌｄ［ｉ’
域５ｈｉＦＡＰＫＲＤ （以下ＢＰＦと称す）である、
動作を説明すると、第２図（イ）に示す如きＦＭ変調信
号は方形変換１［！１ドＳｌにより第２図（Ｂ）に示す
如き方形波形に変換ざ鎚、Ｎ分周器２にて周波数は１／
Ｎに分周され第２図（Ｃ）に示す如き周期の長い方形波
となる。この波形は周波数が低いこ亡で相対的（ｔこ長
い遅延娃がとれる遅延線３により入力ＦＭ笈制信号の周
期のば千１音〜数百倍の時間τだけ遅延され詔２図（２
）に示す如き時間τだけ遅延した第２、Ａ（Ｄ）に示す
如き方形波となりＮ逓倍器４に入力する。Ｎ逓倍器４で
は入力した方形波をＮ逓倍して入力ＦＭ変調信号と同じ
周波数の方形波とするがこの方形波は第２図（Ｅ）に示
す如く時間τだけ遅延している。この時間τだけ遅延し
た方形波をＢＰＦ５全通して不要信号を取り除けば第２
図■に示す如き時間τだけ遅延した元のＦＭ変調信号が
得られる。勿論所望時間遅延さすように遅延線を調整す
ればＦ’Ｍ変調信号の周期の数十倍から数百倍の遅延時
間を容易に得ることが出来るし又出力ＦＭ変調信号は誤
差を生ずることもなく、又各回路及び遅延線３は小形な
もので得られる。In the figure, 1 is a square wave conversion circuit, 2! "iN frequency divider, 3 is slow i
rg4), 4 r, t N A times ps, sld[i'
To explain the operation, the FM modulated signal as shown in FIG. 2 (a) undergoes rectangular transformation 1[! The waveform is converted into a rectangular waveform as shown in Fig. 2 (B) using the 1-channel de-sl, and the frequency is reduced to 1/1 by the N frequency divider 2.
The frequency is divided into N, resulting in a square wave with a long period as shown in FIG. 2(C). This waveform is delayed by a time τ, which is between 1,000 to several hundred times the period of the input FM control signal, due to the delay line 3, which has a relatively long delay due to the low frequency.
) is delayed by the time τ as shown in FIG. The N multiplier 4 multiplies the input square wave by N to produce a square wave having the same frequency as the input FM modulation signal, but this square wave is delayed by a time τ as shown in FIG. 2(E). If the square wave delayed by this time τ is passed through the BPF5 and unnecessary signals are removed, the second
The original FM modulated signal delayed by the time τ as shown in FIG. Of course, by adjusting the delay line to provide a desired time delay, it is possible to easily obtain a delay time that is several tens to hundreds of times the period of the F'M modulation signal, and the output FM modulation signal may have errors. Moreover, each circuit and the delay line 3 can be made small.
（ｆ） 発明の効果
以上）ｆ細に説明する如く本発明によれば、小形で、誤
差もなく、ＦＭ変調信号を、その周期の数十〜数百倍の
時間容易に遅延さすことが出来る効果がある。(f) Effects of the Invention and More) As described in detail, according to the present invention, it is possible to easily delay an FM modulation signal by several tens to hundreds of times the period of the FM modulation signal without any error. effective.
第１図は本発明の実施例の遅延回路のブロック図、第２
図は第１図の各部の波形のタイムチャートでるる。
図中１は方形波変換回路、２はＮ分周器、３は遅りｌ線
、４ばＮ逓倍器、５は惜戦通過ｌ゛波器を示す。FIG. 1 is a block diagram of a delay circuit according to an embodiment of the present invention, and FIG.
The figure is a time chart of the waveforms of each part in FIG. In the figure, 1 is a square wave conversion circuit, 2 is an N frequency divider, 3 is a lagging l line, 4 is an N multiplier, and 5 is a narrow pass l waver.
Claims (1)
力周波数を１／Ｎに分周する分周回路と、この分周回路
の出力を遅延さす遅延素子と、この遅延された出力ｔＮ
逓倍する逓倍回路とにより構成されることを特徴とする
遅延回路。A circuit that converts an FM modulation signal into a square wave, a frequency divider circuit that divides the output frequency of this circuit into 1/N, a delay element that delays the output of this frequency divider circuit, and this delayed output tN.
A delay circuit comprising a multiplier circuit that performs multiplication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4173083A JPS59168707A (en) | 1983-03-14 | 1983-03-14 | Delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4173083A JPS59168707A (en) | 1983-03-14 | 1983-03-14 | Delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59168707A true JPS59168707A (en) | 1984-09-22 |
Family
ID=12616538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4173083A Pending JPS59168707A (en) | 1983-03-14 | 1983-03-14 | Delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59168707A (en) |
-
1983
- 1983-03-14 JP JP4173083A patent/JPS59168707A/en active Pending
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